JP3316227B2 - Memory access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method for a memory having a high-speed access mode for realizing a high-speed memory access.

[0002]

2. Description of the Related Art A processor (upper device) for controlling access to a memory outputs an address for specifying a memory access position. When a memory is managed in units of a plurality of partitions (pages), the processor outputs an upper address for designating a page and a lower address for designating an area in the page at the time of access, and sets them in the memory. . In recent years, when the same page is continuously accessed, only the lower address is newly set in the memory, and the upper address is newly set as the upper address by using the previously set and held address. Omit
A memory control system having a high-speed access mode for increasing the access speed has been constructed. Here, the operation method of the memory control system having the high-speed access mode, that is, the memory access control method will be described.

FIG. 2 shows a block diagram of a conventional general memory control system. Memory control system S shown in FIG.
Are a processor (CPU) 1, an address selection circuit 2, a memory timing generation circuit 3, a page hit determination circuit 4,
And it is comprised of a memory 5. The processor 1 controls access to the memory 5. The address selection circuit 2 outputs the upper address UA output from the processor 1.
And the lower address LA are output alternately to the memory 5 as the memory address MA.

A memory timing generation circuit 3 receives an address latch signal ADS and a write / read instructing signal WR from the processor 1 and instructs a memory 5 to latch signals RAS and CAS for instructing the memory 5 to latch a memory address MA.
And a write enable signal WE, and if the page hit signal PH output by a page hit determination circuit 4 described later is valid, the address selection circuit 2
Mask instruction signal C for instructing masking of upper address UA
S is output.

[0005] The memory timing generation circuit 3 outputs a ready signal RDY to the processor 1 when the preparation for accessing the area specified by the upper address UA and the lower address LA output by the processor 1 is completed. The page hit determination circuit 4 monitors the upper address UA, and determines the page accessed immediately before (upper address U).
In the case of the same access as in A), a page hit signal PH is output to the memory timing generation circuit 3.

The operation (memory access control method) of the memory control system S having the above configuration will be described with reference to FIG. FIG. 3 is a time chart according to a conventional memory access control method. The memory control system S operates in synchronization with the basic clock clock. First, when the processor 1 performs reading of the memory 5 (first access), the address latch signal ADS is set to valid (low level) until timings T1 and T2, and the upper address UA is set until timings T1 to T6. Then, the output of the lower address LA and the write / read instruction signal WR are set to be valid (low level), and the access is started.

The memory address selection circuit 2 outputs the upper address UA as the memory address MA since the mask instruction signal CS is invalid (high level) during the timings T1 to T3. Further, during the timing T3 to T6, since the mask instruction signal CS is valid (low level), the lower address LA is output as the memory address MA.

[0008] The memory timing generation circuit 3 sets the latch signal RAS to valid (low level) after the timing T2, and between the timings T5 and T6, the ready signal RDY.
Is set to valid (low level). The memory 5 outputs the data D during the timing T5 to T6,
Reads data D at timing T6 and terminates the access.

Next, an access (second access) in which the page hit determination circuit 4 detects a page hit will be described. The processor 1 sets the address latch signal ADS to be valid between the timings T6 and T7, and between the timings T6 and T9, the upper address UA and the lower address L
A, and the access is started by setting the write / read instruction signal WR to valid.

The page hit determination circuit 4 compares the previous access with the upper address UA of the current access. The page hit determination circuit 4 temporarily stores the upper address UA output during the previous access in an internal register or the like. In this case, since the content of the previous upper address UA is “0” and matches the content of the current upper address UA (page hit), the page hit signal PH is set to valid (low level) from timing T6 to T9. .

Since the page hit signal PH is valid, the memory timing generation circuit 3 outputs the timing T6 to T7.
During this period, only the latch signal CAS is temporarily set to be invalid, and is set to be valid during the timing T7 to T9. In addition, the ready signal RDY is set valid during the timing T8 to T9. The memory 5 is connected between timings T8 and T9.
The data D is validated, and the processor 1 determines at timing T9
, The data D is read and the access is terminated.

Next, an access (third access) in which the page hit determination circuit 4 detects a page miss will be described. The processor 1 operates between the timings T9 and T10.
The address latch signal ADS is set to be valid, and during the timing T9 to T16, the upper address UA, the lower address LA, and the write / read instruction signal WR are set to be valid, and access is started.

The page hit determination circuit 4 compares the previous access with the upper address UA of the current access. In this case, since the content of the previous upper address UA is "0" and the content of the current upper address UA is "1", which results in a mismatch (page hit), the page hit signal PH is set to be invalid after timing T9. .

The address selection circuit 2 has a mask designation signal C
S becomes invalid during the timing T9 to T14 and becomes valid after the timing T14.
13 is the upper address UA as the memory address MA.
And outputs the lower address LA as the memory address MA during the timing T13 to T16. Since the page hit signal PH is invalid, the memory timing generation circuit 3 outputs the latch signal RA at the timing T10.
Set S to invalid. Thereafter, after the RAS precharge time of the memory 5 has elapsed, that is, at the timing T12, the latch signal RAS is set to be valid. The timing T
From 14 to T16, the latch signal CAS is set to be valid,
The ready signal is set valid between timings T15 and T16. The memory 5 sets the data D valid between timings T15 and T16.
At 16, the data D is read and the access is terminated.

[0015]

In the memory access control method described above, the latch signal RAS must be precharged after confirming a page miss. For this reason, when the page hit rate is low, every time a page miss occurs, an access delay for performing the precharge occurs, causing a problem that the effect of the page hit is impaired and the access time is lengthened. Was. The present invention has been made in view of the above points, and an object of the present invention is to provide a memory access control method capable of avoiding an increase in access time due to a page miss, which impairs the effect of a page hit.

[0016]

According to the present invention, when an upper address is set, a lower address is set, and when accessing a memory for specifying an access position, the upper address is monitored and the same upper address is monitored. While the is output, the setting of the new upper address is omitted for the memory, the upper address set in the past is retained, and the memory is accessed by setting only the lower address. is executed, an instruction processor for accessing the memory is executed, monitors the prefetch queue for storing in advance, in the prefetch queue, before Symbol when the instruction is not empty stored releases the holding of the upper address Te, before the new upper position address is output to indicate the setting of the upper address to the memory
Set the upper address setting signal to valid. Another invention is to set a lower address after setting an upper address and, when accessing a memory for specifying an access position, monitor the upper address, and while the same upper address is being output, For the memory,
A repeat executed by a processor accessing the memory, omitting the setting of a new upper address, holding the upper address set in the past, executing the access to the memory by setting only the lower address, and detecting an instruction, when the repeat instruction is being executed, it continues the holding of the upper address, when the repeat instruction is finished, before the new upper position address is output, the upper An upper address setting signal for instructing the memory to set an address is set to be valid.

[0017]

According to this method, when accessing a memory for setting an upper address and a lower address,
While the access is continuously repeated at the same upper address, fetching of the upper address is omitted, and the prefetch queue is skipped.
When it is detected that no instruction is stored in the memory and there is no free space, an upper address setting instruction signal for instructing the memory to set an upper address is set valid before a new upper address is output. Thus, when a new upper address is output, the upper address can be immediately set in the memory. Similarly, instead of detecting the absence of free stored instructions in the prefetch queue, so as to detect that the processor is executing the repeat command
May be. When these are detected, the upper address setting instruction signal is set valid before a new upper address is output.

[0018]

FIG. 1 is a block diagram according to a first embodiment of the present invention. The memory control system S1 shown in the figure is different from the memory control system S described in FIG. 2 in that a timeout circuit 6 is newly provided. The timeout circuit 6 is a timer that is reset each time the ready signal RDY output from the memory timing generation circuit 3 to the processor 1 is set to be valid.

When the ready signal is kept invalid for a certain period of time, that is, when the memory 5 is not accessed for a certain period of time, a timeout occurs when the timer count exceeds a preset threshold value. The latch-off signal RO output to the memory timing generation circuit 3 is set to be valid (low level).
When recognizing that the latch-off signal RO has been set to be valid, the memory timing generation circuit 3 sets the latch signal (upper address setting signal) RAS to be invalid and performs precharge.

Here, the operation of the memory control system S1 (memory access control method) will be described with reference to FIG. FIG. 4 is a time chart according to the first embodiment of the present invention. In the figure, timings T21 to T36 are:
This is the same as the timings T1 to T16 described above with reference to FIG. Therefore, the operation after the timing T37 (the fourth access) will be described here.

It is assumed that the memory 5 has not been accessed for two clocks between the timings T36 and T38. When two clocks are counted, the timeout circuit 6 sets the latch-off signal RO to valid (low level) between timings T38 and T40. When recognizing that the latch-off signal RO is valid, the memory timing generation circuit 3 sets the latch signal RAS to invalid at a timing T38 and starts precharge.

Thereafter, the processor 1 sets the timing T39.
During the period from T to T40, the address latch signal ADS is set to be valid, and between the timings T39 to T44, the upper address UA, the lower address LA, and the write / read instruction signal WR are set to be valid, and access is started.

The memory address selection circuit 2 outputs the upper address UA as the memory address MA since the mask instruction signal CS is invalid during the timing T39 to T41, and further, the mask instruction signal CS during the timing T41 to T44. Is valid, the lower address LA is output as the memory address MA. The memory timing generation circuit 3 sets the latch signal RAS to be valid after the timing T40, and sets the latch signal CAS to be valid during the timing T42 to T44.

The memory 5 sets the data D valid during the timing T43 to T44, and the processor 1 reads the data D at the timing T44 to terminate the access.
As described above, when the access to the memory 5 is not performed for a certain period of time, it is determined that a page hit does not occur, and the precharge of the latch signal RAS is started to prepare for an access to a new memory 5.

FIG. 5 is a block diagram according to a second embodiment of the present invention. Memory control system S shown in FIG.
2 is the memory control system S described in FIG.
The difference is that the processor 1 is provided with a prefetch queue monitoring unit 1a.

The prefetch queue monitoring unit 1a, the prefetch queue provided in the processor 1, intended to monitor whether or not to execute instructions stored thereon, there is no free space if stored instruction in the prefetch queue , A control to set the prefetch signal PF output to the memory timing generation circuit 3 to invalid (high level). When recognizing that the prefetch signal PF has been set to be invalid, the memory timing generation circuit 3 sets the latch signal (upper address setting signal) RAS to be invalid and executes precharge.

Here, the operation of the memory control system S2 (memory access control method) will be described with reference to FIG. FIG. 6 is a time chart according to the second embodiment of the present invention. In the figure, timings T51 to T66
Are the timings T1 to T16 described above with reference to FIG.
Is the same as Therefore, the operation after the timing T67 (the fourth access) will be described here.

At timing T66, the processor 1
If there is no free space in the prefetch queue, the prefetch queue monitoring means 1a invalidates the prefetch signal PF. When recognizing that the prefetch signal PF has been set to be invalid, the memory timing generation circuit 3 sets the latch signal RAS to invalid at timing T68,
Start precharge.

After that, the processor 1 sets the timing T69.
During the period from T70 to T70, the address latch signal ADS is set to be valid, and during the timing T69 to T64, the upper address UA and the lower address LA, and the write / read instruction signal WR are set to be valid, and access is started.

The memory address selection circuit 2 outputs the upper address UA as the memory address MA since the mask instruction signal CS is invalid during the timing T69 to T71, and further outputs the mask instruction signal CS during the timing T71 to T74. Is valid, the lower address LA is output as the memory address MA. After the timing T70, the memory timing generation circuit 3 sets the latch signal RAS to be valid, and sets the latch signal CAS to be valid during the timing T72 to T74.

The memory 5 sets the data D valid during the timing T73 to T74, and the processor 1 reads the data D at the timing T74 and terminates the access.
As described above, if there is no free space in the prefetch queue of the processor 1 and the access to the memory 5 is not performed, it is determined that the page hit does not occur and the latch signal RA is output.
Precharge of S is started to prepare for access to a new memory 5.

FIG. 7 is a block diagram according to a third embodiment of the present invention. Memory control system S shown in FIG.
2 is the memory control system S described in FIG.
Compared with the processor 1, the repeat instruction monitoring means 1
The difference is that b is provided.

The repeat instruction monitoring means 1b allows the processor 1 to execute a repeat instruction, for example, a continuous area of the memory 5,
It monitors whether or not an instruction for realizing a process of continuously reading out one area at a time is being executed. When a repeat instruction is not executed, a repeat signal output to the memory timing generation circuit 3 is output. Control is performed to set REP to invalid (high level). Memory timing generation circuit 3
When recognizing that the repeat signal REP has been set to be invalid, it sets the latch signal (upper address setting signal) RAS to be invalid and executes precharge.

Here, the operation of the memory control system S2 (memory access control method) will be described with reference to FIG. FIG. 8 is a time chart according to the third embodiment of the present invention. In the figure, timings T71 to T96
Are the timings T1 to T16 described above with reference to FIG.
Is the same as Therefore, the operation after the timing T96 (the fourth access) will be described here.

At timing T66, the processor 1
Terminates the repeat instruction, the repeat instruction monitoring means 1
b sets the repeat signal REP to invalid. When recognizing that the repeat signal REP has been set to be invalid, the memory timing generation circuit 3 sets the latch signal RAS to be invalid at a timing T98 and starts precharge.

Thereafter, the processor 1 sets the timing T99
During the period from T to T100, the address latch signal ADS is set to be valid, and between the timings T99 to T104, the upper address UA, the lower address LA, and the write / read instruction signal WR are set to be valid, and access is started.

The memory address selection circuit 2 outputs the upper address UA as the memory address MA since the mask instruction signal CS is invalid during the timing T99 to T101, and further outputs the mask instruction signal CS during the timing T101 to T104. Is valid, the memory address M
The lower address LA is output as A. The memory timing generation circuit 3 sets the latch signal RAS to be valid after the timing T100, and sets the timings T102 to T104.
During this period, the latch signal CAS is set to be valid.

The memory 5 stores timings T103 to T10.
During the period 4, the data D is set valid, and the processor 1 reads the data D at the timing T104 and terminates the access. As described above, when the processor 1 does not execute the repeat instruction, it is determined that the page does not hit.
Precharge of the latch signal RAS is started to prepare for access to a new memory 5.

[0039]

As described above, according to the memory access control method of the present invention, the upper address and the lower address newly output by the processor are stored in the memory before the page miss accompanying the memory access occurs. In order to prepare for the process to be set, when a new upper address and a lower address are output from the processor, it is possible to quickly respond.

[Brief description of the drawings]

FIG. 1 is a block diagram according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional memory control system.

FIG. 3 is a time chart according to a conventional memory access control method.

FIG. 4 is a time chart according to the first embodiment of the present invention.

FIG. 5 is a block diagram according to a second embodiment of the present invention.

FIG. 6 is a time chart according to a second embodiment of the present invention.

FIG. 7 is a block diagram according to a third embodiment of the present invention.

FIG. 8 is a time chart according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor (CPU) 2 Address selection circuit 3 Memory timing generation circuit 4 Page hit determination circuit 5 Memory 6 Timeout circuit

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/30-9/36 G06F 12/00-12/06 G06F 13/16-13/18 G11C 7 / 00,11 / 401,11 / 41

Claims (2)

(57) [Claims] When a lower address is set after setting an upper address and a memory for specifying an access position is accessed, the upper address is monitored, and while the same upper address is being output, Omitting the setting of the new upper address for the memory, holding the upper address set in the past, and accessing the memory by setting only the lower address, accessing the memory A prefetch queue that stores an instruction to be executed by a processor to be executed in advance is monitored, and when the instruction is stored in the prefetch queue and there is no free space, the holding of the upper address is released, and a new upper address is output. Before setting, the upper address setting signal for instructing the memory to set the new upper address is set to valid. Memory access control method comprising Rukoto. 2. A method of setting a lower address after setting an upper address and accessing a memory for specifying an access position, wherein the upper address is monitored and while the same upper address is being output, Omitting the setting of the new upper address for the memory, holding the upper address set in the past, and accessing the memory by setting only the lower address, accessing the memory A repeat instruction to be executed by the processor to be executed is detected. If the repeat instruction is executed, the holding of the upper address is continued. If the repeat instruction is completed, a new upper address is output. Before that, it is effective to set an upper address setting signal for instructing the memory to set the new upper address. Memory access control method.