JP3312543B2 - CPU monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-precision CPU monitoring circuit using a logic circuit.

[0002]

2. Description of the Related Art First, there is a conventional circuit for monitoring a repetitive pulse signal from a CPU as shown in FIG. This circuit includes a bandpass filter 01 including resistors R1 to R3 and capacitors C1 and C2, and an NPN transistor 0.
2, a Schmitt inverter 03, and a time constant generating circuit 04 including a resistor R4 and a capacitor C3. Hereinafter, the circuit operation of the conventional example will be described. In the conventional circuit, PRU
When the N signal passes through the band-pass filter circuit 01, differentiation (integration) is performed for each rising edge and falling edge.
A signal is output (point A in FIG. 7). In this circuit, PRUN
PRUN monitoring is performed by utilizing the relationship between the amplitude AW of the differential (integral) signal at the time of rising and the VBE of the NPN transistor 02. That is, (1) If AW> VBE, the circuit determines that the normal PRUN has been input, and discharges the charge stored in the capacitor C3 in FIG. 7 every time the PRUN signal rises.

(2) If AW <VBE (PRRUN cycle is very short) or if an integral (differential) signal at the rise of PRUN is not input (PRUN signal stops), the circuit determines that the PRUN signal is abnormal. It is determined, and the charging of the capacitor C3 in FIG. 7 is continued.

[0004] As shown in FIG. 8, when the PRUN signal is normal, the differential (integral) signal at the rise of PRUN is used as the signal B.
Before the point voltage exceeds the H-level threshold (VtH) of the Schmitt inverter 03, the charge accumulated in the capacitor C3 is discharged. Therefore, the output of the Schmitt inverter 03 does not invert, and the WRES output becomes H. Hold. However, in consideration of a case where the PRUN signal is abnormal, for example, when the capacitor C3 is stopped, the voltage at the point B gradually increases due to the continuous charging of the capacitor C3, and the H-level threshold value of the Schmitt inverter 03 ( VtH), the output of the Schmitt inverter 03 is inverted and WRES
The output becomes L. Immediately thereafter, the electric charge of the capacitor C3 is discharged, and when the voltage at the point B falls to the L-level threshold value (VtL) of the Schmitt inverter 03, the output of the Schmitt inverter 03 is again inverted, and the WRES output becomes H again. Becomes Thereafter, the electric charge is further discharged to the capacitor C3, and when the voltage at the point B exceeds the H-level threshold (VtH) of the Schmitt inverter 03, the WRES output becomes L. Thereafter, the above operation is repeated until a normal PRUN signal (a differential (integral) signal at the time of PRUN rising with an amplitude exceeding the VBE of the NPN-Tr) is input, whereby an intermittent reset signal is output.

[0005]

However, in such a conventional CPU monitoring circuit, since a capacitor is discharged by a differential (integral) signal at the time of rising of the PRUN, the rising of the PRUN signal (the rising of the PRUN signal) is performed. Min) only monitors the pulse and rise time,
It is possible to judge whether the PRUN signal is short-period abnormal, long-period abnormal, stop abnormal, or input noise is normal / abnormal (all based on the PRUN rising interval).
There is a problem that it is difficult to detect a composite pattern of the PRUN abnormalities (stop abnormality, cycle abnormality, duty abnormality) including a duty abnormality and a duty abnormality. In addition, PR
Regarding the failure of the time constant on the long side such as the long cycle and stop of the UN, the node at the point B in FIG.
It is determined whether or not a differential (integral) signal at the rise of PRUN is input during the time when the battery is charged up to VtH (V). Therefore, the PRUN long cycle detection limit has the same time constant as the stop detection limit. There was also a problem that only monitoring was possible.

Further, since the conventional circuit is an analog circuit using discrete elements (C, R), the variation among the elements (eg, resistance variation ± 5%, temperature characteristic 2000 ppm)
, Capacitor variation ± 20%, temperature characteristic 15%, etc.), the variation in total PRUN monitoring is large, and in consideration of these variations, it is designed so that even in the worst case, the normal PRUN is not erroneously judged as abnormal. Then, there is also a problem that the monitoring width cannot be brought very close to the PRUN normal value.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and includes an edge detection circuit, first, second, third, and fourth counters, and a first counter. ,
CP including second, third, fourth, fifth, and sixth logic circuits and first, second, third, fourth, and fifth storage circuits
U monitoring circuit, wherein the edge detection circuit receives a repetitive monitoring pulse signal (hereinafter, referred to as a PRUN signal) from a CPU and receives the PRU signal in response to a first clock pulse.
Output rising and falling edge detection signals of the N signal;
The first counter is reset each time a rising edge detection signal output from the edge detection circuit and an intermittent reset signal output from the fifth storage circuit are output, and receives the second clock pulse. Counting, outputting the count value to the first logic circuit,
When the count value output from the first counter reaches a logical value, the first logic circuit outputs a window width corresponding to a variation allowable range to the first storage circuit, and The storage circuit determines whether the H width of the PRUN signal is normal or abnormal based on the window width output from the first logic circuit and the falling detection signal output from the edge detection circuit. The third
And the second counter is reset each time a falling edge detection signal output from the edge detection circuit and an intermittent reset signal output from the fifth storage circuit are output. At the same time, the second clock pulse is received and counting is performed.
When the count value output from the second counter reaches a logical value, the second logical circuit sends a window width corresponding to the variation allowable value to the second storage circuit. The second storage circuit outputs a normal / L width of the PRUN signal based on the window width output from the second logic circuit and the rising detection signal output from the edge detection circuit. An abnormality determination is performed, and the result is output to the third logic circuit. The third logic circuit determines whether the H width of the PRUN signal output from the first storage circuit is normal or abnormal. , Based on the L / N normal / abnormal judgment result of the PRUN signal output from the second storage circuit and the edge detection signal of the PRUN signal output from the edge detection circuit, And both L width determines whether normal or abnormal, and outputs the result to the third counter,
The third counter is reset based on a determination result output from the third logic circuit, and
And outputs the count value to the fourth logic circuit. The fourth logic circuit outputs the first L pulse of the intermittent reset signal from the time when the PRRUN signal is determined to be abnormal. Is set, and when the count value output from the third counter reaches the waiting time, a trigger pulse of an intermittent reset signal is output to the third storage circuit. The third storage circuit is reset every time the third logic circuit outputs a signal indicating normality. Based on the reset, the third storage circuit resets the fourth counter, and resets the fourth logic circuit. When the trigger pulse of the intermittent reset signal is output from the controller, the fourth counter is started, and the fourth counter counts in response to the fourth clock pulse. Counting the intermittent reset signal in response to the trigger pulse of the intermittent reset signal, the fifth logic circuit determines a repetition period of the intermittent reset signal using a count value of the fourth counter, The fourth storage circuit stores the repetition cycle of the intermittent reset signal determined by the fifth logic circuit, resets the fourth counter for each determined repetition cycle, and resets the sixth logic circuit. The circuit determines the length of the H width and the L width of the intermittent reset signal using the count value of the fourth counter, and the fifth storage circuit stores
The lengths of the H width and the L width of the intermittent reset signal determined by the logic circuit are stored, and for each of the stored intermittent reset signals, the intermittent reset signal is sent to the first counter and the second counter. The purpose is to solve the above problem by outputting.

[0008]

Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a (digital) CPU monitoring circuit using a logic circuit according to an embodiment of the present invention. First, the configuration of the present embodiment will be described. In FIG.
Has been entered. The rising / falling edge detection circuit 1 is, for example, a circuit as shown in FIG. 2 and operates in response to a first clock pulse input CLK1. The rising side of the PRUN signal outputs the rising edge detection pulse twice consecutively with the phase shifted, and outputs the first rising edge detection pulse (UPED1) to the reset terminal of the first counter 2 and to the second terminal as shown in FIG. To the CK terminal of the storage circuit 7 of
The second rising edge detection pulse (UPED2) is input to the third logic circuit 8. Similarly, on the falling side of the PRUN signal, the falling edge detection pulse is output twice consecutively with the phase shifted, and the first falling edge detection pulse (DWED
1) is input to the reset terminal of the second counter 5 and the CK terminal of the first storage circuit 4, and the second falling edge detection pulse (DWED2) is input to the third logic circuit 8.

The first counter 2 counts in response to a second clock pulse input CLK2, and its output is the first
Logic circuit 3. This first logic circuit 3
The output of the first counter 2 constitutes a logic corresponding to a window width for determining whether or not the H width of the PRUN signal is within a specified range. D terminal.

The second counter 5 also counts with the second clock pulse input CLK2, and its output is
Is connected to the logic circuit 6. This second logic circuit 6
A logic corresponding to a window width for determining whether the L width of the PRUN signal is within a prescribed range is formed, and an output thereof is connected to a D terminal of the second storage circuit 7.

A normal / abnormal judgment signal (HWD (Q)) of the PRUN signal H width is output from the Q terminal of the first storage circuit 4, and the normal / abnormality of the PRUN signal L width is output from the Q terminal of the second storage circuit 7. An abnormality determination signal (LWD (Q)) is output and input to the third logic circuit 8, respectively.

The third logic circuit 8 constitutes a logic for judging whether both the H width and the L width of the PRUN signal are normal, and the output (DFR) of the logic is determined by the third counter 9 and the third counter. It is connected to the reset terminal R of the storage circuit 11.

The third counter 9 is a counter that counts with a third clock pulse input CLK3, and its output is connected to the fourth logic circuit 10.

The fourth logic circuit 10 calculates the time constant from the abnormal start point of the PRUN signal to the output of the first L level pulse of the intermittent reset signal = clock off time (tOF).
The output (WDF) is a trigger signal for outputting an intermittent reset, and is connected to the CK terminal of the third storage circuit 11.

The Q terminal of the third storage circuit 11 is connected to the reset terminal of the fourth counter 12, and from there the fourth terminal
Of the counter 12 is released.

The fourth counter 12 counts according to a fourth clock pulse input CLK4, and its output is connected to the fifth logic circuit 13 and the sixth logic circuit 15.

The fifth logic circuit 13 includes a fourth counter 1
2 is configured to determine the repetition period of the intermittent reset signal by using the output of the fourth storage circuit 1.
4 is connected to the D terminal.

The Q terminal of the fourth storage circuit 14 is connected to the reset terminal of the fourth counter 12, and resets the fourth counter 12 every intermittent reset cycle (T
RES).

The sixth logic circuit 15 constitutes logic for determining the H width (tRH) / L width (tRL) of the intermittent set, and its output is connected to the D terminal of the fifth storage circuit 16. I have.

From the Q terminal of the fifth storage circuit 16, a reset signal (H constant when PRUN is normal, intermittent reset signal when abnormal) is output, and each of the first counter 2 and the second counter 5 is output. Connected to reset terminal.

Next, the circuit operation of the present embodiment will be described. As shown in FIG. 1, when the PRUN signal is input to the rising / falling edge detection circuit 1, a rising / falling edge detection pulse is output each time the PRUN signal rises and falls.

The first counter 2 is activated simultaneously with the reset by the rising edge detection pulse, and starts counting the second input clock pulse CLK2. At this time, the second input clock pulse CLK2 must have a sufficiently short cycle with respect to the PRUN signal, and a shorter clock pulse is required as the system requires higher PRUN monitoring accuracy.

After the counter is started, the output (= count value) of the first counter 2 increases with time. When the count value reaches the logical value (= decode value) of the first logical circuit 3, the first logical circuit 3
From D1, a window corresponding to the permissible variation range of the PRUN signal H width is logically output.

By setting this window width at the design stage, the monitoring accuracy of the PRUN signal can be made strict or moderate. The normal / abnormal judgment of the PRUN signal H width
The window input to the D terminal in the first storage circuit 4 is H
It is determined whether or not the first falling edge detection pulse DWED1 is input to the CK terminal during the level period.
When the RUN signal H width is in the normal range, the Q terminal is set to H,
If abnormal, the Q terminal outputs L. L of PRUN signal
The width monitoring is performed by the same operation as the H width monitoring.

The second counter 5 is activated simultaneously with the reset by the first falling edge detection pulse DWED1, and starts counting the second input clock pulse.

After the counter is started, the output (= count value) of the second counter 5 increases with time. When the count value reaches the logic value (= decode value) of the second logic circuit 6, the second logic circuit 6 sets the DWE coming from the system.
From D1, a window corresponding to the permissible variation range of the PRRUN signal L width is logically output. Whether the PRUN signal L width is normal or abnormal is determined by whether or not the first rising edge detection pulse UPED1 is input to the CK terminal while the window input to the D terminal in the second storage circuit 7 is at the H level. When the width of the PRUN signal L is within the normal range, the Q terminal outputs H, and when the width is abnormal, the Q terminal outputs L.

In the third logic circuit 8, the first storage circuit 4
It is determined whether both the H width and the L width of the PRUN signal (ie, the PRUN cycle) are normal based on the Q output (HWD) of the second storage circuit 7 and the Q output (LWD) of the second storage circuit 7. 2 rising edge detection pulse (UP
ED2) and the second falling edge detection pulse (DWE)
D2), an L-level pulse determined by the second clock input CLK2 is output to the DFR.
It will be constant. FIG. 3 shows an example of the third logic circuit 8.

Here, the circuit operation so far is summarized in FIG. In FIG. 5, when the PRUN signal is normal, HWD
DWED1 during the H period, and UPE during the LWD H period.
Since D1 is included, the Q output HW of the first storage circuit 4
D (Q) and the Q output LWD (Q) of the second storage circuit 7
Maintain an H level, respectively, so that the third logic circuit 8 outputs an L level pulse for each of UPED2 and DWED2.

If the PRUN signal is abnormal, for example, if it stops at the L level, it is assumed that the PRUN signal has been
Signal is normal and both HWD (Q) and LWD (Q) are H
Even if it is the level, since there is no edge input of the PRUN signal, the output (DFR) of the third logic circuit 8 holds the H level, and the counter for activating the intermittent reset signal of the next and subsequent stages is not reset. Continue counting up.

Further, in the case of a duty abnormality or a period abnormality of the PRUN signal (FIG. 4), the input of DWED1 is set to H level.
WD goes out of H period or UPED1 input is LWD
, HWD (Q) and / or LWD (Q) are at the L level, and the DFR is at H level as in the case of abnormal PRUN stop. Hold the level.

The third counter 9 is a so-called clock off time (tOFF) in the watchdog timer.
The output of which is connected to the fourth logic circuit 10.

The fourth logic circuit 10 includes a third counter 9
Is used to set the waiting time from the abnormal start point of the PRUN signal to the output of the first L pulse of the intermittent reset pulse.

The third storage circuit 11 stores the fourth logic circuit 1
The reset state of the fourth counter 12 is determined by inputting an output of 0, that is, a trigger pulse for activating the fourth counter 12 to the CK terminal. That is, when the Q output is at the L level (= initial state), the counter is reset, and when the Q output is at the H level due to the input of the trigger pulse, the counter is activated.

The fourth counter 12 outputs an intermittent reset signal (tRH = repetition signal H width, tRL = repetition signal L
The output of the counter is connected to two points of a fifth logic circuit 13 and a sixth logic circuit 15.

The fifth logic circuit 13 includes a fourth counter 1
The logic of determining the repetition period of the intermittent reset signal is configured by using the output of the second circuit 2. The output is stored in the fourth storage circuit 14, and the fourth counter 12 is reset every Q output. , A repetitive signal having a constant period is obtained.

The sixth logic circuit 15 constitutes a logic for determining the lengths of the H width and the L width of the intermittent reset signal using the output of the fourth counter 12, and outputs the output to the fifth logic. The Q output (WRE) is stored by the storage circuit 16.
A desired intermittent reset pulse can be obtained from S).

Here, the schematic operation of the digital watchdog timer described above will be described with reference to FIG. In FIG. 6, when the PRUN signal is normal, the third counter 9
Is periodically reset by the rising / falling edge detection pulse, the fourth counter 12 is also constantly reset, and as a result, the WRES output holds the H level. Next, when the PRUN signal continues to be abnormal, a trigger pulse (WDF) for an intermittent reset is output after a predetermined time (set by the fourth logic circuit 10 at the time of design) from the PRUN abnormality, and the fourth counter 12 is output by the trigger signal. Upon activation, an intermittent reset pulse is output from the WRES output in the order of L width and H width. Generally, during reset, the CPU
Since the UN signal is not output, it is necessary to mask the count of the PRUN signal during the L period of the intermittent reset.
This is the reason that the first counter 2 and the second counter 5 are reset by the WRES output.

The first to sixth logic circuits 3, 6, 8, 10, 13, and 15 of the embodiment set the period of the clock pulse for each counter and the time constant of each speed. Depending on the logical pattern,
Not uniquely specified. Although the clock inputs of the edge detection circuit 1 and the first to fourth counters 2, 5, 9, and 12 are described as different clocks in the embodiment in consideration of each time constant, monitoring accuracy, and the like, the same clock is used. No problem with the clock.

In the digital CPU monitoring circuit of this configuration, P
Since the length of both the H width and the L width of the RUN signal is monitored for each rising / falling edge, and an intermittent reset is output when the PRUN abnormality continues for a predetermined time, (1) the conventional PRUN (2) Minimum pulse / maximum pulse of each of H width / L width, which can detect a duty abnormality and a composite abnormality of PRUN including a duty / stop / periodic variation, which were difficult to detect by the rising cycle monitoring method. The detection limit and the stop detection limit, as well as the clock off time and the intermittent reset time (H width / L width) can be set individually, and the maximum period that could be handled only by the same time constant in the conventional PRUN rising cycle monitoring method There is also an advantage that the detection limit and the maximum stop detection limit can be handled as different time constants.

Further, with respect to the accuracy (variation) which has been a problem in the conventional example, since the present embodiment is full digital, (3) the area formed into an IC is small, and the external element is only an oscillation circuit. For this reason, the PRUN monitoring accuracy is almost the same as the error of the oscillator (eg, ± 1% due to the variation of CERALOCK and the temperature), and there is an advantage that the PRUN monitoring accuracy is remarkably improved.

Further, from the effects of (2) and (3),
(4) It is possible to arbitrarily set each monitoring width of the PRUN signal without considering the element variation.
There is also an advantage.

[0042]

As described above, according to the present invention, the configuration is such that both the H width and the L width of the PRUN signal are monitored using a logic circuit. A CPU monitoring circuit that can detect complex abnormal conditions, can set the H- / L-width period abnormality (maximum and minimum) detection limit and stop abnormality detection limit arbitrarily, and can monitor with high accuracy The effect that it can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a CPU monitoring circuit using a logic circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an edge detection circuit used in the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third logic circuit used in the embodiment of the present invention.

FIG. 4 is a time chart (part 1) illustrating a general operation of the CPU monitoring circuit according to the embodiment;

FIG. 5 is a time chart (part 2) illustrating a general operation of the CPU monitoring circuit according to the embodiment;

FIG. 6 is a time chart (part 3) illustrating a general operation of the CPU monitoring circuit according to the embodiment;

FIG. 7 is an electrical connection diagram showing a conventional CPU monitoring circuit.

FIG. 8 is a time chart illustrating a general operation of a conventional CPU monitoring circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Edge detection circuit 2 1st counter 3 1st logic circuit 4 1st memory circuit 5 2nd counter 6 2nd logic circuit 7 2nd memory circuit 8 3rd logic circuit 9 3rd counter 10 Fourth logic circuit 11 Third storage circuit 12 Fourth counter 13 Fifth logic circuit 14 Fourth storage circuit 15 Sixth logic circuit 16 Fifth storage circuit

Claims (1)

(57) [Claims] 1. An edge detection circuit, first, second, third, and fourth counters, and first, second, third, fourth, and fifth counters.
And a sixth logic circuit, and a first, second, third, fourth, and fifth storage circuit, wherein the edge detection circuit is configured to output a repetitive monitoring pulse signal (hereinafter, referred to as a “pulse signal”) from the CPU. , PRUN signal), and outputs a rising and falling edge detection signal of the PRUN signal in response to a first clock pulse. The first counter detects a rising edge output from the edge detection circuit. Each time the signal and the intermittent reset signal output by the fifth storage circuit are output, the reset is performed, and the count is performed in response to the second clock pulse, and the count value is output to the first logic circuit. When the count value output from the first counter reaches a logical value, the first logic circuit changes the window width corresponding to the variation allowable range to the first value. The first storage circuit outputs an H width of the PRUN signal based on a window width output from the first logic circuit and a falling detection signal output from the edge detection circuit. And outputs the result to the third logic circuit. The second counter determines whether the falling edge detection signal output from the edge detection circuit and the fifth storage circuit Each time the output intermittent reset signal is output, the reset is performed, and the count is performed in response to the second clock pulse, and the count value is output to the second logic circuit. When the count value output from the second counter reaches a logical value, a window width corresponding to the variation allowable value is output to the second storage circuit, and the second storage circuit 2 based on the window width output from the logic circuit 2 and the rising detection signal output from the edge detection circuit, and determines whether the L width of the PRUN signal is normal or abnormal. And the third logic circuit outputs a signal indicating whether the H width of the PRUN signal output from the first storage circuit is normal or not.
The PRUN signal is output based on the PRUN signal output from the second storage circuit, the L-width normal / abnormal determination result, and the PRUN signal output from the edge detection circuit. H width and L of signal
It is determined whether both widths are normal or abnormal.
The third counter is reset based on the determination result output from the third logic circuit, and the third counter is reset.
Counts and outputs the count value to the fourth logic circuit. The fourth logic circuit outputs the first L pulse of the intermittent reset signal from the time when the PRRUN signal is determined to be abnormal. Is set, and when the count value output from the third counter reaches the waiting time, the trigger pulse of the intermittent reset signal is set to the third time.
The third storage circuit is reset each time the third logic circuit outputs a signal indicating normality, and based on this reset, resets the fourth counter, When the trigger pulse of the intermittent reset signal is output from the fourth logic circuit, the fourth counter is started, and the fourth counter receives a fourth clock pulse and counts. The intermittent reset signal is counted according to the trigger pulse of the intermittent reset signal, and the fifth
The logic circuit determines the repetition period of the intermittent reset signal using the count value of the fourth counter, and the fourth storage circuit determines the repetition period of the intermittent reset signal determined by the fifth logic circuit. While memorizing the cycle,
Resetting the fourth counter for each determined repetition cycle, the sixth logic circuit uses the count value of the fourth counter to determine the lengths of the H width and the L width of the intermittent reset signal. The fifth storage circuit stores the lengths of the H width and the L width of the intermittent reset signal determined by the sixth logic circuit,
A CPU monitoring circuit for outputting the intermittent reset signal to the first counter and the second counter for each of the stored intermittent reset signals.