JP3298931B2 - Oscillator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating circuit, and more particularly to an oscillating circuit used for displaying characters and images on a television or VTR.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional oscillation circuit. This oscillation circuit is, for example, an LC oscillation circuit used in an on-screen device (a device for displaying a character image) to obtain timing in the horizontal direction of character display. This oscillation circuit has bias circuits 1 and 2 and an oscillation element 3.

Each of the bias circuits 1 and 2 includes a MOS
FETs 1a, 1b, 1c, 1d and 2a, 2b, 2c,
2d. The oscillation element 3 includes a clocked inverter 3a and an inverter 3b.

The input side of the clocked inverter 3a is grounded via a capacitor 6a, and the input side has a drain and a gate of the MOS FET 1a,
The drain and gate of the FET 1c are connected to one end of the inductance 5, respectively.

[0005] The output side of the clocked inverter 3a is grounded via a capacitor 6b.
The drain and gate of b, and the drain and gate of MOS FET 2c are connected respectively.

Further, a MOS FET 1a and a MOS FET
The source of 2a is grounded to the power supply _VDD , and the MOSFET 1
a is connected to the source of the MOSFET 1b, and the source of the MOSFET 1c is connected to the source of the MOSFET 1d.
Is connected to the drain of the MOSFET 2a and the source of the MOSFET 2b.
The source of ET2c is connected to the drain of MOSFET2d, and the sources of MOSFET1d and MOSFET2d are connected to ground.

The input side of the NOR 9 is connected to the oscillation control terminal 7 and the oscillation control terminal 8, and the input side of the OR 4 is connected to the output side of the NOR 9 and the oscillation control terminal 8. The NOR 9 is connected to the input side of the inverters 3b and 3c and the positive operation control terminal of the clocked inverter 3a. The output side of the inverter 3b is connected to the negative operation control terminal of the clocked inverter 3a.
Is connected to the gates of MOSFETs 1d and 2d. The output side of OR4 is MOSFET1
a, 2a.

Next, the operation will be described. When the oscillation control signal input to the oscillation control terminal 7 is at a high level (H), the output of the OR 4 is at a low level, and the positive operation control terminal of the clocked inverter 3a is at a low level (L). The negative operation control terminal of the clocked inverter 3a through the inverter 1
Since the output of R4 is input, it becomes high level (H),
Clocked inverter 3a stops the oscillating operation.

At the same time, the output of the inverter 3c goes high (H), so that the MOS FETs 1d,
2d is turned on, and the output of OR4 becomes low level, so that the MOS FETs 1a and 2d are turned on and the bias circuits 1 and 2 operate, whereby the input and output terminals of the clocked inverter 3a are set to predetermined values ( For example, V
_DD / 2).

When the oscillation control signal input to the oscillation control terminal 7 is set to a low level (L), the signals are inverted when the oscillation is stopped, the bias circuits 1 and 2 stop operating, and the clocked inverter 3a Operates and starts oscillating. At this time, since the input and output terminals of the clocked inverter 3a are biased, if the input of the clocked inverter 3a is inverted, the output is surely inverted in response to this, and the clock loss at the time of oscillation start (input (A phenomenon that the output is not inverted in response to the

If a clock dropout occurs, the displayed characters are disturbed in the horizontal direction on the screen. The signal input to the oscillation control terminal 8 is a high-level oscillation control signal for forcibly stopping the oscillation from the system controller, and is input when the oscillation is stopped for a long time. When this signal is set to the high level (H) to stop the oscillation, unlike when the signal of the oscillation control terminal 7 is set to the high level (H) to stop the oscillation,
The output of R4 becomes high level (H) and MOS FET
1d and 2d are turned off, and the bias circuits 1 and 2 stop operating. By disabling the bias circuit in this way, a bias current does not flow, current consumption can be suppressed, and a battery-operated device can be used for a long time.

The oscillation control terminal 7 receives a normal oscillation stop signal (a high-level signal for stopping oscillation during the horizontal synchronizing signal input period).
, A forced oscillation stop signal (output when the screen is completely switched to video display by a high-level signal output from the system controller and character display is not performed for a long time) is input.

[0013]

The above-described conventional oscillation circuit can prevent clock dropout at the start of oscillation and can reduce horizontal disturbance of displayed characters on the screen. To stop oscillation,
The operation of the clocked inverter in the oscillation stage is stopped to stop the oscillation, and the input and output terminals are biased to a predetermined potential. However, when the potential is at the predetermined potential, the impedance from the power supply (V _DD ) is high, and the minute oscillation may occur. Will remain.

If this minute oscillation remains, oscillation occurs at the phase of the previous oscillation when the next oscillation starts, so that a phase difference occurs between the start timing and the actual oscillation, and the horizontal characters of the displayed characters on the screen are displayed. There is a problem that the direction is disturbed.

This problem is caused by shortening of the oscillation stop period (5 μs to 1
(shortened to μs).

An object of the present invention is to provide an oscillation circuit having a reduced oscillation stop period.

[0017]

In order to achieve the above object, an oscillation circuit according to the present invention comprises a first control signal having a logic level lower than a first control signal.
An oscillation element that performs oscillation operation / oscillation stop according to the bell
The feedback connected between the input and output terminals of the oscillator
And a second control element connected to the input terminal of the oscillation element.
The input terminal of the oscillation element is changed according to the logic level of the control signal.
Switch element connected to power supply and logic of third control signal
The input terminal and the output of the oscillation element according to the level
A bias circuit for setting a terminal to a predetermined potential, and an oscillation control signal
The first, second and third controls in response to a logic level of
A control circuit for outputting a control signal, wherein the oscillation control signal
When controlling the oscillation / stop of the oscillation element based on
The control circuit may control the oscillation control signal to output a first logic level.
At the time of a bell, the oscillation element is stopped as the first control signal.
Outputting a logic level for stopping operation,
The input terminal of the oscillation element is once set to the power supply potential as a control signal.
Output a logic level to
The input terminal and the third control signal until
Via a logic level signal that sets the output terminal to a predetermined potential.
Output to the oscillation circuit when the oscillation start timing is reached.
A first logic level for causing the oscillation element to oscillate;
It outputs a control signal. Also, a first control signal
Oscillator that oscillates / stops according to the logic level of
Connected between the input terminal and the output terminal of the oscillation element.
Feedback element and the input terminal of the oscillation element.
The input of the oscillation element is changed according to the logic level of the second control signal.
A switch element for setting the input terminal to the power supply potential, and a third control signal.
Signal and the input terminal of the oscillation element according to the logic level of the signal.
Circuit that sets the output terminal and output terminal to a predetermined potential, and oscillation
The first, second, and third signals in response to a logic level of a control signal.
A control circuit for outputting a third control signal;
Controlling oscillation / stop of the oscillation element based on a control signal;
When the oscillation circuit receives the first oscillation signal,
At the time of a logic level, the oscillation element is used as the first control signal.
Output a logic level to stop the
Control signal from the first logic level to the second logic level
After the transition, the oscillation element is used as the second control signal.
Outputs a logic level once the power source potential input terminal,
Thereafter, the third control signal is output until the oscillation start timing comes.
The input terminal and the output terminal to a predetermined potential.
Output a logic level signal to the bias circuit.
When the start timing comes, the oscillation element starts oscillating.
And outputs the first control signal of a logic level to be applied.
is there.

[0018]

[0019]

The oscillation is reliably stopped in a short time by shorting the input terminal of the oscillation element to the power supply potential. This eliminates the phase difference between the oscillation start timing and the actual oscillation, and eliminates the disturbance of displayed characters on the screen.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a timing chart.

In FIG. 1, the oscillation circuit of the present invention has bias circuits 1 and 2, an oscillation element 3, a switching element 11 for short-circuit, and a control circuit 10.

The bias circuits 1 and 2 are MOS FETs
1a, 1b, 1c and 1d and 2a, 2b, 2c and 2d. The oscillation element 3 is a clocked inverter 3
a and an inverter 3b.

The input side of the clocked inverter 3a is grounded via a capacitor 6a, and further has one end of an inductance 5 and a switching element 11
And are connected.

The switching element 11 is a MOS FET
The MOS FET 11 has a drain connected to the input side of the clocked inverter 3a and a source grounded.

The output side of the clocked inverter 3a is grounded via a capacitor 6b, and the output side is connected to the other end of the inductance 5 and the drains and gates of the MOS FETs 2b and 2c. Also MOS FET
1a is connected to the source of the MOSFET 1b, and the source of the MOSFET 1c is connected to the source of the MOSFET 1c.
d, the drain of the MOS FET 2a is connected to the source of the MOS FET 2b, and the
The source of the SFET 2c and the drain of the MOSFET 2d are connected, the sources of the MOSFETs 1a and 2a are connected to a power supply (V _DD ), and the sources of the MOSFETs 1d and 2d are connected to the ground.

The oscillation control terminals 7 and 8 are connected to the input side of the control circuit 10.

The output terminal 1 of the control circuit 10 is
It is connected to the gates of ET1d and 2d. Control circuit 1
0 output terminal 2 is connected to the gates of MOS FETs 1a and 2a. The output terminal 3 of the control circuit 10 is connected to the input side of the inverter 3b and the positive control terminal of the clocked inverter 3a, and the output side of the inverter 3b is connected to the negative control terminal of the clocked inverter 3a. The output terminal 4 of the control circuit 10 is connected to a MOS FET 11
Connected to the gate.

Next, the operation will be described with reference to the timing chart of FIG. First, when the oscillation control signal input from the system controller to the oscillation control terminal 8 is set to high level (H), the control signal 104 output from the control circuit 10 to the clocked inverter 3a becomes low level (L), and the oscillation element 3 is stopped. Also, the bias circuit positive control signal 103 is at a high level (H).
And the MOS FETs 1d and 2d are turned on, and the input and output of the clocked inverter 3a are set to low level (L).
Bias. The bias circuit negative signal 105 is set to a high level, the MOSFETs 1a and 2a are turned off, the bias circuits 1 and 2 are not operated, and the bias current does not flow.

The above operation is a case where the oscillation is stopped for a long time.

Next, the operation of starting oscillation from the above-described oscillation stop state will be described. This operation is the same as when the oscillation control signal input to the oscillation control terminal 7 goes high. First, the clocked inverter control signal 104 is set to low level, and the operation of the clocked inverter is stopped. Also, the forced oscillation stop signal 106 is set to a high level,
By turning on the MOS FET 11 and grounding the input of the clocked inverter 3a to the ground, oscillation is reliably stopped so that minute oscillation does not remain.

Next, in order to operate the bias circuit, the bias circuit negative control signal 105 is set to low level. In order to prevent a current flowing from the bias circuit through the MOSFET 11, the forced oscillation stop signal 106 is set to a low level, and the MOSFET 11 is turned off.

The oscillation is started by setting the bias circuit positive control signal 103 to low level (L), the bias circuit negative control signal 105 to high level (H), and the clocked inverter control signal 104 to low level (L) at the oscillation start timing. To start. At this time, since no minute oscillation remains, oscillation occurs at that timing, and no phase difference occurs. In addition, since a bias circuit is used, a stable oscillation waveform can be obtained without causing clock omission. As a result, it is possible to eliminate the horizontal disturbance of the display characters on the screen.

FIG. 3 shows a case where the control circuit 10 for performing the above-described circuit operation (the timing chart of FIG. 2) is constituted by a logic circuit.

In order to enhance the effect of the embodiment, a switch element similar to the MOSFET 11 is added to the output side of the clocked inverter 3a, and the same signal as the MOSFET 11 is used. You may make it short-circuit.

[0035]

As described above, according to the present invention, the switching element is provided so that the input of the clocked inverter of the oscillating element can be forcibly short-circuited to the first power supply (V _DD or V _SS ). Oscillation can be reliably stopped in time. As a result, no phase difference occurs between the oscillation start timing and the actual oscillation, so that it is possible to eliminate the horizontal disturbance of the display characters on the screen.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of the circuit of FIG.

FIG. 3 is a circuit diagram showing one embodiment of the control circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 2 bias circuit 1a, 1b, 1c, 1d, 2a, 2b, 2c, 2d M
OS FET 3 Oscillator 3a Clocked inverter 3b Inverter 4 OR circuit (only conventional circuit) 5 Inductance 6a, 6b Capacitor 7 Oscillation control signal (normal oscillation stop signal) 8 Oscillation control signal (forced oscillation stop signal) 9 NOR Circuit 10 Control circuit (only for the present invention)

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-159104 (JP, A) JP-A-62-21306 (JP, A) JP-A-59-205802 (JP, A) JP-A-51- 130150 (JP, A) Hikaru 3-28813 (JP, U)

Claims (2)

(57) [Claims] An oscillating element for oscillating / stopping oscillating according to a logical level of a first control signal; a feedback element connected between an input terminal and an output terminal of the oscillating element; A switch element connected to an input terminal of the oscillator element and connecting an input terminal of the oscillation element to a power supply according to a logic level of a second control signal; and the input terminal of the oscillation element according to a logic level of a third control signal. And a bias circuit for setting an output terminal to a predetermined potential; and a control circuit for outputting the first, second, and third control signals in response to a logical level of an oscillation control signal, based on the oscillation control signal. When controlling the oscillation / stop of the oscillation element, the control circuit outputs a logic level for stopping the oscillation element as the first control signal when the oscillation control signal is at a first logic level. Both output a logic level for temporarily setting the input terminal of the oscillation element to a power supply potential as the second control signal, and then set the input terminal and the output terminal to a predetermined potential as the third control signal until the oscillation start timing. An oscillation circuit that outputs a logic level signal to the bias circuit and outputs the logic level first control signal that causes the oscillation element to oscillate at the oscillation start timing. 2. An oscillation element for performing an oscillation operation / stop operation according to a logic level of a first control signal; a feedback element connected between an input terminal and an output terminal of the oscillation element; A switching element connected to an input terminal of the oscillator element for setting an input terminal of the oscillation element to a power supply potential according to a logic level of a second control signal; and the input terminal of the oscillation element according to a logic level of a third control signal And a bias circuit for setting an output terminal to a predetermined potential; and a control circuit for outputting the first, second, and third control signals in response to a logical level of an oscillation control signal, based on the oscillation control signal. When controlling the oscillation / stop of the oscillation element, the control circuit outputs a logic level for stopping the oscillation element as the first control signal when the oscillation control signal is at a first logic level. , After the control signal transits from the first logic level to the second logic level, a logic level for temporarily setting the input terminal of the oscillation element to a power supply potential is output as the second control signal. A logic level signal for setting the input terminal and the output terminal to a predetermined potential is output to the bias circuit as the third control signal until the oscillation start timing, and when the oscillation start timing comes, the oscillation element operates to oscillate. An oscillation circuit that outputs the first control signal having a logical level to be controlled.