JP2853718B2 - Output control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output control circuit,
In particular, the present invention relates to an output control circuit that outputs a stable output control signal when a power supply voltage rises.

[0002]

2. Description of the Related Art Conventionally, this type of output control circuit is constituted by a combination of a first output buffer control circuit 209 and a second output buffer control circuit 210 as shown in FIG. , 207 are connected to the output control circuit, the output control circuit directly generates the power supply potential 201 as an output signal,
This controls on / off of the output buffer.

The state of a conventional output control circuit when the power supply rises will be described below with reference to FIG.

In the conventional example shown in FIG. 3, a first output control signal 202 for controlling a P-ch output buffer 206 and an N-c
h output control signal 2 for controlling output buffer 207
03 is input to the output control circuit and the power supply potential 2
When 01 rises and reaches the internal circuit stable operation voltage, the first output control signal 202 becomes a logical value “L” level (hereinafter referred to as “L”), and the second output control signal 203 becomes a logical value “H”. "Level" (hereinafter referred to as "H").

The operation of each unit when the power supply potential 201 rises will be described below with reference to the timing chart of FIG. Until the power supply potential 201 reaches the internal operation stable voltage from the GND potential, the potentials of the first output control signal 202 and the second output control signal 203 are indefinite.

Further, output buffer control circuits 209 and 21
Since 0 cannot perform a normal inverter operation and the first and second output signals 204 and 205 are undefined, the potential of the output terminal 208 connected to the drains of the P, N-ch output buffers 206 and 207 is also undefined. Become.

Further, after the power supply potential 201 reaches the internal operation stable voltage, the first output control signal 202 becomes "L".
And the first output signal 204 becomes “H”, and P-c
The h output buffer 206 is turned off, and the second output control signal 203 becomes “H”. As a result, the second output signal 205 becomes “L”, and the N-ch output buffer 20
7 turns off.

Therefore, the P, N-ch output buffer 20
The output terminal 208 connected to the drains of the transistors 6,207 becomes high impedance.

[0009]

By the way, the above-mentioned conventional output control circuit has an unstable and indeterminate state of the output signal during the period from the start of power supply rise at the time of power supply start to the time when the circuit reaches a stable operating voltage. It became a state. This is a fatal problem when connecting peripheral parts and circuits that react below the circuit stable operation voltage to the output circuit.

An object of the present invention is to provide an output control circuit capable of maintaining a stable output control signal even when the power supply potential rises.

[0011]

An output control circuit according to the present invention receives an oscillation clock signal generated by first and second potentials and outputs the oscillation clock signal only when the output control signal is in an active state. A gate, a charge pump unit that pushes up or pushes down a charge potential toward the second potential with the first potential as a reference potential due to capacitive coupling of the oscillation clock signal output from the gate; Consisting of a capacitor having both ends at the first potential,
A circuit for outputting the charge potential as an output signal.

[0012]

Only when the output control signal is active, the output signal is supplied to the charge pump section which raises the charge potential to the power supply potential with reference to GND by the transmission clock signal, and the output control circuit having a capacitance between the charge potential and GND. By inputting to the gate of the N-ch output buffer, the output is controlled to determine the state of the output terminal. After the power supply potential starts to rise, no transmission clock signal is generated until the internal circuit stabilization voltage is reached, so that the charge pump unit does not operate and no charge is supplied to the charge potential.
Therefore, even if the output control signal is undefined, the charge potential and the output signal are kept at GND by the capacitance. As a result, the N-ch output buffer is always turned off, and the output terminal can stably maintain the high impedance state.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
Is a timing chart.

In the first embodiment, as shown in FIG. 1, a two-input NOR having an oscillation clock signal 1 and an output control signal 2 as inputs.
A gate 3, a charge pump section 6 for raising a charge potential 5 to a power supply potential 4 based on the GND potential by the oscillation clock signal 1, and a capacitor 7 between the charge potential 5 and GND; As the output signal 8, the source is input to GND, and the drain is input to the gate of an N-ch output buffer 9 connected to the output terminal 10.

When the power supply potential 4 rises and reaches the internal circuit stable operation voltage, the output control signal 2 becomes "H",
It is to be initialized.

The operation of each unit when the power supply potential 4 rises will be described below with reference to the timing chart of FIG. Since the oscillation circuit does not oscillate and the oscillation clock is not transmitted until the power supply potential 4 reaches the internal operation stable voltage from the GND potential, a clock signal required for the operation of the charge pump unit 2 is generated in the oscillation clock signal 1. I haven't.

Therefore, the charge pump section 6 cannot raise the charge potential 5 even if the output control signal 2 is "L", so that the charge potential 5 is maintained at the GND potential by the capacitor 7. Therefore, the output signal 8 outputs “L”, and the N-ch output buffer 9 maintains the off state.

Further, after the power supply potential 4 reaches the internal operation stable voltage, the oscillation circuit oscillates and an oscillation clock is transmitted. In this embodiment, the output control signal 2 is initialized to "H". Therefore, the output of the NOR gate 3 is fixed at "L", the charge pump unit 6 does not operate, and the N-ch output buffer keeps the off state. For this reason, the output terminal 10 stably maintains the high impedance state from the initial rise of the power supply potential 4.

When the output control signal is set to "L" in this state, the NOR gate 3 outputs a clock signal necessary for the operation of the charge pump unit 6, so that the charge pump unit 6 pushes up the charge potential 5. As a result, the charge potential 5 is maintained at the power supply potential 4. Therefore, the output signal 8 outputs “H” and the N-ch output buffer 9
Is turned on, and the output terminal 10 outputs the GND level. After the power supply potential 4 reaches the internal operation stable voltage in this way, the N-ch output buffer 9 can be controlled based on the contents of the output control signal 2.

FIG. 2 shows a second embodiment of the present invention.
Is a timing chart.

In the second embodiment, as shown in FIG. 2, the NOR gate 10 which outputs the oscillation clock signal 101 only when the output control signal 102 and the second output control signal 112 are "L".
3, a second NOR gate 113, and a charge pump section 106 which raises a charge potential 105 to a power supply potential 104 based on the GND potential by the oscillation clock signal 101.
have. Then, with reference to the power supply potential 104, GND
A second charge pump section 116 for lowering the second charge potential 115 to a potential, a charge potential 105 and GND
And between the power supply potential 104 and the charge potential 115, the capacitors 107 and 117 are provided.
As an output signal 108, an N-ch output buffer 109 having a source connected to GND and a drain connected to an output terminal 110.
Of the second charge potential 115
Is the second output signal 118, and the source is the power supply potential 10
4, the drain is input to the gate of the P-ch output buffer 119 connected to the output terminal 110.

When the power supply potential 104 rises and reaches the internal circuit stable operation voltage, the output control signal 102 and the second output control signal 112 are initialized to "H".

FIG. 5 shows a timing chart of the second embodiment. When the power supply potential 104 rises, the charge pump unit 106, the charge potential 105, the output signal 108, and the N-ch output buffer 109 perform the same operations as those described in the first embodiment, and the N-ch output buffer 10
9 keeps the off state.

The second charge pump section 116, the second charge potential 115, the second output signal 118
The −ch output buffer 119 has a configuration in which the power supply potential 4 and the GND potential of each unit described in the first embodiment are inverted.
The same operation is performed with the opposite polarity, and the P-ch output buffer 119 maintains the off state.

For this reason, the output terminal 110 is connected to the power supply potential 104.
The high impedance state is maintained stably from the beginning of the rise.

[0027]

As described above, the output control circuit of the present invention can keep the output control signal in a stable state when the power supply voltage rises. This makes it possible to easily use peripheral parts and circuits that respond to the output at a circuit stable operating voltage or less.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional technique.

FIG. 4 is a timing chart of the first embodiment of the present invention.

FIG. 5 is a timing chart of the second embodiment of the present invention.

FIG. 6 is a timing chart of a conventional example. DESCRIPTION OF SYMBOLS 1 ... Oscillation clock signal 2 ... Output control signal 3 ... NOR gate 4 ... Power supply potential 5 ... Charge potential 6 ... Charge pump part 7 ... Capacitance 8 ... Output signal 9 ... N-ch output buffer 10 ... Output terminal 101 ... Oscillation clock signal 102 output control signal 103 NOR gate 104 power supply potential 105 charge potential 106 charge pump unit 107 capacitance 108 output signal 109 N-ch output buffer 110 output terminal 112 second output control signal 113 Second NOR gate 115... Second charge potential 116... Second charge pump unit 117. Capacitance 118. Second output signal 119. P-ch output buffer 201. Power supply potential 202. ... second output control signal 204 ... first output signal 205 ... second output signal 206 ... P- h output buffer 207 ... N-ch output buffer 208 ... output terminal 209 ... first output buffer control circuit 210 ... second output buffer control circuit

────────────────────────────────────────────────── ─── Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) G06F 1/26-1/32 H03K 17/00-17/70 Practical file (PATOLIS) Patent file (PATOLIS)

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit that operates at first and second potentials, receives an oscillation clock signal generated by the first and second potentials, and operates only when an output control signal is in an active state. A gate that outputs a signal; a charge pump unit that pushes up or pushes a charge potential toward the second potential using the first potential as a reference potential by capacitive coupling of the oscillation clock signal output from the gate; An output control circuit comprising a charge potential and a capacitor having both ends of the first potential, and outputting the charge potential as an output signal. 2. A semiconductor integrated circuit that operates at first and second potentials, receives an oscillation clock signal generated by the first and second potentials, and receives the oscillation clock only when an output control signal is in an active state. A gate for outputting a signal, and a second charge potential that is raised or depressed toward the first potential with the second potential as a reference potential by capacitive coupling of the oscillation clock signal output from the gate. An output control circuit comprising: a charge pump section; a second capacitor having the second charge potential and a second capacitor having both ends of the second potential; and outputting the second charge potential as an output signal.