JPH05165551A - Output control circuit - Google Patents

Abstract

PURPOSE:To obtain the output control circuit which can maintain a stable output control signal even when a power supply potential rises. CONSTITUTION:This output control circuit is provided with a charge pump part 6, which increases a charge potential 5 to a power supply potential 4 with a GND as a reference according to a transmitting clock signal 1 only when an output control signal 2 is active, and a capacitor 7 between the charge potential 5 and the GND. By inputting an output signal 8 to the gate of an N-ch output buffer 9, an output is controlled and the state of an output terminal 10 is decided. After the power supply potential starts rising, since no transmitting clock signal 1 is generated until the potential reaches an internal circuit stable voltage, the charge pump part 6 is not operated and no electric charge is supplied to the charge potential. Therefore, even when the output control signal is instable, the charge potential and the output signal are kept at the GND by the capacitor. Thus, the N-ch output buffer is always turned off, and the output terminal can stably maintain a high impedance state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output control circuit,
In particular, the present invention relates to an output control circuit that outputs a stable output control signal when the power supply voltage rises.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, an output control circuit of this type is constituted by a combination of a first output buffer control circuit 209 and a second output buffer control circuit 210 as shown in FIG. , 207, when these output control circuits are connected to the gates, this output control circuit directly uses the power supply potential 201 as an output signal to generate.
This controls the on / off of the output buffer.

The state of the conventional output control circuit when the power is turned on will be described below with reference to FIG.

In the conventional example shown in FIG. 3, the first output control signal 202 for controlling the P-ch output buffer 206 and N-c are used.
h Second output control signal 2 for controlling the output buffer 207
03 is input to the output control circuit, and the power supply potential 2
When 01 rises and reaches the stable operation voltage of the internal circuit, the first output control signal 202 is at a logical value “L” level (hereinafter referred to as “L”) and the second output control signal 203 is at a logical value “H”. It is adapted to be initialized to the "level" (hereinafter referred to as "H").

The operation of each part when the power supply potential 201 rises will be described below with reference to the timing chart of FIG. The potentials of the first output control signal 202 and the second output control signal 203 are indefinite until the power supply potential 201 reaches the internal operation stable voltage from the GND potential.

Further, the output buffer control circuits 209 and 21
Since 0 does not perform a normal inverter operation and the first and second output signals 204 and 205 are also indefinite, the potential of the output terminal 208 connected to the drains of the P, N-ch output buffers 206 and 207 is also indefinite. Become.

Further, after the power source potential: 201 reaches the internal operation stable voltage, the first output control signal 202 is "L".
, The first output signal 204 becomes "H", and P-c
The h output buffer 206 is turned off, and the second output control signal 203 becomes "H". As a result, the second output signal 205 becomes "L", and the N-ch output buffer 20
7 turns off.

Therefore, the P, N-ch output buffer 20
The output end 208 connected to the drains of 6, 207 becomes high impedance.

[0009]

By the way, in the above-mentioned conventional output control circuit, the state of the output signal is unstable and indefinite during the period from the start of the power source rise at the time of power source rise to the stable operation voltage of the circuit. It became a state. This is a fatal problem when connecting peripheral components / circuits that react below the circuit stable operating voltage to the output circuit.

Therefore, an object of the present invention is to obtain an output control circuit capable of maintaining a stable output control signal even when the power supply potential rises.

[0011]

The output control circuit of the present invention receives an oscillation clock signal generated by the first and second potentials and outputs the oscillation clock signal only when the output control signal is in an active state. A gate and a charge pump unit that pushes up or pushes down the charge potential toward the second potential with the first potential as a reference potential by capacitive coupling with the oscillation clock signal output from the gate; It consists of a capacitor with the first potential at both ends,
It is characterized in that it has a circuit for outputting the charge potential as an output signal.

[0012]

In the output control circuit having the capacitance between the charge potential and GND, and the charge pump unit that pushes up the charge potential to the power supply potential with reference to GND by the oscillation clock signal only when the output control signal is active, By inputting to the gate of the N-ch output buffer, the output is controlled to determine the state of the output end. Since the oscillation clock signal is not generated until the internal circuit stable voltage is reached after the power supply potential starts rising, the charge pump unit does not operate and no charge is supplied to the charge potential.
Therefore, even if the output control signal is indefinite, the charge potential and the output signal are kept at GND by the capacitance. As a result, the N-ch output buffer is always in the off state, and the output end can stably maintain the high impedance state.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and FIG.
Is a timing diagram.

The first embodiment, as shown in FIG. 1, is a 2-input NOR which receives an oscillation clock signal 1 and an output control signal 2.
A gate 3, a charge pump unit 6 that pushes up the charge potential 5 to the power supply potential 4 based on the GND potential by the oscillation clock signal 1, and a capacitor 7 between the charge potential 5 and GND are provided. As the output signal 8, the source is input to GND and the drain is input to the gate of the N-ch output buffer 9 connected to the output terminal 10.

When the power supply potential 4 rises and reaches the internal circuit stable operation voltage, the output control signal 2 becomes "H",
It is supposed to be initialized.

The operation of each part when the power supply potential 4 rises will be described below with reference to the timing chart of FIG. Since the oscillation circuit does not oscillate and the oscillation clock is not transmitted until the power supply potential 4 reaches the internal operation stable voltage from the GND potential, a clock signal necessary for the operation of the charge pump unit 2 is generated in the oscillation clock signal 1. I haven't.

Therefore, the charge pump unit 6 cannot push up the charge potential 5 even if the output control signal 2 is "L", so that the charge potential 5 is held at the GND potential by the capacitor 7. Therefore, the output signal 8 outputs "L", and the N-ch output buffer 9 maintains the off state.

After the power supply potential 4 reaches the internal operation stable voltage, the oscillation circuit oscillates and the oscillation clock is transmitted. In this embodiment, the output control signal 2 is initially set to "H". Therefore, the output of the NOR gate 3 is fixed to "L", the charge pump unit 6 does not operate, and the N-ch output buffer continues to be in the off state. Therefore, the output terminal 10 stably maintains the high impedance state from the initial rising of the power supply potential 4.

When the output control signal is set to "L" in this state, the NOR gate 3 outputs the clock signal necessary for the operation of the charge pump unit 6, so that the charge pump unit 6 pushes up the charge potential 5. As a result, the charge potential 5 is maintained at the power supply potential 4. Therefore, the output signal 8 outputs "H", and the N-ch output buffer 9
Turns on, and the output terminal 10 outputs the GND level. After the power supply potential 4 reaches the stable internal operation voltage in this way, the N-ch output buffer 9 can be controlled based on the content of the output control signal 2.

FIG. 2 shows a second embodiment of the present invention, and FIG.
Is a timing diagram.

In the second embodiment, as shown in FIG. 2, the NOR gate 10 outputs the oscillation clock signal 101 only when the output control signal 102 and the second output control signal 112 are "L".
3, the second NOR gate 113, and the charge pump unit 106 that pushes up the charge potential 105 to the power supply potential 104 based on the GND potential by the oscillation clock signal 101.
have. Then, GND with reference to the power supply potential 104
The second charge pump unit 116 that pushes the second charge potential 115 to the potential, the charge potential 105, and the GND.
Capacitors 107 and 117 between the power supply potential 104 and the charge potential 115.
As an output signal 108, an N-ch output buffer 109 having a source connected to GND and a drain connected to an output terminal 110.
Input to the gate of the second charge potential 115
Is the second output signal 118, and the source is the power supply potential 10
4, the drain is input to the gate of the P-ch output buffer 119 whose output terminal 110 is connected.

When the power supply potential 104 rises and reaches the internal circuit stable operation voltage, the output control signal 102 and the second output control signal 112 are initialized to "H".

FIG. 5 shows a timing chart of the second embodiment. When the power supply potential 104 rises, the charge pump unit 106, the charge potential 105, the output signal 108, and the N-ch output buffer 109 perform the same operations as those of the units described in the first embodiment, and the N-ch output buffer 10
9 remains off.

Further, the second charge pump section 116, the second charge potential 115, the second output signal 118 and P
The −ch output buffer 119 has a configuration in which the power supply potential 4 and the GND potential of each part described in the first embodiment are reversed,
The operation is the same with the opposite polarity, and the P-ch output buffer 119 maintains the off state.

Therefore, the output terminal 110 is connected to the power supply potential 104.
The high impedance state will be maintained stably from the beginning of rising.

[0027]

As described above, the output control circuit of the present invention can keep the output control signal in a stable state when the power supply voltage rises. This makes it possible to easily use peripheral components / circuits that react to the output at a circuit stable operating voltage or lower.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional technique.

FIG. 4 is a timing diagram of the first embodiment of the present invention.

FIG. 5 is a timing diagram of the second embodiment of the present invention.

FIG. 6 is a timing chart of a conventional example. 1 ... Oscillation clock signal 2 ... Output control signal 3 ... NOR gate 4 ... Power supply potential 5 ... Charge potential 6 ... Charge pump unit 7 ... Capacitance 8 ... Output signal 9 ... N-ch output buffer 10 ... Output end 101 ... Oscillation clock signal 102 ... Output control signal 103 ... NOR gate 104 ... Power supply potential 105 ... Charge potential 106 ... Charge pump section 107 ... Capacitance 108 ... Output signal 109 ... N-ch output buffer 110 ... Output end 112 ... Second output control signal 113 ... Second NOR gate 115 ... Second charge potential 116 ... Second charge pump section 117 ... Capacitance 118 ... Second output signal 119 ... P-ch output buffer 201 ... Power supply potential 202 ... First output control signal 203 ... second output control signal 204 ... first output signal 205 ... second output signal 206 ... P- h output buffer 207 ... N-ch output buffer 208 ... output terminal 209 ... first output buffer control circuit 210 ... second output buffer control circuit

Claims (2)

[Claims] 1. A semiconductor integrated circuit which operates with first and second potentials, receives an oscillation clock signal generated by the first and second potentials, and outputs the oscillation clock signal only when an output control signal is in an active state. A charge pump unit that pushes up or pushes down a charge potential toward the second potential with the first potential as a reference potential by capacitive coupling of a gate outputting a signal and the oscillation clock signal output from the gate, An output control circuit comprising a charge potential and a capacitor having the first potential at both ends, and outputting the charge potential as an output signal. 2. A semiconductor integrated circuit which operates at first and second potentials, receives the oscillation clock signal generated by the first and second potentials, and only when the output control signal is in an active state, the oscillation clock signal. The second charge potential is pushed up or pushed down toward the first potential with the second potential as a reference potential by capacitive coupling between the gate for outputting a signal and the oscillation clock signal output from the gate. An output control circuit comprising a charge pump unit, a second capacitor having a second charge potential and a second capacitor having the second potential at both ends, and outputting the second charge potential as an output signal.