JP3297985B2 - Shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION A complementary MOS (CMOS: CMOS) comprising first and second clocked inverters and a third inverter and driven by a two-phase clock signal.
The present invention relates to a shift register formed by cascading unit register circuits having a complementary metal oxide semiconductor structure.

[0002]

2. Description of the Related Art A shift register in which unit register circuits having a CMOS structure are cascade-connected in multiple stages is driven by a low-impedance, high-output clock signal source because the unit register circuits of each stage become capacitive loads. .

[0003] The present applicant has, for example, shown in FIG.
And N-channel MOS transistors N _1, N _2, and P-channel MOS transistors P _1, the first clocked inverter INV ₁ consisting of P _2, N-channel MOS transistor N _3, N ₄ and the P-channel MOS transistor P _3, P ₄ Second clocked inverter IN comprising
And V _2, and a third inverter INV _3, 2-phase clock signals HCK, in the shift register unit register circuit complementary MOS structure that is driven to multistage cascade by HCKX, for each stage unit register SR _1, SR _2, the clock switch circuit to ··· S
C _1, SC _2, the ... provided, the unit register circuit SR _1, SR ₂ of each stage, the input and output data, ... is detected whether or not significant, the data is significant Only the unit register circuit of the stage in which the two-phase clock signal HCK, HCK is detected via the clock switch circuit
A shift register that can reduce power consumption by supplying X is proposed first (Japanese Unexamined Patent Publication No.
147598).

In the shift register, the pull-up element P ₅ is connected to the first and second clocked inverters INV ₁ and INV ₂ constituting the unit register circuit.
And by providing a pull-down element N _5, 2-phase clock signals HCK, first and second clocked inverters INV _1, INV when HCKX is not supplied
₂ is prevented from being in a floating state, and the unit register circuits SR ₁ , SR ₂ ,... Of each stage are kept in a stable state even when a two-phase clock is not supplied. .

[0005]

By the way, as described above, the unit register circuits SR ₁ , SR ₂ ,.
Are provided with clock switch circuits SC ₁ , SC ₂ ,..., Clock line capacitances CP and CQ in the unit register circuit viewed from the nodes P and Q of the clock switch circuit, and CP = CN ₁ + CP ₃ + CN. ₅ CQ = CN ₃ + CP ₁ + CP ₅ causes distortion in the clock waveform as shown in FIG. Here, CN ₁ and CN ₃ are connected to each N constituting the first and second clocked inverters INV ₁ and INV _2.
The gate capacitance of each of the channel MOS transistors N ₁ and N ₃ , and CP ₁ and CP ₃ are the respective P-channel MOS transistors P ₁ constituting the first and second clocked inverters INV ₁ and INV _2. , P ₃ , and CN ₅ , CP ₅ are the capacitances of the pull-up element P ₅ and the pull-down element N ₅ .

[0006] ΔV ₁ and ΔV ₂ shown in FIG. 5 are DC offset voltages determined by the ratio of the ON resistance of the clock switch SW to the resistance of the pull-up element P ₅ and the pull-down element N ₅ . In order to reduce the voltages ΔV ₁ and ΔV ₂ , it is necessary to lower the on-resistance of the clock switch SW and set the resistances of the pull-up element P ₅ and the pull-down element N ₅ high. In order to reduce the on-resistance of the clock switch SW, it is necessary to increase the channel width of the MOS transistor forming the clock switch SW. However, this will increase the regulatory dose of the clock bus line. Further, in order to increase the resistance of the pull-up element P ₅ and the pull-down element N ₅ , the channel length must be set longer, and the above-mentioned capacitances CN ₅ and CP ₅ are increased. This results in a reduction in speed and a trade-off relationship.

In the shift register, the power consumption increases due to the DC current flowing through the pull-up element P ₅ and the pull-down element N ₅ .

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a shift register which further reduces input capacity, operates at higher speed, and consumes less power in view of the above-mentioned conventional problems.

[0009]

SUMMARY OF THE INVENTION The present invention is a shift register in which a unit register circuit having a clocked inverter of a complementary MOS structure driven by a two-phase clock signal is cascaded in multiple stages. Detecting means for detecting whether input or output data of the register circuit is significant, pull-up means and pull-down means provided at a two-phase clock signal input terminal of a clocked inverter of each unit register circuit, First switching means for supplying the two-phase clock signal only to a unit register circuit of a stage in which input or output data is detected to be significant by the detection means, and input or output data provided by the detection means The pull-up means and the pull-up means only for the unit register circuit of the stage detected as significant. Characterized in that it comprises a second switching means for interrupting the flow of current to the down means.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A shift register according to the present invention is configured, for example, as shown in FIG. The shift register shown in FIG. 1 is an improvement of the shift register having the configuration shown in FIG. 4 previously proposed by the present applicant, and the same components are denoted by the same reference numerals. ing.

That is, this shift register has a multi-stage vertical
Connected complementary MOS unit register circuit
SR₁, SR_TwoDrive circuit integrated type liquid crystal table consisting of ...
The horizontal address circuit of the display device, each unit register
Data circuit SR₁, SR_Two, ... clock switch circuit
SC₁, SC_Two, ... from the clock line
So that the phase clock signals HCK and HCKX are supplied
Has become. Each unit register circuit SR₁, SR_Two,
.. Represent N-channel MOS transistors N
₁, N_TwoAnd P-channel MOS transistor P₁, P
_TwoClocked inverter INV₁And N
Channel MOS transistor N_Three, N _FourAnd P channel
MOS transistor P_Three, P_FourThe second clock consisting of
Quad inverter INV_TwoAnd the third inverter INV_Three
It is composed of

The unit register circuit S of each stage
The clock switch circuits SC ₁ , SC ₂ ,... Provided in R ₁ , SR _{2 ,.}
And a NOR gate NOR to which the output data D _{n + 1} is supplied;
Inverter IN for inverting the output of NOR gate NOR
V, and a pair of clock switches SW in which transistors of different conductivity types that are switching-controlled by the output of the NOR gate NOR and the inverter INV are connected in parallel. The clock switch circuits SC ₁ , SC ₂ ,.
.. Indicates that each unit register circuit SR ₁ , SR ₂ ,.
Whether or not the input and output data is significant is detected by the NOR gate NOR and the inverter INV, and only the unit register circuit of the stage where the data is detected is significant via the clock switch SW. Clock signal H
CK and HCKX are supplied.

Further, this shift register includes first and second clocked inverters INV ₁ , IV ₁ constituting unit register circuits SR ₁ , SR ₂ ,.
Pull-up element P ₅ and a pull-down element N ₅ respectively NV ₂ via the switching element P _6, N ₆ are connected. Then, the switching elements P ₆ , N of each stage
₆ is a NOR gate NOR and an inverter I of each stage constituting the clock switch circuits SC ₁ , SC ₂ ,.
Is switching-controlled by the NV output of the data it is adapted to interrupt the current flowing through the pull-up element P ₅ and a pull-down element N ₅ units register circuit stages that are detected to be significant.

In the shift register having such a configuration, whether the input and output data of each of the unit register circuits SR ₁ , SR ₂ ,... Is significant is detected by the NOR gate NOR and the inverter INV, and the data is detected. The two-phase clock signals HCK and HC are supplied via the clock switch SW only to the unit register circuit of the stage that has been detected to be significant.
Since KX is supplied, power consumption by the two-phase clock signals HCK and HCKX supplied to the clock line can be significantly reduced.

The unit register circuit S of each stage
The NOR gate NOR of each stage for detecting whether the input and output data of R ₁ , SR ₂ ,... Are significant, and the output of the inverter INV provide the switching elements P ₆ ,
The N ₆ by switching control, the data is cut off the current flowing through the pull-up element P ₅ and a pull-down element N ₅ units register circuit stage that has been detected as significant, the pull-up device P ₅ and the pull-down Element N ₅
Does not load the clock line. Thus, this shift register, the operation as is shown in the timing chart of FIG. 2, the output determined by the ratio of the resistance of the on resistance and the pull-up element P ₅ and a pull-down element N ₅ clock switch SW DC offset △ V does not occur. The drive voltage can be reduced accordingly, and the voltage can be reduced.

Also, nodes P,
The clock line capacities CP and CQ in the unit register circuit viewed from Q are as follows: CP = CN ₁ + CP ₃ CQ = CN ₃ + CP ₁ That is, gate capacities CN ₁ and CP necessary for data transfer
₁ , CP ₃ and CN ₃ only. Further, the size of the clock switch SW of each stage constituting the clock switch circuits SC ₁ , SC ₂ ,... Can be reduced, and the capacity of the bus line for the clock signal HCK can be set to the minimum. Therefore, this shift register can perform high-speed operation.

Further, the switching elements P ₆ , N of each stage
_6, since interrupting the flow of current only unit register circuit stages that the data is significant is detected pull-up element P ₅ and a pull-down element N _5, 2-phase clock signals HCK, is HCKX not supplied Sometimes, the first and second clocked inverters INV ₁ , INV ₂ are prevented from being in a floating state, and the unit register circuits SR ₁ , SR _{2 at} each stage are also supplied when a two-phase clock is not supplied. ,... Can be maintained in a stable state.

[0019] In the embodiment of the present invention shown in FIG. 1 described above, using MOS transistors as pull-up element P ₅ and a pull-down element N _5, pulled up by resistor as shown in FIG. 3 it may be configured to element P ₅ and a pull-down element N _5. In general, the area occupied by the more is the high resistance when forming a resistance wiring material becomes large, the shift register according to the present invention, the pull-up element P ₅ and a pull-down element N ₅ of the resistance value on the even circuit operation is low There is no problem, it can be configured with a small area, and the layout is simple.

[0020]

As described above, in the shift register according to the present invention, it is detected that the data is significant by the detecting means for detecting whether the input and output data of the unit register circuit of each stage is significant. Since the two-phase clock is supplied only to the unit register circuit of the stage through the first switching means, the power consumption by the two-phase clock can be significantly reduced.

In the shift register according to the present invention,
The detection means detects that the data is significant.
Pull-up means only for the unit register circuit of the
The current flowing through the pull-down means is supplied to the second switching means.
, The two-phase clock signal is supplied
First and second clocked inverters when not Is
Two-phase clock to prevent loading state
Is not supplied, the unit register of each stage
The road can be kept in a stable state.

Further, in the shift register according to the present invention, the pull-up means and the pull-down means do not load the clock line, so that the output has a DC offset Δ △.
Since V is not generated, the driving voltage can be reduced by that amount, and the voltage can be reduced. Further, the clock line capacity in the unit register circuit is only the gate capacity necessary for data transfer, and high-speed operation can be performed.

Therefore, according to the present invention, it is possible to provide a shift register that achieves low input capacitance, high-speed operation, and low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a shift register according to the present invention.

FIG. 2 is a timing chart showing the operation of the shift register.

FIG. 3 is a block diagram showing another configuration of the shift register according to the present invention.

FIG. 4 is a block diagram showing a configuration of a shift register previously proposed by the present applicant.

FIG. 5 is a timing chart showing the operation of the shift register.

[Explanation of symbols]

... INV ₁ first clocked inverter, INV ₂ second clocked inverter, INV ₃ third inverter, SR ₁ , SR ₂ ,.
SC _1, SC _2, ··· clock switch circuit, P ₅
Pull-up element, N ₅ pull-down element, P _6, N ₆
Switching element, SW clock switch, NOR
NOR gate, INV inverter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 19/00 G11C 19/28 G09G 3/20

Claims (1)

(57) [Claims] In a shift register in which unit register circuits each having a clocked inverter of a complementary MOS structure driven by a two-phase clock signal are cascaded in multiple stages, input or output data of the unit register circuits in each stage is significant. Detecting means for detecting whether or not there is a signal; pull-up means and pull-down means provided at a two-phase clock signal input terminal of a clocked inverter of a unit register circuit at each stage; The first switching means for supplying the two-phase clock signal only to the unit register circuit of the stage where the input or output data is detected to be significant by the detection unit Current flowing through the pull-up means and pull-down means only for the register circuit Second shift register and a switching means for interrupting.