JP4737333B2 - Signal output device and signal input device - Google Patents

Description

The present invention relates to a signal output device and a signal input device .

  An active matrix circuit basically includes a row-shaped selection line, a column-shaped signal line, an active element arranged at the intersection of the two, and a selection pulse for sequentially scanning each selection line to select an active element. And a horizontal scanning circuit that outputs a control pulse for controlling the opening and closing of each signal line and inputs or outputs a signal to a selected active element. The active matrix circuit having such a configuration can be applied to, for example, a liquid crystal display device and a surface pressure distribution detection device. When applied to a display such as a liquid crystal display device, the horizontal scanning circuit outputs an image signal to a pixel electrode connected to an active element. On the other hand, when applied to a surface pressure distribution detection device such as a fingerprint detector, a pressure signal applied to an electrode connected to an active element is captured.

Japanese Patent Laid-Open No. 10-68663

  The horizontal scanning circuit described above includes a transfer circuit composed of a shift register, and sequentially transfers a horizontal start pulse from the first stage to the rear stage according to a horizontal clock signal and outputs a control pulse. The vertical scanning circuit includes a vertical transfer circuit that sequentially transfers a vertical start pulse from the first stage to the rear stage according to a vertical clock signal. The start pulse and clock signal supplied to these transfer circuits are conventionally supplied from an external timing generator. However, if these are supplied from the outside, there is a problem that the configuration of the entire system to which the active matrix circuit is applied becomes complicated. Conventionally, a booster circuit is provided for boosting a low voltage start pulse or clock signal input from the outside to a high voltage internally and supplying it to the transfer circuit. However, since this booster circuit boosts the clock signal supplied to each stage of the transfer circuit with a single level shifter, the load tends to be excessive, and there are problems such as signal delay and increased current consumption. It was happening.

One embodiment of the present invention includes a plurality of elements used for signal output, and a scanning circuit that sequentially selects the plurality of elements by a control pulse, and the scanning circuit is responsive to an input start pulse. The signal output device includes a transfer circuit that sequentially transfers control pulses, and a booster circuit that boosts a clock signal for each unit of a plurality of units each including one or more stages of the transfer circuit .

According to another aspect of the present invention, a plurality of elements used for outputting signals arranged in a matrix, a vertical scanning circuit that sequentially selects columns along the horizontal direction of the plurality of elements along the vertical direction, and A column of elements selected by the vertical scanning circuit, and a horizontal scanning circuit that sequentially outputs signals to the elements along the horizontal direction, and at least one of the vertical scanning circuit or the horizontal scanning circuit is input A booster that has a transfer circuit that sequentially transfers a control pulse to the element to be selected in response to a start pulse, and that boosts the clock signal for each unit of a plurality of units each including one or more stages of the transfer circuit. A signal output device having a circuit.

Here, in the signal output device of the present invention, for each of the boosting circuits, the boosting operation is performed in accordance with the corresponding stage of the transfer circuit performing the transfer operation.

In the signal output device of the present invention, on / off of the boosting operation is directly controlled by the pulse output from the corresponding stage of the transfer circuit for each of the boosting circuits.

In the signal output device of the present invention, each stage of the transfer circuit performs a transfer operation according to the clock signal supplied from the corresponding booster circuit and outputs a control pulse, and further, according to the control pulse, the clock signal It also includes a switch for sampling and controlling the opening and closing of each signal line.

Another aspect of the present invention includes a plurality of detection units and a scanning circuit that sequentially selects the plurality of detection units by a control pulse, and the scanning circuit generates a control pulse according to an input start pulse. The signal input device includes a transfer circuit that sequentially transfers and a booster circuit that boosts a clock signal for each unit of a plurality of units each including one or more stages of the transfer circuit.

According to another aspect of the present invention, a plurality of detection units arranged in a matrix, a vertical scanning circuit that sequentially selects columns along the horizontal direction of the plurality of detection units along the vertical direction, and the vertical scanning circuit And a horizontal scanning circuit that sequentially acquires signals from the detection unit along the horizontal direction, and at least one of the vertical scanning circuit or the horizontal scanning circuit is input to A booster that has a transfer circuit that sequentially transfers a control pulse to the detection unit to be selected in accordance with a pulse, and that boosts the clock signal for each unit of a plurality of units each including one or more stages of the transfer circuit. A signal input device having a circuit.

Here, in the signal input device according to the present invention, for each of the booster circuits, the boosting operation is performed in accordance with the corresponding stage of the transfer circuit performing the transfer operation.

In the signal input device of the present invention, on / off of the boosting operation is directly controlled by the pulse output from the corresponding stage of the transfer circuit for each of the boosting circuits.

In the signal input device of the present invention, each stage of the transfer circuit performs a transfer operation according to the clock signal supplied from the corresponding booster circuit and outputs a control pulse, and further, according to the control pulse, the clock signal It also includes a switch for sampling and controlling the opening and closing of each signal line.

According to the present invention, unlike the case where the transfer start waveform (VST waveform) is sent from the outside, the waveform need not always be considered in the dot sequential transfer circuit. It is not necessary to assemble an external circuit in order to construct a waveform with an appropriate setting. As a result, the number of circuits in the entire system can be reduced. Since the waveform only needs to be input at the start of transfer, the power consumption of the internal level shifter circuit and the external system can be reduced. Since the external VST waveform does not always need to be input constantly, the influence of noise from the input is small. The delay amount between the VST waveform and the drive waveform (VCK waveform) is taken into consideration, and the operation margin is large. It can also be used for waveforms with only initial settings such as drive mode and control. When input / output of data to / from the internal dots is performed at a constant period, since signal control from the outside is not particularly entered, it is suitable for use in such a device.

Further , according to the present invention, unlike the case where the VCK waveform is sent from the outside in the point sequential transfer circuit, it is not always necessary to consider the VST waveform. In consideration of the internal load of the VCK waveform, a waveform having an appropriate setting is configured, so that no external circuit is formed and the number of circuits in the entire system can be reduced. Since there is no need to input an external VCK waveform, there is no influence of noise between input and output. Since the logical point in consideration of the delay amount of the VST waveform and the VCK waveform is latched, the dependence on the input waveform is small and the operation margin is large.

Further , according to the present invention, in the horizontal transfer circuit, unlike the case where the transfer start waveform (start waveform) is sent from the outside, it is not always necessary to consider the waveform. It is not necessary to assemble an external circuit in order to construct a waveform with an appropriate setting. This also reduces the number of circuits in the entire system. Since it is sufficient to input a waveform only at the start of transfer, the power consumption of the internal level shifter circuit and the external system can be reduced. Since the external start waveform does not always need to be input constantly, the influence of noise from the input is small. In addition, external signals can be blocked when not needed. Considering the delay amount of the start waveform and the drive waveform, the operation margin is large. The present invention can be similarly applied to a repetitive waveform having a large change in DC only by an initial setting such as a drive mode and control. When a method of synthesizing a waveform from a reference clock is used, a waveform that loops periodically can be generated from an internal waveform without external supply.

In addition , according to the present invention, in the point sequential transfer circuit, the initial state in the circuit is determined, so that it is not necessary to perform invalid transfer for initial setting. The transfer state can be initialized at any timing. In order to clear the uncertainty of the potential state in the transfer circuit depending on the previous operation state, the initial condition can always be determined and the data input / output point can be determined, so there is no abnormal operation at the start of transfer. It is not necessary to carry out idle transfer from the start of voltage application and transfer, and it is not necessary to perform an operation with a certain margin in the timing period. Immediately after inputting the waveform for initialization, input / output of data in the device can be executed immediately, and the exchange of information is expedited.

In addition , according to the present invention, the change in the duty ratio due to the transistor characteristics of the buffer is small compared to a configuration in which a level shifter is used at the circuit end and several stages of buffers are arranged to operate the maximum load amount of the wiring. . In addition, a circuit for shaping is not necessary. The loss of power consumption in the buffer itself is small, and the buffer can be driven with a small size buffer. The load for supplying the clk waveform other than the transfer period is small, and the power consumption in the level shifter is also small. The delay is small and the attenuation of the voltage amplitude value is also small. Therefore, it is possible to drive with a high margin for the shift register operation. With a configuration in which one level shifter is associated with one shift register, it is not necessary to add a dummy shift register unrelated to transfer to the first stage or the last stage, and the area of the dummy circuit, the number of circuits, power consumption, and the like can be saved. By controlling on / off of each shift register, since the overlapping period in timing is small, the power consumption of the level shifter itself can be reduced.

In addition , according to the present invention, the change in the duty ratio due to the transistor characteristics of the buffer is small compared to a configuration in which a level shifter is used at the circuit end and several stages of buffers are arranged to operate the maximum load amount of the wiring. . Further, a circuit for shaping the waveform is unnecessary. The loss of power consumption in the buffer itself is small, and it becomes possible to drive with a small size buffer. The load for supplying the clk waveform outside the transfer period is small, and the power consumption in the level shifter is also small. The delay due to the load component at the time of transmission in the first stage and the last stage is small, and the attenuation of the voltage amplitude value is also small. Therefore, driving with a high shift register operation margin is possible. Compared to the configuration in which the level shifter is configured immediately before the shift register and is controlled by the output of each shift register, the number of control lines is small and the area in the wiring portion can be reduced. Compared with the case where the level shifter is configured immediately before the shift register and the shift register and the level shifter are associated with each other at 1: 1, the circuit configuration can be widely arranged and sufficient current supply is possible. By the on / off control, the overlapping period in the timing is small, so that the power consumption of the level shifter itself can be reduced.

Further, according to the present invention, in the active matrix circuit, the reference clock (HCK waveform) for controlling the signal line to be supplied to each dot, less affected by delays that occur in the transfer circuit, the external signal Can be controlled within the delay region. Control is possible with a very small delay amount in total. The latch of the shift register circuit and the signal line can be controlled, so that the number of internal circuits can be reduced, the power consumption can be reduced, and a space-saving circuit configuration can be realized. Since the delay amount of the HST waveform and the HCK waveform is small, a circuit configuration with a large operation margin can be realized.

It is a schematic diagram which shows the surface pressure distribution detection apparatus which shows the application example of the active matrix circuit which concerns on this invention. FIG. 2 is a cross-sectional view showing a specific configuration of the active matrix circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing an overall configuration of the active matrix circuit shown in FIG. 1. It is a block diagram which shows 1st embodiment of this invention. It is a wave form diagram with which it uses for operation | movement description of 1st embodiment. It is a circuit diagram which shows the specific example of 1st embodiment. FIG. 7 is a circuit diagram showing a more specific configuration of the circuit shown in FIG. 6. It is a block diagram which shows 2nd embodiment of this invention. It is a timing chart used for operation | movement description of 2nd embodiment. It is a circuit diagram which shows the specific example of 2nd embodiment. It is a circuit diagram which shows the other specific example of 2nd embodiment. FIG. 12 is a circuit diagram illustrating a more specific configuration example of the circuit illustrated in FIG. 11. It is a block diagram which shows 3rd embodiment of this invention. It is a timing chart used for operation | movement description of 3rd embodiment. It is another timing chart with which it uses for operation | movement description of 3rd embodiment. It is a circuit diagram which shows the specific example of 3rd embodiment. It is a circuit diagram which shows the other specific example of 3rd embodiment. It is a circuit diagram which shows another specific example of 3rd embodiment. FIG. 19 is a circuit diagram showing a specific configuration of the circuit shown in FIG. 18. It is a block diagram which shows 4th embodiment of this invention. It is a timing chart used for operation | movement description of 4th embodiment. It is a circuit diagram which shows the specific example of 4th embodiment. It is a circuit diagram which shows another specific example of 4th embodiment. It is a block diagram which shows 5th embodiment of this invention. It is a timing chart used for operation | movement description of 5th embodiment. It is a circuit diagram which shows the specific structural example of 5th embodiment. It is a block diagram which shows the reference example of an active matrix circuit. It is a block diagram which shows 6th embodiment of this invention. It is a timing chart used for operation | movement description of 6th embodiment. It is a block diagram which shows the other reference example of an active matrix circuit. It is a block diagram which shows 7th embodiment of this invention. It is a timing chart used for operation | movement description of 7th embodiment. It is a circuit diagram which shows the example of a specific circuit structure of 7th embodiment. It is process drawing which shows the manufacturing method of the thin-film transistor used for the active matrix circuit concerning this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 schematically shows a surface pressure distribution detection apparatus which is an embodiment of an active matrix circuit according to the present invention. This surface pressure distribution detection device is used as a fingerprint sensor, and includes a detection unit 202 provided on a substrate 201 made of glass or the like by a thin film semiconductor process, and a flexible film 203 placed thereon. The film 203 is made of polyester or polyamide having a thickness of about 10 μm, and a conductive film is formed on the lower surface thereof by vapor deposition or the like. This conductive film is grounded. The detection unit 202 includes electrodes arranged in a matrix and thin film transistors connected to these electrodes. In detecting a fingerprint, when a finger 205 to be detected is placed on the film 203 and pressed lightly as shown in the figure, the conductive film formed on the lower surface of the film 203 at the portion where the peak (ridge) of the fingerprint hits. Is in contact with the sensor electrode connected to each thin film transistor of the detection unit 202 underneath, and as a result, each electrode is grounded through the conductive film 203. In this way, the signal voltage applied from the outside is detected through the electrodes arranged in a matrix and the corresponding thin film transistors, and the fingerprint is read. The active matrix circuit according to the present invention can be applied not only to a surface pressure distribution detection device such as a fingerprint sensor but also to an active matrix type liquid crystal display device.

  FIG. 2 is a schematic partial cross-sectional view illustrating a specific configuration example of the inspection unit 202 illustrated in FIG. 1. As shown in the figure, the active matrix circuit is formed using an insulating substrate 1 made of glass or the like. On the insulating substrate 1, element regions including sets of electrodes 2 and thin film transistors 3 connected to each other are integrated and arranged in a matrix. In the figure, only one element region is shown for easy understanding. When the thin film semiconductor device having such a configuration is used for, for example, a surface pressure distribution detection circuit, a conductive film 4 having anisotropy is overlaid on the insulating substrate 1. Each electrode 2 is sensitive to a signal voltage applied from directly above the conductive film 4 for each element region. Each thin film transistor 3 is sequentially turned on / off to detect a signal voltage applied to the corresponding electrode 2. The sensitive portion SR in which the electrode 2 is formed extends so as to cover the corresponding thin film transistor 3 and the non-sensitive portion NSR in which the signal wiring 9 and the gate wiring are formed, and the surface of the sensitive portion SR in each element region. Is in the top position. In other words, the electrode 2 entirely shields the thin film transistor 3, the signal wiring 9, and the gate wiring included in the insensitive portion NSR. With this configuration, when a signal voltage applied through the conductive film 4 is detected, an adverse effect of a parasitic electric field generated in the vertical direction from the signal wiring 9 and the gate wiring is prevented. That is, the surface of the insulating substrate 1 is basically only the electrode 2 when viewed from the conductive film 4 side, and the detection power is increased.

  The structure of the apparatus will be described in detail with reference to FIG. The thin film transistor 3 has a top gate structure, in which a gate electrode 6, a gate insulating film 5, and a semiconductor thin film 7 are laminated in order from the top. Specifically, a semiconductor thin film 7 made of polycrystalline silicon or the like is patterned in an island shape on an insulating substrate 1 made of quartz glass or the like. A gate electrode 6 is patterned on the gate insulating film 5 thereon. Although not shown, a gate wiring extends from the gate electrode 6. A source region D and a drain region S are formed in the semiconductor thin film 7 on both sides of the gate electrode 6. The gate electrode 6 and the semiconductor thin film 7 are covered with a first interlayer insulating film 8. A signal wiring 9 made of a metal film is patterned thereon, and is electrically connected to the source region S of the thin film transistor 3 through a contact hole. The signal wiring 9 is covered with a second interlayer insulating film 10. The electrode 2 is patterned on the second interlayer insulating film 10. The electrode 2 is electrically connected to the drain region D of the thin film transistor 3 through a contact hole opened in the second interlayer insulating film 10 and the first interlayer insulating film 8. As is apparent from the drawing, the electrode 2 is formed so as to shield the thin film transistor 3, the signal wiring 9 and the gate wiring included in the non-sensitive portion NSR from the conductive film 4. The electrode 2 is formed by patterning a transparent conductive film made of, for example, ITO. When applied to a surface pressure distribution detection apparatus, the thin film semiconductor device does not necessarily need to be transparent, and therefore the electrode 2 is not necessarily formed of a transparent conductive film such as ITO. However, since ITO has a practically sufficient level of chemical stability and mechanical strength and is excellent as an electrode material, it is used in the present embodiment. However, the present invention is not limited to ITO, and it is of course possible to use aluminum or the like for the electrode 2, for example.

  Next, the manufacturing method of the thin film semiconductor device will be briefly described with reference to FIG. First, amorphous silicon is deposited on the insulating substrate 1 made of heat-resistant quartz glass or the like by CVD or the like. Subsequently, solid phase growth is performed at a processing temperature of 1000 ° C. or higher to convert amorphous silicon into polycrystalline silicon. The semiconductor thin film 7 thus improved in performance is patterned into an island shape. A gate insulating film 5 is formed thereon. Specifically, the semiconductor thin film 7 is heat-treated at a high temperature of 1000 ° C. or higher to form a thermal oxide film, which is used as the gate insulating film 5. Further, a gate electrode 6 made of polycrystal silicon having a reduced resistance is formed on the gate insulating film 5. Impurity ions are implanted at a high concentration into the semiconductor thin film 7 by ion implantation or the like using the gate electrode 6 as a mask to form the drain region D and the source region S. Subsequently, a first interlayer insulating film 8 made of PSG or the like is deposited by CVD or the like. After opening a contact hole in the first interlayer insulating film 8 by etching or the like, metal aluminum or the like is deposited thereon by sputtering. The metal aluminum is patterned into a predetermined shape and processed into a signal wiring 9. The signal wiring 9 is electrically connected to the source region S of the thin film transistor 3 through a contact hole. Further, a second interlayer insulating film 10 made of PSG or the like is deposited so as to cover the signal wiring 9. After opening a contact hole through the second interlayer insulating film 10 and the first interlayer insulating film 8, ITO is deposited by sputtering or the like. This ITO is patterned into a predetermined shape and processed into an electrode 2. The electrode 2 is electrically connected to the drain region D of the thin film transistor 3 through a contact hole opened in the second interlayer insulating film 10 and the first interlayer insulating film 8. The gate wiring is also processed simultaneously with the patterning of the gate electrode 6.

FIG. 3 is a schematic circuit block diagram showing the overall configuration of the active matrix circuit shown in FIGS. 1 and 2. As shown in the figure, this circuit includes a plurality of gate wirings (selection lines) 6a arranged in rows and a plurality of signal wirings 9 arranged in columns. An electrode 2 and a thin film transistor 3 are formed at each intersection of both wirings 6a and 9. The source region of the thin film transistor 3 is connected to the corresponding signal wiring 9, the drain region is connected to the corresponding electrode 2, and the gate electrode is connected to the corresponding gate wiring 6a. Although not shown, the surfaces of the electrodes 2 arranged in a matrix are covered with an anisotropic conductive film. A built-in vertical scanning circuit 20 is connected to the plurality of gate wirings 6a, and the selection pulses φ _V1 , φ _V2 ,..., Φ _VM are output to vertically scan the gate wirings 6a, and 1 for each horizontal period. The thin film transistors 3 for the rows are turned on, and the corresponding electrodes 2 for one row are selected. Further, a built-in horizontal scanning circuit 40 is connected to each signal wiring 9. The horizontal scanning circuit 40 sequentially scans each signal wiring 9 within one horizontal period, and reads a signal voltage from the electrode 2 through the transistor 3 in an on state. This signal voltage is applied to each electrode 2 via a conductive film. Specifically, each signal line 9 is connected to the signal line 104 via the switch 103, and the read signal voltage is sequentially supplied to the external detection circuit 60. The detection circuit 60 analyzes the read signal voltage to recognize a fingerprint pattern or the like. The horizontal scanning circuit 40 sequentially outputs sampling pulses φ _H1 , φ _H2 , φ _H3 ,..., Φ _HN and sequentially opens and closes the switches 103 to sample the signal voltage from the corresponding signal wiring 9. As described above, the electrodes 2 arranged in a matrix form the sensor area 80. Around the periphery, a vertical scanning circuit 20 and a horizontal scanning circuit 40 are arranged. The vertical scanning circuit 20 includes a vertical transfer circuit (shift register) that sequentially transfers the vertical start pulse VST from the first stage to the rear stage according to the vertical clock signals VCK1 and VCK2. Further, the horizontal scanning circuit 40 sequentially transfers the horizontal start pulse HST from the first stage to the rear stage according to the horizontal clock signals HCK1 and HCK2, and outputs a control pulse that is the source of the sampling pulse (shift register). Is included. Note that VCK1 and VCK2 are in opposite phase to each other. Similarly, HCK1 and HCK2 are also in a reverse phase relationship.

  FIG. 4 shows an embodiment of an active matrix circuit according to the first aspect of the present invention, and particularly shows a block configuration around a vertical scanning circuit. As shown in the figure, the vertical scanning circuit of the present active matrix circuit includes a V transfer circuit 22 that sequentially transfers an input start pulse VST from a first stage to a rear stage according to a clock signal to form a selection pulse, and a rear stage. And a VST generating circuit 21 that processes the selection pulse output from the signal, forms a start pulse internally, and inputs it to the leading stage of the V transfer circuit 22. In addition, a level shifter 30 for boosting a reset signal input from the outside and a start selection circuit 23 are provided. In the first transfer operation, the start selection circuit 23 selects a reset signal input from the outside and supplies it to the VST generation circuit 21. On the other hand, when the next transfer operation is repeated, the start selection circuit 23 performs the final stage of the V transfer circuit 22. The timing waveform (selection pulse) output from is selected and supplied to the VST generation circuit 21.

  FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. As shown in the figure, when the first VST is applied to the V transfer circuit 22 via the start selection circuit 23, it is sequentially transferred according to VCK1 and a selection pulse is output. In the timing chart, the first stage selection pulse is represented by gate1 and the second stage selection pulse is represented by gate2. When the transfer circuit 22 outputs the final stage gate, which is the final stage selection pulse, this is supplied to the VST generation circuit 21 via the start selection circuit 23 to form the next VST. In this way, when VST is supplied for the first time, the VST is sequentially generated internally and the transfer operation is continued. In this way, since the loop circuit generates VST from the initial setting waveform (RESET waveform) and the internal waveform, transfer control can be performed without inputting the vertical transfer start waveform one by one. Since the transfer can be started at an arbitrary timing and the internal circuit and system circuit for the transfer waveform are not required, the power consumption of the entire system can be reduced and the circuit can be reduced. When the final stage transfer ends, a start signal can be generated, and the transfer can always be performed constantly without depending on an external signal. Since the VST waveform is formed from the signal in the circuit, a circuit configuration with a small operation delay and a large operation margin can be realized by the booster circuit of the input waveform.

  FIG. 6 is a circuit diagram showing a specific configuration example of the circuit shown in FIG. In this example, the VST generation circuit 21 is configured by an RS flip-flop (RSFF), and the start selection circuit 23 is configured by 2 NAND. A delay circuit 24 is inserted between the RSFF 21 and the V transfer circuit 22. In this example, the VST generation circuit 21 uses RSFF that starts the VST waveform at the timing latched to the final waveform of the V transfer circuit 22 and stops at the end of the first transfer stage. In consideration of the first stage, the RSFF set / reset is controlled, and the set waveform employs a NAND control system. The VST generation circuit 21 may use a D flip-flop (DFF) instead of the RSFF shown in FIG. 6 and latch the final waveform as it is at the first stage timing.

  FIG. 7 is a circuit diagram illustrating a specific configuration example of the RSFF 21 and the 2NAND 23 illustrated in FIG. In this example, both the RSFF 21 and the 2NAND 23 are composed of thin film transistors (TFTs) having a CMOS structure.

  FIG. 8 schematically shows an embodiment of an active matrix circuit according to the second aspect of the present invention. As shown in the figure, the horizontal scanning circuit includes an H transfer circuit 41 that sequentially transfers the horizontal start pulse HST from the first stage to the rear stage in accordance with the horizontal clock signal HCK and outputs a control pulse. In this example, HST and HCK input from the outside are supplied to the H transfer circuit 41 via the level shifter 31 and the buffer 32. On the other hand, the vertical scanning circuit processes the vertical transfer pulse 22 that sequentially transfers the vertical start pulse VST from the first stage to the rear stage according to the vertical clock signal VCK, and the control pulse that is output from the rear stage of the horizontal transfer circuit 41. And a VCK generation circuit 25 that generates a vertical clock signal VCK and supplies the vertical clock signal VCK to the vertical transfer circuit 22. VST is supplied from the vertical start pulse generating circuit 24. A specific configuration example of the VST generation circuit 24 is as described above.

  FIG. 9 is a timing chart for explaining the operation of the circuit shown in FIG. First, paying attention to the horizontal transfer circuit side, HST is transferred by HCK1 and HCK2, and control pulses are sequentially output. These pulses are sequentially supplied from the first stage signal line switch to the final stage signal line switch. VCK1 and VCK2 are internally created in accordance with the control pulse output from the final stage of the horizontal transfer circuit. Next, paying attention to the vertical transfer circuit side, VST is sequentially transferred by VCK1 and VCK2 described above, and a selection pulse is output. These selection pulses are respectively supplied to the first stage gate line switch, the second stage gate line switch,..., The final stage gate line. As described above, the subject of this embodiment is a circuit that generates a vertical drive waveform (VCK waveform) from an internal waveform at a timing obtained from the input of a horizontal drive waveform in a point sequential transfer circuit. A loop circuit is used so as to operate the vertical line (Vgate) of the next stage as the horizontal transfer circuit (H shift register) ends. Since the first stage gate line operates before the start of the horizontal transfer start waveform (HST waveform), the first stage operates with the initial setting, and the loop circuit configuration uses the H shift register final stage timing after the next stage. Yes. Therefore, the circuit configuration can be controlled without inputting a transfer waveform from the outside to the vertical transfer circuit (V shift register). The VCK is latched at the timing of the H shift register circuit, and the gate line switch of each dot is controlled by using the waveform as the drive waveform, so that there is little delay from the external signal, no external noise is received, and the signal line at the optimum point Can be controlled. As a result, waveform supply with a constant duty ratio and delay amount is possible, and a circuit configuration with a large operation margin can be realized. Since the VCK waveform is generated from the signal inside the circuit, an external system circuit is unnecessary, and internal circuits such as an internal booster circuit (level shifter circuit) and a phase difference adjustment circuit are unnecessary. As a result, the external input waveform can be reduced and the power consumption of the circuit can be reduced.

  FIG. 10 is a block diagram illustrating a configuration example of the circuit illustrated in FIG. In this example, as the VCK generation circuit 25, a D flip-flop that uses the H final stage waveform as input and latches it is used. In this case, it is necessary to select the final stage waveform in consideration of the internal circuit delay and transmission delay at the final stage and the total timing of the latch circuit. This is somewhat likely to cause a delay in the internal circuit, and the delay amount of the generated waveform itself tends to be large.

  FIG. 11 shows an example in which the counter operation is performed at the timing latched to the H final stage waveform as the VCK generation circuit 25. In the method of counting the internal initial conditions from the waveform output from the H final stage shift register, the inversion operation of each condition is latched to the waveform output from the H final stage shift register. In this case, if the initial conditions are determined, the internal delay amount can be reduced. The waveform can be adjusted by the output point. In this example as well, the final stage waveform of the shift register is used, and a loop circuit synchronized therewith is formed, and a VCK waveform is generated each time the loop is made to enable a transfer operation.

  FIG. 12 shows a specific configuration example of the VCK generation circuit 25 shown in FIG. Control pulses HOUT1 and HOUT2 output from the final stage of the H shift register are processed to output VCK1 and VCK2 internally. The CMOS circuit configuration is a combination of an N channel thin film transistor and a P channel thin film transistor.

  FIG. 13 is a schematic block diagram showing an embodiment of an active matrix circuit according to the third aspect of the present invention, and particularly shows a configuration around a horizontal scanning circuit. As shown in the drawing, the horizontal scanning circuit sequentially transfers the input start pulse in according to the clock signal clk from the first stage to the rear stage and outputs the control pulse g, and the horizontal scanning circuit outputs from the rear stage. A start pulse generating circuit d that processes the control pulse g to form a start pulse in internally and inputs it to the leading stage of the transfer circuit j is provided. In addition, a level shifter b that boosts an externally input start pulse in and a start waveform selection circuit c that selects an external start pulse in at startup and supplies it to the transfer circuit j are provided. Further, a control circuit e for controlling the level shifter b and the start waveform selection circuit c is provided. When a transfer start waveform (start waveform f) for the transfer circuit j is input from the outside (a in the figure), the voltage is boosted by the internal booster circuit b (level shifter). Note that the start waveform may be directly input without boosting. In this case, since a high voltage pulse must be generated as a start waveform from the beginning, power consumption increases when viewed as a whole system. This start waveform is input to the shift register j. After the transfer is completed, the control circuit e stops the operation of the level shifter b, determines the potential, and sets the input to be DC, in order to switch to the circuit side that creates the start waveform internally. That is, once the initial waveform is input from the outside, it is not necessary to send the waveform, so the voltage is fixed to High or Low. Once the transfer operation is started, a loop type transfer circuit configuration is formed in which start pulses are sequentially formed thereafter. The transfer can be started at an arbitrary timing, and after inputting the first waveform, the circuit that outputs the waveform does not need to operate, and the entire system can be reduced in power and the circuit can be reduced. When the final stage transfer ends, a start signal can be generated, and the transfer can always be performed constantly without depending on an external signal. In addition, low power consumption can be realized by blocking external signals.

  FIG. 14 is a timing chart for explaining the operation of the circuit shown in FIG. At the time of start-up, an externally input start pulse in is sequentially transferred by the clock signal clk, and control pulses for controlling the opening and closing of the signal lines are sequentially output. When a control pulse assigned to the last stage of the signal line is output, this is processed to internally create a start pulse in. As a result, the transfer operation is repeated with the internal start pulse while the external start pulse in is cut off thereafter. In particular, the example shown in FIG. 14 creates a start waveform by latching the control pulse output from the final stage.

  FIG. 15 is a timing chart showing a modification of the operation of the circuit shown in FIG. In this example, when a control pulse assigned to the last stage of the signal line is output, a predetermined selection period is set according to this. The clock signal clk is selected within this selection period, and this is processed and synthesized into an internally generated start pulse in.

  FIG. 16 illustrates a specific configuration example of the circuit illustrated in FIG. 13, and the operation thereof is as illustrated in the timing chart illustrated in FIG. 14. In this example, a DFF is used as the start waveform generation circuit d. Using DFF, the waveform output from the last stage of the shift register is latched with clk at the timing of the first stage to generate a start waveform. In this case, it is necessary to select the final stage waveform in consideration of the internal circuit delay and transmission delay at the final stage and the total timing of the first stage latch circuit.

  FIG. 17 shows another specific configuration example of the circuit shown in FIG. 13, and its operation is as shown in the timing chart of FIG. In this example, RSFF is used as the start waveform generation circuit d. RSFF raises the start waveform at the timing latched in the final waveform, and falls at the end of the first transfer stage. The start waveform is started from the waveform output from the last stage of the shift register, and the start waveform is stopped from the waveform at the end of the first stage. In this case as well, the internal circuit delay and transmission delay, and the total timing of the first stage latch circuit are considered. However, it is necessary to select the final waveform.

  FIG. 18 is a block diagram showing still another specific example of the circuit shown in FIG. 13, and the operation thereof is as shown in the timing chart of FIG. In this example, a circuit that synthesizes a start waveform from a reference clock (CLK waveform) at the timing latched in the final waveform is used as the start waveform generation circuit d. That is, this is a circuit that selects the clk waveform corresponding to the start waveform timing from the waveform output from the last stage of the shift register, selects the clk waveform that matches the timing at the end of the first stage, and synthesizes it from the RSFF. In this case, the delay amount is only the delay of the external clk waveform itself, and it is necessary to select the clk timing. In this way, the shift register is looped using the final waveform of the shift register. A start waveform is generated for each loop.

  FIG. 19 is a circuit diagram showing a specific configuration example of the start waveform generation circuit d shown in FIG. The CMOS structure is a combination of an N-channel thin film transistor and a P-channel thin film transistor.

  FIG. 20 is a block diagram showing an embodiment of an active matrix circuit according to the fourth aspect of the present invention. The horizontal scanning circuit includes a horizontal transfer circuit 41 that sequentially transfers a horizontal start pulse from the first stage to the rear stage in accordance with a horizontal clock signal and outputs a control pulse. The vertical scanning circuit includes a vertical transfer circuit 22 that sequentially transfers vertical start pulses from the first stage to the rear stage in accordance with a vertical clock signal. The H transfer circuit 41 and the V transfer circuit 22 described above are connected to the sensor area 80. As a feature, a reset circuit 33 is provided, and the horizontal transfer circuit 41 and the vertical transfer circuit 22 are forcibly reset in response to a reset pulse supplied from the outside and returned to the initial state.

  FIG. 21 is a timing chart for explaining the operation of the circuit shown in FIG. First, when reset signals RESET1 and RESET2 are input from the outside, both the vertical transfer circuit and the horizontal transfer circuit are once initialized. Thereafter, HST is supplied from the outside, and HST is sequentially transferred by the horizontal transfer circuit in accordance with HCK1 and HCK2 supplied from the outside, and a control pulse assigned to each signal line is output. When a control pulse is output from the final stage of the horizontal transfer circuit, the next and subsequent HSTs are generated internally based on this. At the same time, VCK is also created internally. The vertical transfer circuit operates in the same manner as the horizontal transfer circuit. First, after forcibly initializing in accordance with a reset pulse, VST is transferred in accordance with VCK, and selection pulses are sequentially output to each selection line.

  As described above, the data in the transfer circuit (shift register) is determined before transfer using the reset pulse. The initial setting waveform is input from the outside, and then each waveform for starting circuit transfer is sent. When the initialization signal (reset signal) is received, the H shift register and the V shift register are determined to be High or Low because the circuit configuration is configured to determine the potential state in the circuit. Peripheral circuits (signal line control switch, level shifter, etc.) are also sequentially set to the determined voltage according to the determined conditions, so that the dot (pixel) controlled by the H shift register and V shift register is the first dot in the first stage. It is initialized. When a transfer signal such as HST or HCK is sent, the first dot signal at the first stage is output or input, and transfer starts. Since all circuits are initialized, there is no indeterminate state in the circuit, so there is no need to start operation from the middle stage of the level shifter or input / output duplicate signals. Capturing / writing is possible. When a reset signal is input in the middle of the transfer, the shift register is initialized and becomes operable again from the first stage, so that it is used for the initialization configuration of each circuit. Since it is possible to input and output data for an extremely short time, it is not necessary to input idle timing such as invalid transfer.

  FIG. 22 is a circuit diagram showing a specific configuration example of the reset circuit 33 shown in FIG. This reset circuit is actually provided at each stage of the shift register constituting the transfer circuit. FIG. 22 shows a method based on through current control of a thin film transistor. Current consumption is large because reset is performed using a through current, but initialization in the circuit is fast, and the load on the circuit when initialization is not set is low, so there is little impact on circuit timing such as transfer In addition, the circuit configuration has a small amount of delay. In the circuit, H and L enclosed in quotation marks represent a potential state when a reset is applied.

  FIG. 23 shows a specific configuration example of the reset circuit 33 similarly shown in FIG. 20, and is incorporated in each shift register stage. This example is a logic-determined initialization method. Since the potential of each transistor is determined, the current for the load charge such as resistance and capacitance is sufficient, and the current consumption is small. However, since this circuit passes on the transfer, the delay of the circuit itself affects the timing. This is effective when there is no influence of the circuit internal delay.

  FIG. 24 is a block diagram showing an embodiment of an active matrix circuit according to the fifth aspect of the present invention. In this example, a low-voltage clock signal (external CLK) input from the outside is boosted to a high voltage, and each stage of the corresponding transfer circuit (in the example shown, a stage composed of shift register A and shift register B). Is provided with a booster circuit for supplying to This booster circuit has a level shifter c for boosting the clock signal CLK individually corresponding to each stage of the transfer circuit (a pair of shift register A and shift register B). The level shifter c performs a boost operation in accordance with the transfer operation of the corresponding stage e of the transfer circuit. In particular, in the level shifter c, on / off of the boosting operation is directly controlled by a pulse output from the corresponding stage e of the transfer circuit. The control pulse output from each stage e of the transfer circuit is supplied to a switch for turning on / off the signal line via the signal line control circuit d.

  FIG. 25 is a timing chart for explaining the operation of the level shifter c shown in FIG. Each stage e of the transfer circuit (shift register) performs transfer from the point where the transfer start waveform (in waveform) is input. A control switch is provided in the level shifter c so that the booster circuit (level shifter) c can operate simultaneously with the operation of the shift register. Specifically, the H_Switch and L_Switch waveforms are input as control waveforms, and the operation of the level shifter c is controlled using these waveforms. The voltage amplitude is boosted from the external drive waveform (external clk waveform) by the action of the level shifter c, and the transfer latch waveform clk is operated. The shift register e is controlled by the clk waveform and starts transfer. At this time, a control pulse k to the signal line is also output. The internal clk output from the level shifter c is configured with an optimum transistor size to which a waveform is supplied according to a buffer size in consideration of a load depending on the number of input gate lines. Also, clk is boosted immediately before use. After the transfer period is ended by the shift register operation, Low and High signals are given to H_Switch and L_Switch, respectively. In order to stop the operation of the level shifter c after the shift register itself outputs the control pulse, the clk waveform is controlled by the setting in the level shifter according to the final transfer signal, and the operation of the level shifter is stopped. After the operation is stopped, the voltage value of each clk waveform of the shift register is determined, and the transfer is kept in the holding state. For example, clk is held high. After the transfer is completed, the external HCK waveform is not accepted because of the DC operation. In this manner, voltage boosting of the clk is started in synchronism with the input of the transfer circuit, the voltage state of the boosting circuit is determined in synchronism with the end timing of the transfer, and the operation of the clk is performed. Is not applied to the shift register, and the transient current is suppressed. The clk of the low voltage input waveform is not boosted until the timing of use, and prevents waveform attenuation and increase in timing delay due to transmission inside the circuit. Since the level shifter is controlled by the signal of the shift register, the buffer of the level shifter is configured with the load range of the minimum operation of the shift register, and the timing at which the level shifter operates adjacent to each other at the time of transfer is reduced, and the consumption is low. Electricity becomes possible. Since boost driving is performed immediately before transfer, it is possible to supply a shaped waveform with a small circuit size, a small deviation in duty ratio, and a small delay amount.

  FIG. 26 is a circuit diagram showing a specific configuration example of the level shifter c shown in FIG. This circuit has a CMOS configuration in which an N-channel thin film transistor and a P-channel thin film transistor are combined. In the figure, external inputs cLk of low voltage and opposite phase are represented by in1 and in2, and cLk of the high voltage after boosting is represented by out1 / out2.

  FIG. 27 is a block diagram illustrating a reference example of the level shifter (LVS). The level shifter LVS is used at the circuit end, and several stages of buffers are arranged to drive the maximum load of wiring. The duty ratio changes depending on the N-channel and P-channel transistor characteristics of the buffer. A phase adjustment circuit m is necessary for the shaping. In addition, since the final buffer having a large size always performs a transient operation, the power consumption of the buffer itself is large. Since the clk waveform is supplied to the shift register also at timings other than the transfer period, a load is applied and power consumption in the level shifter is large. The first and last stages of the shift register have a large delay due to the load component at the time of transfer, and the Vth of the shift register operation becomes a transfer with a very severe margin due to the attenuation of the voltage amplitude value. Since one shift register is not associated with one level shifter, a dummy shift register not related to transfer must be added to the first and last stages of the transfer circuit, and the circuit configuration and consumption in that area Electricity is wasted.

  FIG. 28 is a block diagram showing a configuration example of an active matrix circuit according to the sixth aspect of the present invention. Basically, it is similar to the configuration shown in FIG. The difference is that the booster circuit has a level shifter c that individually boosts the clock signal CLK in correspondence with a group having two or more stages of the transfer circuit as a unit. That is, the previous example has one level shifter per shift register, whereas this example has one level shifter per two shift registers. Each level shifter c is set so as to perform a boosting operation in accordance with a pair of two or more stages of the transfer circuit performing a transfer operation.

  FIG. 29 is a timing chart for explaining the operation of the circuit shown in FIG. The operation of this embodiment will be described with reference to FIG. 29 with reference to FIG. The transfer circuit (shift register e) performs transfer from the point where the transfer start waveform (in waveform) is input. When the RS flip-flop d is used as the control circuit of the level shifter c together with the operation of the shift register, the set signal (l in the figure) is transferred, and the H_Switch and L_Switch (k, l in the figure) waveforms are used as the control waveforms. A Low signal is applied to turn on the operation of the level shifter. The voltage amplitude is boosted from the external drive waveform (external clk waveform) by the action of the level shifter circuit, and the transfer latch waveform clk is operated. The shift register is controlled by clk and starts transfer. At this time, a control signal to the signal line is also output. The waveform is supplied by the buffer size considering the load of the clk input supplied from the level shifter, and the level shifter c is configured with the minimum transistor size. Further, the level shifter c starts boosting immediately before the corresponding transfer circuit stage set enters the operating state. After the corresponding stage of the shift register is finished operating by clk supplied from the level shifter, the reset signal (n in the figure) is transferred to RSFF, and the Low and High signals are given to H_Switch and L_Switch, respectively, and the operation of the level shifter is stopped. Let At this time, the voltage value of each clk waveform of the shift register is determined, and the transfer is kept in the hold state. After the transfer is completed, the external clk waveform is not accepted because of the DC operation. Thus, by associating one level shifter with a plurality of sets of transfer circuits, the circuit scale as a whole can be reduced as compared with the case of 1: 1 correspondence. In particular, this configuration is preferably applied to a level shifter located in the middle stage in the transfer circuit.

  FIG. 30 is a schematic block diagram illustrating a reference example of the level shifter. In this example, the level shifter LVS is arranged immediately before the shift registers S / RA, S / B..., And the level shifter LVS is controlled by the output of each shift register via AND. Since the output lines proportional to the number of stages of the shift register connected to the level shifter are arranged in AND, the area in the wiring portion becomes large and the circuit area is limited.

  FIG. 31 is a block diagram showing an embodiment of an active matrix circuit according to the seventh aspect of the present invention. As shown in the figure, this circuit includes a booster circuit that boosts low-voltage clock signals HCK1 and HCK2 input from the outside to a high voltage and supplies them to each stage of the transfer circuit (shift registers A and B). . The booster circuit has a plurality of level shifters for individually boosting the clock signals HCK1 and HCK2 corresponding to each stage of the transfer circuit (shift register A and shift register B). Each stage of the transfer circuit (shift registers A and B) performs a transfer operation according to the clock signals HCK1 and HCK2 supplied from the corresponding level shifter LVS and outputs a control pulse, and further, according to this control pulse, a clock signal HCK1. , HCK2 and a switch 102 for controlling opening / closing of each signal line.

  FIG. 32 is a timing chart for explaining the operation of the circuit shown in FIG. The operation of the active matrix circuit will be described based on FIG. 32 with reference to FIG. A transfer drive waveform (HCK waveform) of the transfer circuit (shift registers A and B) is input from the outside, and the voltage is boosted by an internal booster circuit (level shifter). The boosted HCK waveform is used as the latch waveform of the shift register. At the time of transfer, the HCK waveform switch 102 is closed to obtain the waveform of the signal line control switch 103 using the output waveform of the operation timing of the shift register. When the input of HCK matches the input of the signal line switch control, the next waveform change point (latch waveform) becomes the input waveform to the signal line control switch 103 as it is. At the end of the transfer, the switch 102 that matches the input of HCK and the input of the signal line switch control is closed and determined in a DC manner. At this time, if the method of feeding back the deterministic voltage in the wiring to the control of the shift register output waveform is taken, instability occurs when the initial state is not determinable, and a configuration in which the initial setting waveform is input again becomes necessary. As the voltage is determined, the signal line control switch 103 is turned off and maintains the previous state. At the time of transfer, each signal line is controlled by the switch 103. By controlling this switch 103 with HCK, it is possible to control within the delay region from the external signal regardless of the delay amount generated in the transfer circuit. Therefore, a very small delay amount is sufficient. By latching HCK at the timing generated by the transfer circuit (shift register circuit) and controlling the switch using the waveform as the input waveform of the control circuit, the signal line can be controlled at a point with little delay from the external signal. HCK can have a role of a waveform as a latch in the shift register circuit and a control switch of the signal line, and the number of circuits can be reduced and space can be saved.

  FIG. 33 is a circuit diagram showing a specific configuration around switches 102 and 103 in the circuit shown in FIG. The hck1 and hck2 output from the level shifter are gated by the switch 102 by the CNT output from the corresponding shift register, and then applied to the switch 103 configured by a transmission gate to control on / off of the corresponding signal line. To do.

  A thin film transistor is suitable as an active element (switching element) of the active matrix circuit described above. In particular, polycrystalline silicon is used for a semiconductor thin film that becomes an active layer (element region) of a thin film transistor. The polycrystalline silicon thin film transistor is used not only as a switching element but also as a circuit element, and a peripheral drive circuit such as a scanning circuit or a booster circuit can be incorporated on the same substrate together with the switching element. In addition, since the polycrystalline silicon thin film transistor can be miniaturized, the area occupied by the switching elements in the active matrix structure can be reduced, and high definition of the pixels can be achieved. By the way, the conventional polycrystalline silicon thin film transistor has a maximum process temperature of about 1000 ° C. in the manufacturing process, and quartz glass having excellent heat resistance has been used as an insulating substrate. It was difficult to use a glass substrate having a relatively low melting point in the manufacturing process. However, the use of a low-melting glass material is indispensable for reducing the cost of the active matrix circuit. Therefore, in recent years, development of a so-called low temperature process in which the maximum process temperature is 600 ° C. or less has been promoted. In particular, the low-temperature process is extremely advantageous in terms of cost when manufacturing a high-definition active matrix device.

  FIG. 34 is a process diagram showing an example of a method of manufacturing a thin film transistor used in the active matrix circuit according to the present invention. In this embodiment, a low-temperature manufacturing process of an n-channel type thin film transistor is shown for convenience, but the same applies to the p-channel type only by changing the impurity species (dopant species). Here, a manufacturing method of a bottom-gate thin film transistor is described. First, as shown in (a), Al, Ta, Mo, W, Cr, Cu or an alloy thereof is formed with a thickness of 100 to 250 nm on an insulating substrate 1 made of glass or the like, and patterned to form a gate electrode 6. To process.

Next, a gate insulating film is formed on the gate electrode 6 as shown in FIG. In this embodiment, the gate insulating film has a two-layer structure of gate nitride film 5a (SiN _x ) / gate oxide film 5b (SiO ₂ ). The gate nitride film 5a was formed by a plasma CVD method (PCVD method) using a mixture of SiH ₄ gas and NH ₃ gas as a source gas. Note that atmospheric pressure CVD or reduced pressure CVD may be used instead of plasma CVD. In this embodiment, the gate nitride film 5a is deposited with a thickness of 50 nm. In succession to the formation of the gate nitride film 5a, the gate oxide film 5b is formed with a thickness of about 200 nm. Further, a semiconductor thin film 7 made of amorphous silicon was continuously formed with a thickness of about 30 to 80 nm on the gate oxide film 5b. The two-layer gate insulating film and the amorphous semiconductor thin film 7 were continuously formed without breaking the vacuum system of the film forming chamber. Here, when the plasma CVD method is used, annealing is performed in a nitrogen atmosphere at 400 ° C. to 450 ° C. for about 1 hour to 2 hours in order to desorb hydrogen in the film.

Here, Vth ion implantation is performed for the purpose of controlling Vth of the thin film transistor as necessary. In this example, B + was ion-implanted with a dose of about 1 × 10 ^{12 to} 6 × 10 ¹² / cm ² . Subsequently, laser light is irradiated to crystallize the amorphous semiconductor thin film 7. An excimer laser beam can be used as the laser light. So-called laser annealing is an effective means for crystallizing a semiconductor thin film at a process temperature of 600 ° C. or lower. In this embodiment, crystallization is performed by irradiating the amorphous semiconductor thin film 7 with laser light excited in a pulse shape and shaped into a rectangular shape or a belt shape. At this time, since the dehydrogenation process is performed in the previous step, even if the amorphous semiconductor thin film 7 is irradiated with a laser beam and rapidly heated, there is no possibility that the contained hydrogen bumps. In some cases, the semiconductor thin film may be crystallized by solid phase growth instead of laser crystallization. Even in this case, in order to obtain a polycrystalline semiconductor thin film with few crystal defects and excellent crystallinity, it is important to perform a dehydrogenation treatment in advance. Thereafter, the semiconductor thin film 7 is patterned in accordance with the element region of each thin film transistor.

As shown in (c), SiO ₂ is formed to a thickness of about 100 nm to 300 nm on the polycrystalline semiconductor thin film 7 crystallized in the previous step by, for example, plasma CVD. In this example, silane gas was decomposed to form SiO ₂ . This SiO ₂ is patterned into a predetermined shape and processed into a stopper film 11. In this case, the stopper film 11 is patterned so as to be aligned with the gate electrode 6 using a backside exposure technique. The portion of the polycrystalline semiconductor thin film 7 located immediately below the stopper film 11 is protected as a channel region Ch. Subsequently, impurities (for example, P + ions) are implanted into the semiconductor thin film 7 by ion implantation using the stopper film 11 as a mask to form an LDD region. The dose amount at this time is, for example, 4 × 10 ^{12 to} 5 × 10 ¹³ / cm ² . The acceleration voltage is, for example, 10 keV. Further, after patterning a photoresist so as to cover the stopper film 11 and the LDD regions on both sides thereof, impurities (for example, P + ions) are implanted at a high concentration using this as a mask to form the source region S and the drain region D. . For example, ion doping (ion shower) can be used for the impurity implantation. In this embodiment, impurities are implanted by electric field acceleration without mass separation. In this embodiment, impurities are implanted at a dose of about 1 × 10 ¹⁵ / cm ² using PH ₃ gas diluted with H ₂ . A source region S and a drain region D were formed. Although not shown, when a p-channel thin film transistor is formed, after covering the region of the n-channel thin film transistor with a photoresist, the impurity is switched from P + ion to B + ion and the dose amount is about 1 × 10 ¹⁵ / cm ^2. Ion doping may be used. For example, B ₂ H ₆ gas diluted with H ₂ is used. Here, impurities may be implanted using a mass separation type ion implantation apparatus. Thereafter, an activation process of impurities implanted into the semiconductor thin film 7 is performed. Activation may be any of furnace annealing, annealing using an energy beam such as a laser, and annealing using RTA.

Finally, as shown in (d), SiO ₂ is formed to a thickness of about 200 nm to form the interlayer insulating film 12. After the formation of the interlayer insulating film 12, SiN _x is formed to a thickness of about 200 to 400 nm by a plasma CVD method to form a passivation film (cap film) 13. At this stage, heat treatment at about 350 ° C. is performed for 1 hour in an atmosphere of nitrogen gas, forming gas, or vacuum to diffuse hydrogen atoms contained in the interlayer insulating film 12 into the semiconductor thin film 7. Thereafter, a contact hole is opened, and Mo, Al or the like is sputtered to a thickness of 200 to 400 nm, and then patterned into a predetermined shape to be processed into the wiring electrode 9. Further, after applying the planarizing layer 10 made of acrylic resin or the like with a thickness of about 1 μm, a contact hole is opened. A transparent conductive film made of ITO, IXO, or the like is sputtered on the planarizing layer 10 and then patterned into a predetermined shape to be processed into the electrode 2. When ITO is used, annealing is performed at 220 ° C. in N _{2 for} about 30 minutes.

  DESCRIPTION OF SYMBOLS 21 ... Vertical start pulse generation circuit, 22 ... Vertical transfer circuit, 30 ... Level shifter, 25 ... Vertical clock signal generation circuit, 31 ... Level shifter, 41 ... Horizontal transfer circuit

Claims (8)

A plurality of elements used for signal output;
Ri formed and a scanning circuit for sequentially selecting the control pulse device of the multiple,
Run査回path includes a transfer circuit for sequentially transferring a start pulse input to the first stage to the end stage,
A plurality of units a plurality of stages in units of transfer circuit for each single position of the clock signal have a booster circuit that boosts respectively,
Each of the booster circuits is a signal output device that performs a boosting operation in accordance with the transfer operation of the corresponding stage of the transfer circuit . A plurality of elements used for outputting signals arranged in a matrix;
A vertical scanning circuit for sequentially selecting along the columns along the horizontal direction of the multiple elements in a vertical direction,
The columns in the element selected by the vertical scanning circuit, Ri formed and a horizontal scanning circuit for outputting sequentially signals to elements along the horizontal direction,
At least one of the vertical scanning circuit or horizontal scanning circuit includes a transfer circuit for sequentially transferring a start pulse input to the first stage to the selection target element of the tail stage,
A plurality of units a plurality of stages in units of transfer circuit for each single position of the clock signal have a booster circuit that boosts respectively,
Each of the booster circuits is a signal output device that performs a boosting operation in accordance with the transfer operation of the corresponding stage of the transfer circuit . Each boost circuit, the corresponding on-off of the step-up operation by the pulse output from the stage signal output device according to claim 1 or claim 2 which is directly controlled transfer circuit. Each stage of the transfer circuit is performed transfer operation according to the corresponding clock signal supplied from the booster circuit outputs a control pulse,
Further control signal output device as claimed in claim 1 or claim 2 comprising a switch that controls the opening and closing of the respective signal line by sampling the clock signal according to control pulses. A plurality of detection units;
Ri formed and a scanning circuit for sequentially selecting the control pulse detection part of multiple,
Run査回path includes a transfer circuit for sequentially transferring a start pulse input to the first stage to the end stage,
A plurality of units a plurality of stages in units of transfer circuit for each single position of the clock signal have a booster circuit that boosts respectively,
Each of the boosting circuits is a signal input device that performs a boosting operation in accordance with the transfer operation of the corresponding stage of the transfer circuit . A plurality of detectors arranged in a matrix;
A vertical scanning circuit for sequentially selecting along the columns along the horizontal direction of the detection portion of the multiple vertically,
The columns in the detector selected by the vertical scanning circuit, Ri formed and a horizontal scanning circuit for performing acquisition of the signal from the sequential detection unit along the horizontal direction,
At least one of the vertical scanning circuit or horizontal scanning circuit includes a transfer circuit for sequentially transferring a start pulse input to the first stage in the detection of the selection of the tail stage,
A plurality of units a plurality of stages in units of transfer circuit for each single position of the clock signal have a booster circuit that boosts respectively,
Each of the boosting circuits is a signal input device that performs a boosting operation in accordance with the transfer operation of the corresponding stage of the transfer circuit . Each boost circuit, the signal input apparatus according to the corresponding claim 5 or claim 6 off the step-up operation is controlled directly by the pulse output from the stage of the transfer circuit. Each stage of the transfer circuit is performed transfer operation according to the corresponding clock signal supplied from the booster circuit outputs a control pulse,
Further control signal input device of claim 5 or claim 6 comprising a switch for opening and closing control of each signal line by sampling the clock signal according to control pulses.

Images