JP3297665B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for obtaining a crystalline semiconductor used for a thin film device such as a thin film insulated gate field effect transistor (thin film transistor or TFT).

[0002]

2. Description of the Related Art Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate field effect transistor (TFT) is manufactured by a plasma CVD method or a thermal CV method.
The amorphous silicon film formed by the method D was crystallized at a temperature of 600 ° C. or higher in an apparatus such as an electric furnace.

[0003]

However, such a conventional method has many problems. The biggest problem is that the crystalline silicon film obtained is polycrystalline, and it is difficult to obtain a good product because the grain boundaries are difficult to control, and its characteristics vary, and its reliability and yield are not so high. there were. That is, since the silicon crystal obtained by the conventional heat treatment is generated at random, it is almost impossible to control the crystal growth direction and the like. The present invention has been made in view of such problems, and has as its object to control crystal growth.

[0004]

SUMMARY OF THE INVENTION The present invention provides an amorphous state or a disordered crystalline state which can be said to be substantially an amorphous state (for example, a state in which a portion having good crystallinity and an amorphous portion are mixed). ), A gate electrode is formed on the silicon film, an impurity region is formed in the silicon film using the gate electrode as a mask, and nickel, iron,
A region containing at least one of cobalt and platinum is formed in close contact with at least a part of the impurity region, and is annealed to crystallize the silicon film starting from the nickel-containing region. ,
TF that controls crystal growth and, consequently, has high reliability and high yield
T is obtained. In particular, according to the present invention, the crystallization of the source and the drain proceeds simultaneously with the crystallization of the active layer (channel formation region), whereby the grain boundaries between the source, the drain and the active layer are substantially lost, and the excellent characteristics are obtained. Get.

With respect to the conventional crystallization of a silicon film, a method of solid-phase epitaxial growth using a crystalline island-like film as a nucleus and using this as a seed crystal (for example, see Japanese Patent Laid-Open No. 1-21).
4110). However, for example,
Even if crystal nuclei exist, it has been difficult to suppress crystal growth from other locations. That is, since the annealing temperature for crystal growth was a temperature suitable for generating crystal nuclei sufficiently, crystal growth started from an unexpected place.

The present inventor has proposed nickel (Ni), cobalt,
It has been found that iron and platinum are easily bonded to silicon, and these serve as nuclei for crystal growth. Particularly easily nickel silicide respect nickel (Formula NiSi _x, 0.4 ≦ _x
≦ 2.5) and the lattice constant of nickel silicide is close to that of silicon crystal. Then, they came up with a method of growing silicon crystals using nickel silicide as a nucleus. In practice, compared with the conventional crystallization temperature, 20 to
The crystal growth temperature could be lowered by 150 ° C. At this temperature, no crystal nuclei were generated in the pure silicon film, and thus crystal growth did not occur from an unexpected place. It is presumed that the crystal growth from the crystal nucleus is based on the same mechanism as the conventional one. At a temperature at which the crystal nucleus does not spontaneously generate (preferably 580 ° C. or lower), the higher the temperature, the faster the crystallization proceeds. Similar effects were observed with platinum (Pt), iron (Fe), and cobalt (Co).

According to the present invention, a film or the like containing the above-mentioned material such as nickel, iron, cobalt, platinum alone or a silicide thereof is brought into close contact with the silicon in the impurity region of the thin film transistor. To expand. An oxide is not preferable as a material containing the above-mentioned material. This is because the oxide is a stable compound,
This is because silicide serving as a crystal nucleus is not generated.

[0008] The crystalline silicon expanded from a specific location as described above has a structure close to a single crystal with good crystal continuity. The amorphous silicon film as a starting material for this crystallization showed better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film did not show a clear correlation with the hydrogen concentration in the amorphous silicon film as the starting material. The hydrogen concentration in the crystalline silicon according to the invention is typically 0.01
It was at least 5 atomic%.

In the present invention, heavy metal materials such as nickel, iron, cobalt and platinum are used, but these materials themselves are not preferable for silicon as a semiconductor material. Therefore, it is necessary to remove this, but as a result of the research by the present inventors, nickel is hydrogen chloride, various methane chlorides (such as CH ₃ Cl), and various ethane chlorides (C ₂ H ₃ Cl).
₃ ), and annealing at 400 to 600 ° C. in an atmosphere of various types of ethylene chloride (such as C ₂ HCl ₃ ) revealed that they could be sufficiently removed. The concentrations of nickel, iron, cobalt and platinum in the silicon film according to the present invention are as follows:
Typically, it was 0.005 atomic% or more and 1 atomic% or less. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0010]

[Example] [Example 1] Substrate (Corning 7059)
An underlying silicon oxide film 11 having a thickness of 2000 ° was formed on the substrate 10 by a plasma CVD method. Further, the amorphous silicon film is formed to a thickness of 200 to 3000３, preferably 50 to
0-1500 °, plasma CVD or reduced pressure CVD
It was produced by the method. 350 for amorphous silicon film
Hydrogen desorption was carried out by annealing at ４５０450 ° C. for 0.1 to 2 hours, and crystallization was easy when the hydrogen concentration in the film was 5 atomic% or less. This was patterned to form an island-shaped silicon region 12. Then, a silicon oxide film 13 having a thickness of 500 to 1500 ° functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method. When the plasma CVD method is adopted, the source gas is TEO
Preferred results were obtained with S (tetraethoxysilane) and oxygen. A tantalum film (thickness 5000 °) containing 1% of silicon was deposited by a sputtering method, and this was patterned to form a gate wiring / electrode 14. The material of the gate electrode may be titanium, silicon, chromium, or aluminum.

Next, the substrate was immersed in a 3% solution of tartaric acid in ethylene glycol, and platinum was used as a cathode and a tantalum wiring was used as an anode. The current was initially applied to increase the voltage at 2 V / min,
When the voltage reaches 0 V, the voltage is fixed, and the current is 10 μA.
/ M ² or less, the current was stopped. As a result, anodic oxide (tantalum oxide) 15
Was formed. Similarly, when titanium, aluminum, or silicon is used as the gate electrode, titanium oxide, aluminum oxide, or silicon oxide can be obtained as the anodic oxide.
(Fig. 1 (A))

Next, impurity doping was performed by a plasma doping method. As the doping gas, for example, phosphine (PH ₃ ) was used for the N-type, and diborane (B ₂ H ₆ ) was used for the P-type. The figure shows an N-type TFT.
The accelerating voltage is 80 keV for phosphine and 6 for diborane.
5 keV. Thus, the impurity regions 16A, 16B
Was formed. At this time, the impurity region and the gate electrode
As can be seen from the figure, it is in the offset state. Further, holes were formed in the silicon oxide film 13 on the impurity regions, and nickel silicide (or nickel) films 17A and 17B were formed so as to be in close contact with the semiconductor region 12 through the holes. Then, annealing was performed at 550 ° C. for 4 hours in a nitrogen atmosphere to crystallize the impurity region 16 and other semiconductor regions. (FIG. 1 (B))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 18 in the same manner as in the manufacture of a normal TFT, and contact holes are formed in the silicon oxide film to form wiring / electrodes 19A and 19B in source and drain regions. Was formed. Aluminum, titanium, titanium nitride, and a multilayer film thereof are suitable as the material of the wiring / electrode. Here, titanium nitride (thickness 1000 mm) and aluminum (thickness 5000)
Ii) The multilayer film was used. (Fig. 1 (C))

Through the above steps, a TFT (N-channel type in the figure) was manufactured. Field-effect mobility of the obtained TFT was 30 to 50 cm ² / Vs at 40~60cm ² / Vs, P-channel type N-channel type. Even when a voltage of 17 to 25 V was applied between the gate and the drain for 48 hours, the threshold voltage, the field-effect mobility, and the sub-threshold characteristics were hardly changed, and high reliability was obtained.
This is because, in this embodiment, the source and drain and the channel formation region (the semiconductor region below the gate electrode) are crystallized simultaneously, and the crystallization directions are the same.

Example 2 Substrate (Corning 705)
9) A base silicon oxide film 21 having a thickness of 2000 ° was formed on 20 by a plasma CVD method. Further, the amorphous silicon film is formed to a thickness of 200 to 3000 Å, preferably 5 to
The temperature was set to 00 to 1500 °, and the film was formed by a plasma CVD method or a low pressure CVD method. The amorphous silicon film was dehydrated by annealing at 350 to 450 ° C. for 0.1 to 2 hours, and it was easy to crystallize when the hydrogen concentration in the film was 5 atomic% or less. This was patterned to form an island-shaped silicon region 23. And
A silicon oxide film 24 having a thickness of 500 to 1500 す る functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method. In the case where the plasma CVD method is employed, preferable results were obtained when TEOS (tetraethoxysilane) and oxygen were used as the source gas. Then, a polycrystalline silicon film (thickness: 5000 Å) containing 1 to 5% of phosphorus is deposited by the LPCVD method, and this is patterned to form a gate wiring and
Electrodes 25A and 25B were formed. (Fig. 1 (A))

Thereafter, an impurity is diffused by an ion doping method to form an N-type impurity region 26A and a P-type impurity region 26B. At this time, for example, phosphorus is used as an N-type impurity (doping gas is phosphine PH ₃ ), and the entire surface is doped with an acceleration voltage of 60 to 110 kV, for example, 80 kV. covering the region, P-type impurity, for example, using boron (diborane B ₂ H ₆ doping gas), 40～80KV, for example may be doped at an acceleration voltage of 65 kV.

Further, holes are formed in the silicon oxide film 24 on the impurity regions, and nickel silicide (nickel can be used) films 27A and 27B having a thickness of 200 to 1000 Å, for example, 300 よ う so as to be in close contact with the impurity regions 26 through the holes. Was formed. Then, annealing was performed at 550 ° C. for 4 hours in a nitrogen atmosphere to crystallize the impurity region 26 and other semiconductor regions. In this case, the crystal growth proceeds from both ends of the island-shaped semiconductor region and ends around the middle thereof. Therefore, no grain boundary was formed in the channel forming region, and the adverse effect on the TFT characteristics was small. (Figure 2
(B)) Alternatively, as shown in FIG. 2C, a nickel silicide film 27C may be provided at the center of the island-shaped semiconductor region. In this case, crystallization proceeds from the center. (Fig. 2 (C))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 28 in the same manner as a normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 29A and 29B in the source and drain regions. , 29C. Aluminum, titanium, titanium nitride, and a multilayer film thereof are suitable as the material of the wiring / electrode. Here, a multilayer film of titanium nitride (thickness 1000 °) and aluminum (thickness 5000 °) was used. (FIG. 2 (D)) Through the above steps, a CMOS type TFT was manufactured. A shift register was manufactured using the CMOS circuit thus manufactured, and its operation characteristics were examined. Drain voltage 15
V, the maximum operating frequency is 11 MHz, and the drain voltage is 17
At V, the highest operating frequency was 18 MHz.

[0019]

According to the present invention, the direction of crystal growth, which has been difficult in the past, can be controlled, so that the reliability and yield of thin film transistors can be significantly improved. In addition, since the equipment, apparatus, and method for this are very common and excellent in mass productivity, the profits brought to the industry cannot be expected. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows a top view of the steps of an embodiment. (Step of manufacturing TFT)

FIG. 2 shows a cross-sectional view of a process of the embodiment. (Step of manufacturing TFT)

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate (Corning 7059) 11 ... Base oxide film (silicon oxide) 12 ... Island-shaped silicon region 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode (tantalum) 15. ..Anodic oxide (tantalum oxide) 16 ... impurity region (N type) 17 ... nickel silicide film 18 ... interlayer insulator (silicon oxide) 19 ... metal electrode (titanium nitride / aluminum multilayer film) )

Continuation of the front page (56) References JP-A-2-140915 (JP, A) JP-A-63-142807 (JP, A) JP-B-45-22173 (JP, B1) (58) Fields investigated (Int) .Cl. ⁷ , DB name) H01L 21/20 H01L 21/322 H01L 21/336 H01L 29/786 JICST file (JOIS)

Claims (5)

(57) [Claims] Forming an amorphous silicon film, patterning the amorphous silicon film to form an island-shaped silicon region, forming a gate insulating film on the island-shaped silicon region, Forming a gate electrode on the film, introducing an impurity into the island-shaped silicon region using the gate electrode as a mask to form two impurity regions, and contacting the impurity region with a film containing nickel. After forming the film containing nickel, the island-shaped silicon region is heated, and the island-shaped silicon region is crystal-grown from a position where the film is in contact, and the entire island-shaped silicon region is crystallized. Producing a semiconductor device, wherein the crystallized island-shaped silicon region is annealed in an atmosphere containing a chloride gas to remove nickel from the island-shaped silicon region. Law. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the film containing nickel is a nickel film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the film containing nickel is a nickel silicide film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the chloride is hydrogen chloride, methane chloride, ethane chloride, or ethylene chloride. 5. The method according to claim 1, wherein the annealing is performed by heating the crystallized island-shaped silicon region to 400 to 600 ° C. .