JP3288159B2 - Bus connection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a bus connection system, and
The present invention relates to a bus connection method used when an I / O bus connected to an O device and a memory bus connected to a memory are connected to each other to form a system.

[0002]

2. Description of the Related Art An example of this type of conventional bus connection system is shown in FIG.

In FIG. 5, a processor 6 includes a control line 11
And the completion of the access to the I / O device 7 from the bus control unit 4 'via the bus control unit 4', the next software processing is performed.

The bus control unit 4 'is provided with a bus timer 1 for the bus A'.
When an instruction to start access to the I / O device 7 is received from the processor 6 via the control line 11, activation of access start to the I / O device 7 to the bus A ′ 17 via the control line 12 is started. multiply.

[0005] The bus timer 18 for the bus A 'is
This is a down counter for monitoring the bus time-out, and a core start (not shown) of the bus control unit 4 'instructs a timer start / timer stop. “L ′” is set as the timeout time in the bus timer 18 for the bus A ′. Further, upon receiving the notification of the end of the access of the I / O device 7 or the bus timeout generated on the bus B9 from the bus A'17, the processor 6 notifies the processor 6 of the end of the access of the I / O device 7 or the bus timeout generated on the bus B9. I do. Further, when the bus timer 18 for the bus A ′ detects the bus timeout of the bus A ′ 17, the countdown is stopped and the process is sent to the processor 6.

As shown in FIG. 6, the bus A'17 has an AD (K) indicating an address, an AS (L) indicating an access start, an RDY (M) indicating an access end, and a TMO indicating a bus timeout. Each signal of (N) is carried.

When the bus A'17 receives the start of access start to the I / O device 7 from the bus control unit 4 'via the control line 12, the bus A'17 starts access start to the I / O device 7 to the bus connection unit 1'. multiply. Further, when receiving the end of access of the I / O device 7 from the bus connection unit 1 ', it notifies the bus control unit 4' of the end of access of the I / O device 7.

Next, the bus connection section 1 'includes a bus sequencer 3 and a bus B bus timer 2 as shown in FIG.

The bus sequence 3 receives the start of access start to the I / O device 7 from the bus A'17 via the control line 14, and the start of access start to the I / O device 7 to the bus B9 via the control line 15. multiply.

The bus timer 2 for the bus B is a down-counter for monitoring the bus time-out of the bus B9, and a timer start / stop is instructed by the bus sequencer 3. In the bus timer 2 for the bus B, “M” is set as the timeout time. The relationship between the timeout time “L ′” of the bus A ′ bus timer 18 and the timeout time “M” of the bus B bus timer 2 must be “L ′> M”.

The bus sequencer 3 receives the end of the access of the I / O device 7 from the bus B9 via the control line 15, and the end of the access of the I / O device 7 to the bus A'17 via the control line 14. Notice. Bus timer 2 for bus B
When the bus timeout of the bus B9 is detected, the timeout is notified to the bus sequencer 3 and the countdown is stopped. The bus sequencer 3 notifies the bus A'17 of the bus timeout and the bus B9.

The bus B9 has an AD (E) indicating an address and an AS indicating an access start as shown in FIG.
(F), RDY (G) indicating the end of access, and TMO (H) indicating bus timeout. Bus B
Reference numeral 9 denotes an I / O device 7 from the bus connection unit 1 via a control line 15.
When the activation of access start for the
To start access to the I / O device 7 via the. Further, when receiving the access end from the I / O device 7, it notifies the bus connection unit 1 of the access end of the I / O device 7.

The I / O device 7 receives the activation of the access start from the bus B9, performs the I / O processing, and notifies the bus B9 of the end of the access.

Next, based on FIG.
The operation of normal access to the / O device 7 will be described.

When the processor 6 performs read or write access to the I / O device 7, it instructs the bus control unit 4 'to start access. The bus control unit 4 'activates the access start to the bus A'17 in accordance with the access start instruction received from the processor 6. At the same time, a timer start is instructed to the bus timer 18 for the bus A '. The bus timer 18 for the bus A 'receives "L', L'-1, L'-2,.
・ ・ ”And start countdown.

On bus A'17, an address is sent to AD (K) by bus control unit 4 'and AS (L) is activated. Bus sequencer 3 is bus A'17
Receives an address on AD (K) and an active state on AS (L), and starts access start to bus B9. At the same time, a timer start is instructed to the bus B bus timer 2. The bus timer 2 for the bus B starts counting down to “M, M−1, M−2,...” In response to a timer start instruction.

On the bus B9, the bus sequencer 3
The address is sent to D (E), and AS (F) goes active. The I / O device 7 receives the AD from the bus B9.
The address on (E) and the active state on AS (F) are received. After performing the read or write process for the received address, the I / O device 7 notifies the end of the access.

On the bus B9, the I / O device 7
(G) becomes active.

The active state on RDY (G) is received from the bus B9, and the access completion is notified to the bus A'17.
At the same time, the bus sequencer 3 sets the bus timer 2 for bus B
Is instructed to stop the timer. The bus timer 2 for the bus B stops counting down in response to a timer stop instruction from the bus sequencer 3.

On the bus A'17, RDY (M) is activated by the bus sequencer 3 in the bus connection section 1 '. The bus control unit 4 transmits RDY (M) from the bus A'17.
Upon receiving the active state, the processor 6 notifies the processor 6 that the access has been completed. At the same time, the bus control unit 4 'instructs the bus A' bus timer 18 to stop the timer. The bus timer 18 for the bus A 'stops counting down in response to an instruction to stop the timer of the bus control unit 4'.

When the processor 6 receives the notification of the access end from the control line 11, it starts processing of the next software.

Next, based on FIG.
The operation of the bus timeout for the / O device 7 will be described.

The processor 6 instructs the bus control unit 4 'to start access to the I / O device 7 in the same manner as in normal access. In response to an access start instruction received from the bus control unit 4 'processor 6, access start is activated on the bus A'17. At the same time, the bus control unit 4 'instructs the bus A' bus timer 18 to start a timer. The bus timer 18 for the bus A 'is set to "L', L'-1, L'-" in response to a timer start instruction from the bus control unit 4 '.
2,... ".

On bus A'17, an address is sent to AD (K) by bus control unit 4 'and AS (L) is activated. Bus sequencer 3 is bus A'17
Receives the address on AD (K) and the active state on AK (L), and activates access start to bus B9. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 to start a timer. The bus timer 2 for the bus B starts counting down to “M, M−1, M−2,...” In response to a timer start instruction from the bus sequencer 3.

On the bus B9, the bus sequencer 3
The address is sent to D (E), and AS (F) goes active. I / O device 7 is connected to bus B9
The address on (E) and the active state on AS (F) are received. Here, it is assumed that the I / O device 7 cannot notify the bus B9 of the end of access to the received address due to a failure or failure. In this case, since there is a relationship of “L ′> M” between the timeout time of the bus timer 18 for the bus A ′ and the timeout time of the bus timer 2 for the bus B, the timer value of the bus timer 2 for the bus B becomes “0” first. .
When the value of the bus timer 2 for bus B becomes "0", the bus timer 2 for bus B notifies the bus sequencer 3 of a timeout and stops the countdown. The bus sequencer 3 notifies a timeout to the bus B9.

On the bus B9, the TMO (H) is activated by the bus sequencer 3 in the bus connection section 1 '. Further, the bus sequencer 3 notifies the bus A ′ 17 of the bus timeout by the timeout notification from the bus timer 2 for the bus B.

On the bus A'17, the bus sequencer 3 activates TMO (N). The bus control unit 4 'receives the active state on the TMO (N) from the bus A'17 and notifies the processor 6 of the bus timeout generated on the bus B9. At the same time, the timer is instructed to the bus timer 18 for the bus A 'to stop the timer.

The processor 6 receives the notification of the bus timeout generated on the bus B9 from the control line 11. The processor 6 starts processing of the next software in response to the received notification of the bus timeout.

[0029]

In the conventional bus connection method described above, the timeout time of the bus timer of the bus A must always be longer than the timeout time of the bus timer of the bus B. I / O that requires a time longer than the timeout time
A problem occurs that the device cannot be connected to the bus B. Further, when the bus B exists as an existing bus having a timeout time of the bus timer larger than the timeout time of the bus timer of the bus A, there is a problem that the bus A cannot be connected.

[0030]

In order to solve the above-mentioned problems, a first system of the present invention is a bus connection system in an information processing system in which a first bus and a second bus are connected. A processor that accesses an I / O device connected to the second bus via the first bus; and a first processor that receives an instruction to access the I / O device from the processor. Upon receiving a bus retry instruction from the first bus timer and a bus retry from the first bus to start a bus and monitor a bus timeout of the first bus, the first bus timer is started and the first bus timer is started. A bus control unit including a retry mechanism for restarting a bus, a second bus timer for monitoring a bus timeout of the second bus, and a retry for counting a bus retry time to the first bus When receiving an instruction to access the I / O device from the counter and the first bus, the second bus timer and the retry counter are started and the I / O device connected to the second bus is started. A bus sequencer including a bus sequencer for initiating access and generating a bus retry to the first bus when the time counted by the retry counter has elapsed. Further, in the first method of the present invention, when the first bus timer, the second bus timer, and the retry counter are instructed to start a timer, the first bus timer counts down from an initial value set and counts a time until it becomes 0. When the initial set values are L, M, and N, respectively, N <L <M
Has the relationship Further, in the first method of the present invention, when the bus sequencer receives a restart from the first bus, it performs a timer start of the retry counter, but the restart of the second bus and the second It is provided that the bus timer is not started.

[0031]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the processor 6 includes a control line 11
And instructs the bus control unit 4 to start access to the I / O device 7 via the I / O device 7.
The following software processing is performed by receiving the end of the access.

The bus control unit 4 includes a bus timer 5 for bus A and a retry mechanism 16. When receiving an instruction to start access to the I / O device 7 from the processor 6 via the control line 11, the bus control unit 4 controls the bus via the control line 12. A8 is started to start access to the I / O device 7. The control line 12
Via the bus A8 to notify the processor 6 of the end of access of the I / O device 7 or the bus timeout generated on the bus B9, and notify the processor 6 of the end of access of the I / O device 7 or the bus timeout generated on the bus B9.

The bus timer 5 for the bus A is a down counter for monitoring the bus time-out of the bus A8, and is a core unit (not shown) of the bus control unit 4 or a retry mechanism 16.
Indicates a timer start / timer stop.
The bus A bus timer 5 sets "L" as the timeout time.
Is set. The bus timer 5 for the bus A is connected to the bus A8.
When the bus timeout is detected, the countdown is stopped and the processor 6 is notified.

When the retry mechanism 16 is notified of a bus retry from the bus A8 to the bus A8 via the control line 12, the retry mechanism 16 meets the control line 12 and sends the I / O device 7 to the bus A8.
Starts access to again. At the same time, a timer start is again instructed to the bus A bus timer 5.

The bus A8 has AD (A) indicating an address and AS indicating an access start as shown in FIG.
(B), RDY (C) indicating end of access, RTY (J) indicating bus retry, and TMO indicating bus timeout.
Each signal of (D) is carried.

When the bus A8 receives a start of access to the I / O device 7 from the bus control unit 4 via the control line 12, the bus A8 accesses the bus control unit 1 via the control line 14 to access the I / O device 7. Initiation of the start and termination of access of the I / O device 7 from the bus connection unit 1 or bus B
When receiving the notification of the bus timeout occurring in step 9, the bus control unit 4 is notified of the end of the access of the I / O device 7 or the bus timeout occurring in the bus B9. When receiving a bus retry request from the bus sequencer 3, the bus controller 4 notifies the bus controller 4 of the bus retry.

The bus connection unit 1 includes a bus sequencer 3 and a bus B
Bus timer 2 and a retry counter 10.
The bus sequencer 3 receives the activation of the access start to the I / O device 7 from the bus A8, and activates the access start to the I / O device 7 to the bus B9 via the control line 15. The bus timer 2 for the bus B is a down counter for monitoring a bus time-out of the bus B9, and a timer start / stop is instructed by the bus sequencer 3. In the bus timer 2 for the bus B, “M” is set as the timeout time.

The retry counter 10 is a down counter for generating a bus retry for the bus A8, and a timer start / timer stop is instructed by the bus sequencer 3. In the retry counter 10, "N" is set as an initial value of the retry count (I) as shown in FIG. Timeout time "L" for bus A bus timer 5
There is a relation of “N <L <M” between the timeout time “M” of the bus timer 2 for the bus B and the initial value “N” of the retry count (I) of the retry counter 10.

When the bus sequencer 3 receives the access end of the I / O device 7 from the bus B9, it notifies the bus A8 of the end of access of the I / O device 7. Further, when the bus timer 2 for bus B detects a bus timeout of the bus B9, it notifies the bus sequencer 3 of the timeout and stops the countdown. The bus sequencer 3 notifies the bus timeout to the buses A8 and B9. When the retry counter 10 generates a bus retry for the bus A8, it notifies the bus sequencer 3 of the bus retry and stops the countdown. The bus sequencer 3 notifies the bus A8 of a bus retry.

The bus B9 has a waveform as shown in FIG.
AD (E) indicating address and AS indicating access start
(F), RDY (G) indicating the end of access, and TMO (H) indicating bus timeout. Bus B
9 receives the activation of the access start to the I / O device 7 from the bus connection unit 1, activates the access to the I / O device 7, and receives the end of the access from the I / O device 7. The unit 1 is notified of the end of access of the I / O device 7.

After receiving the activation of the access start from the bus B9, the I / O device 7 notifies the bus B9 of the end of the access.

Next, based on FIG.
The operation of normal access to the / O device 7 will be described.

When the processor 6 performs read or write access to the I / O device 7, the bus control unit 4
Is instructed to start access. The bus control unit 4 activates access start to the bus A8 according to the access start instruction received from the processor 6. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to start a timer. The bus timer 5 for the bus A receives “L, L−1, L−2,.
・ ・ ”And start countdown. On the bus A8, an address is sent to AD (A) by the bus control unit 4, and AS (B) is activated.

The bus sequencer 3 receives the AD from the bus A8.
The address on (A) and the active state on AS (B) are received, and the start of access to the bus B9 is started. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 and the retry counter 10 to start a timer.
The bus timer 2 for the bus B starts counting down to “M, M−1, M−2,...” In response to a timer start instruction from the bus sequencer 3. Also, the retry counter 10
Indicates that the retry count (I) is "N, N-1, N-2, ..." in response to a timer start instruction of the bus sequencer 3.
And count down.

On the bus B9, an address is sent to AD (E) by the bus sequencer 3 in the bus connection unit 1, and AS (F) is activated. The I / O device 7 receives an address on AD (E) and an active state on AS (F) from the bus B9. After performing the read or write processing for the received address, the I / O device 7 notifies the bus B9 of the end of the access.

On the bus B9, the I / O device 7
(G) becomes active. The bus sequencer 3 receives the active state on RDY (G) from the bus B9 and notifies the bus A8 of the end of access. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 and the retry counter 10 to stop the timer. The bus timer 2 for the bus B stops counting down in response to a timer stop instruction from the bus sequencer 3. The retry counter 10 stops counting down in response to a timer stop instruction from the bus sequencer 3.

On the bus A8, the bus sequencer 3
DY (C) becomes active. The bus control unit 4 receives the active state on RDY (C) from the bus A8 and notifies the processor 6 of the end of access. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to stop the timer. The bus A bus timer 5 stops counting down in response to a timer stop instruction from the bus control unit 4. When the processor 6 receives the access end notification from the control line 11, the processor 6 starts processing of the next software.

Next, based on FIG.
The operation of the bus timeout for the / O device 7 will be described.

The processor 6 instructs the bus control unit 4 to start accessing the I / O device 7 in the same manner as in normal access. The bus control unit 4 starts the access start to the bus A8 according to the access start instruction received from the processor 6. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to start a timer. The bus timer 5 for the bus A starts counting down to “L, L−1, L−2,...” In response to a timer start instruction from the bus control unit 4. On the bus A8, the bus control unit 4
The address is sent to D (A), and AS (B) is activated.

The bus sequencer 3 performs AD conversion from the bus A8.
The address on (A) and the active state on AS (B) are received, and the start of access to the bus B9 is started. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 and the retry counter 10 to start a timer.
The bus timer 2 for the bus B starts counting down to “M, M−1, M−2,...” In response to a timer start instruction from the bus sequencer 3. Also, the retry counter 10
Indicates that the retry count (I) is "N, N-1, N-2, ..." in response to a timer start instruction of the bus sequencer 3.
And count down. On the bus B9, an address is sent to AD (E) by the bus sequencer 3 in the bus connection unit 1, and AS (F) is activated.

The I / O device 7 receives the address on AD (E) and the active state on AS (F) from the bus B9.
Here, it is assumed that the I / O device 7 cannot notify the bus B9 of the end of access to the received address due to a failure or failure. At this time, the bus timer 5 for bus A, the bus timer 2 for bus B, and the retry counter 10
Since there is a relationship of “N <L <M” between the timer values of “1” and “2”, the retry count (I) of the retry counter 10 becomes “0” first. When the retry count (I) becomes "0", the retry counter 10
The bus retry is notified and the countdown is stopped. The bus sequencer 3 notifies the bus A8 of a bus retry.

On the bus A8, the bus sequencer 3
TY (J) becomes active. Retry mechanism 16
Receives the active state on RTY (J) from the bus A8, instructs the bus A bus timer 5 to stop the timer, and stops the timer once. At the same time, access start to the I / O device 7 to the bus A8 is started again. At the same time, the retry mechanism 16 again instructs the bus timer 5 for bus A to start the timer. The bus timer 5 for the bus A restarts counting down to “L, L−1, L−2,...” In response to a timer start instruction from the retry mechanism 16. On the bus A8, the address is sent to the AD (A) again by the bus control unit 4, and the AS
(B) becomes active.

The bus sequencer 3 again outputs the AD from the bus A8.
The address on (A) and the active state on AS (B) are received. In this case, the bus sequencer 3 does not start access to the bus B9. The bus sequencer 3 does not instruct the bus timer 2 for the bus B to start the timer. However, a timer start instruction is issued to the retry counter 10, whereby the retry counter 1
0 sets the retry count (I) to "N, N-1, N-
2, ... ”. The retry mechanism 16 of the bus control unit 4 and the bus sequencer 3 of the bus connection unit 1 repeat these operations related to the bus retry until the end of the access from the bus B9 or the bus timer 2 for the bus B detects a bus timeout.

Next, when the countdown of the bus timer 2 for the bus B progresses and the count value becomes "0", the bus timer 2 for the bus B notifies the bus sequencer 3 of a timeout and stops the countdown. Bus sequencer 3
Notifies the bus B9 of the timeout. At the same time, the bus sequencer 3 instructs the retry counter 10 to stop the timer. The retry counter 10 stops counting down in response to a timer stop instruction from the bus sequencer 3.

On the bus B9, the bus sequencer 3
MO (H) becomes active. Further, the bus sequencer 3 notifies the bus A8 of the timeout by the notification of the timeout from the bus timer 2 for the bus B. Bus A8
In the above, TMO (D) is activated by the bus sequencer 3.

The bus control unit 4 transmits the TMO (D) from the bus A8.
The active state is received, and the processor 6 is notified of the bus timeout generated on the bus B9. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to stop the timer. The bus A bus timer 5 stops counting down in response to a timer stop instruction from the bus control unit 4. When the processor 6 receives the notification of the bus timeout generated on the bus B9, the processor 6 starts the processing of the next software based on the received notification of the bus timeout.

Next, based on FIG.
I / O device 7 in normal access to I / O device 7
The operation in the case where the notification of the access end is delayed will be described.

The processor 6 instructs the bus control unit 4 to start accessing the I / O device 7 in the same manner as in normal access. The bus control unit 4 activates access start to the bus A8 according to the access start instruction received from the processor 6. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to start a timer. Bus A
The bus timer 5 starts counting down to "L, L-1, L-2,..." In response to a timer start instruction from the bus control unit 4. AD on the bus A8 by the bus control unit 4.
The address is sent to (A), and AS (B) becomes active.

The bus sequencer 3 outputs the signal from the bus A8 to the AD
The address on (A) and the active state on AS (B) are received, and the start of access to the bus B9 is started. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 and the retry counter 10 to start a timer.
The bus timer 2 for the bus B starts counting down to “M, M−1, M−2,...” In response to a timer start instruction from the bus sequencer 3. Also, the retry counter 10
Indicates that the retry count (I) is "N, N-1, N-2, ..." in response to a timer start instruction of the bus sequencer 3.
And count down.

On the bus B9, the bus sequencer 3
The address is sent to D (E), and AS (F) goes active. The I / O device 7 receives the AD from the bus B9.
The address on (E) and the active state on AS (F) are received. Here, it is assumed that the I / O device 7 takes a long time to read or write the received address, so that the notification of the access end is delayed.

At this time, since the timer value of the bus timer 5 for the bus A, the bus timer 2 for the bus B, and the timer value of the retry counter 10 have a relationship of “N <L <M”, the retry count (I) of the retry counter 10 Becomes "0" first. The retry counter 10 has a retry count (I)
Becomes "0", the bus sequencer 3 is notified of the bus retry, and the countdown is stopped. The bus sequencer 3 notifies the bus A8 of a bus retry.

On the bus A8, the bus sequencer 3
TY (J) becomes active. Retry mechanism 16
Receives the active state on RTY (J) from the bus A8, instructs the bus A bus timer 5 to stop the timer, and stops the timer once. At the same time, the access to the bus A8 for the I / O device 7 is started again. At the same time, the retry mechanism 16 again instructs the bus timer 5 for bus A to start the timer. Bus A
The bus timer 5 restarts counting down to "L, L-1, L-2,..." In response to a timer start instruction from the retry mechanism 16. On the bus A8, the address is sent to the AD (A) again by the bus control unit 4, and
S (B) becomes active.

The bus sequencer 3 again outputs the AD signal from the bus A8.
Receive the address on (A) and the active state on AS (B). In this case, the bus sequencer 3 does not start access to the bus B9. Bus sequencer 3
Does not instruct the bus timer 2 for the bus B to start the timer. However, the timer start is instructed to the retry counter 10, whereby the retry counter 10 again sets the retry count (I) to "N, N-1, N".
−2, ... ”. The retry mechanism 16 of the bus control unit 4 and the bus sequencer 3 of the bus connection unit 1 repeat these operations related to the bus retry until the access from the bus B9 ends or the bus timer 2 for the bus B detects a bus timeout.

Next, when the read or write processing, which has been taking a long time in the I / O device 7, is completed, the bus B9
Notifies the end of access. On the bus B9, the RDY (G) is activated by the I / O device 7. The bus sequencer 3 in the bus connection unit 1 connects the bus B9 to the RDY
(G) Receives the active state and notifies the bus A8 of the end of access. At the same time, the bus sequencer 3 instructs the bus B bus timer 2 and the retry counter 10 to stop the timer. The bus timer 2 for the bus B stops counting down in response to a timer stop instruction from the bus sequencer 3. The retry count 10 stops counting down in response to a timer stop instruction from the bus sequencer 3.

On the bus A8, RDY (C) is activated by the bus sequencer 3 in the bus connection unit 1. The bus control unit 4 receives the active state on RDY (C) from the bus A8 and notifies the processor 6 of the end of access. At the same time, the bus control unit 4 instructs the bus A bus timer 5 to stop the timer. The bus A bus timer 5 stops counting down in response to a timer stop instruction from the bus control unit 4. The processor 6 receives the access end notification from the control line 11. The processor 6 starts processing of the next software in response to the received access completion.

[0067]

As described above, in the bus connection system according to the present invention, since the retry counter and the retry mechanism are provided, the I / O device or the existing extension bus can be used without being limited by the timeout time of the bus timer of the bus A. The effect is that you can connect.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 shows a bus A at the time of normal access in the embodiment of FIG.
FIG. 4 is a timing chart showing the operation of a bus B.

FIG. 3 shows a bus A at the time of timeout in the embodiment of FIG. 1;
FIG. 4 is a timing chart showing the operation of a bus B.

FIG. 4 is a timing chart showing the operation of the bus A and the bus B at the time of an access end delay in the embodiment of FIG. 1;

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is a timing chart showing operations of buses A 'and B during normal access in the conventional example of FIG.

7 is a timing chart showing the operation of the bus A 'and the bus B at the time of timeout in the conventional example of FIG.

[Explanation of symbols]

 1, 1 'bus connection unit 2 bus B bus timer 3 bus sequencer 4, 4' bus control unit 5 bus A bus timer 6 processor 7 I / O device 8 bus A 9 bus B 10 retry counter 11 to 15 control line 16 retry Mechanism 17 Bus A '18 Bus timer for bus A'.

Claims (3)

(57) [Claims] 1. A bus connection method in an information processing system in which a first bus and a second bus are connected, wherein access to an I / O device connected to the second bus is performed by the first bus. A first bus timer that activates the first bus and monitors a bus timeout of the first bus when an instruction to access the I / O device is received from the processor; When a bus retry instruction is received from the first bus, a bus control unit including a retry mechanism that starts the timer of the first bus timer and restarts the first bus, A second bus timer for monitoring a bus timeout, a retry counter for measuring a bus retry time to the first bus, and the I bus from the first bus;
Upon receiving an instruction to access the I / O device, the second bus timer and the retry counter are started, access is started to the I / O device connected to the second bus, and the time counted by the retry counter is counted. A bus connection unit that includes a bus sequencer that causes a bus retry to occur on the first bus as a result of the following. 2. The first bus timer, the second bus timer, and the retry counter count time from a set initial value to 0 when a timer start is instructed. 2. The bus connection method according to claim 1, wherein when the values are set to L, M, and N, respectively, the relationship of N <L <M is satisfied. 3. When the bus sequencer receives a restart from the first bus, the bus sequencer starts the timer of the retry counter. However, the restart of the second bus and the timer of the second bus timer start. 2. The bus connection method according to claim 1, wherein the connection is not performed.