JPH10247167A - Information processor having i/o bus monitoring function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To notify the I/O bus information when an error occurs by monitoring an error signal, storing the contents of a buffer in an error report register against the occurrence of the error and notifying this error. SOLUTION: A bus monitor 6 which monitors an I/O bus 5 is connected to the bus 5, and the monitor 6 is connected to an error notifying device 15 via an error report register 13 having an error flag 19. An error signal monitoring part 7 of the monitor 6 monitors the error signal that shows whether the bus 5 has an error or not. When the error of the bus 5 is detected at the part 7, an error monitor device 14 of the monitor 6 stores the contents of buffers 8 to 10 recording the bus information in the register 13 and then turns on the flag 19. Then the device 15 of an information processor having an I/O bus monitoring function notifies the error when the flag 19 of the register 13 is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having an I / O bus monitoring function having a function of monitoring an I / O bus, and more particularly to monitoring an I / O bus bus information and causing an error. The present invention relates to a technique which is effective when applied to an information processing apparatus having an I / O bus monitoring function for notifying bus information of an I / O bus when an error occurs.

[0002]

2. Description of the Related Art In a conventional computer system, I / O
An error signal indicating whether an error has occurred in the O bus is added. When an I / O bus has a fault, the CPU recognizes the error signal and performs error processing.

In this computer system, when a bus access such as a data transfer is performed to an I / O device connected to the I / O bus via the I / O bus, a response to the data transfer cannot be obtained. , A retry is attempted to attempt data transfer again.

When such data transfer retries frequently occur, a failure may occur in the I / O bus or the I / O device on the I / O bus. No retry of data transfer was detected as a failure.

In a conventional computer system, if an error occurs during execution of a specific process via the I / O bus and a response from the I / O bus cannot be obtained, the
Although the O bus is in a hang-up state, when the I / O bus hangs up, the computer system is stopped as it is, so that the cause of the hang-up error could not be identified.

In this case, the conventional computer system does not detect which I / O device detects the error and what the master of the bus access in which the error occurred is.

A bus failure processing circuit which detects an error during data transfer on a bus, re-executes data transfer, and can continue processing without causing a system down even if an intermittent failure occurs in a control bus. Is described in JP-A-8-22423.

A bus fault monitoring system which has a function of specifying a bus master when a data parity error occurs during data transfer on the bus and which facilitates the specification of a cause of a fault occurring in the bus system is particularly described. Kaihei 8
No. -6868.

[0009]

By the way, in the conventional computer system, when a failure occurs in the I / O bus, an error signal is recognized and error processing is performed. This does not mean that it is difficult to find the cause of the error that has occurred.

In the conventional computer system, when a retry of data transfer occurs due to a failure of the I / O bus or an I / O device on the I / O bus, the retry of the occurred data transfer is regarded as a failure. There is a problem that it is difficult to detect.

Further, in the above-mentioned conventional computer system, when the I / O bus hangs up, the computer system stops as it is, so that there is a problem that it is difficult to find out the cause of the error.

An object of the present invention is to provide a technique capable of notifying bus information of an I / O bus at the time of occurrence of an error and solving the above problem.

[0013]

SUMMARY OF THE INVENTION The present invention relates to an information processing apparatus having an I / O bus monitoring function for monitoring an I / O bus, wherein an address of a bus cycle which is bus information during operation of the I / O bus. The values of the signal, the request signal and the control signal are recorded in a buffer, and the error signal is monitored by an error signal monitoring unit. It is to report.

In the information processing apparatus with an I / O bus monitoring function, a HOST bus to which a CPU is connected and an I / O bus to which an I / O device is connected are connected via an I / O bus bridge. When an I / O device is accessed via the / O bus, bus information such as an address signal, a request signal, and a control signal for each bus access is stored in a buffer.

The error signal monitoring section monitors an error signal indicating whether or not an error has occurred in the I / O bus, and upon detecting the occurrence of the error, an error monitoring device which reports that an error has occurred in the I / O bus. Inform

When the error monitoring device is notified by the error signal monitoring section that an error has occurred in the I / O bus, the error monitoring device stores the contents of the buffer recording the bus information in an error report register and stores an error flag in the error report register. Turn on.

The error reporting device periodically checks the content of the error flag, and when the content of the error flag is on, turns on an LED, sounds a buzzer, or performs other monitoring on the network. Perform error notification to the system.

The contents of the error report register stored by the error monitoring device can be used when investigating the cause of an error that has occurred in the I / O bus. Help identify.

As described above, since the bus information of the I / O bus at the time of occurrence of the error is recorded, it is possible to notify the bus information which helps to identify the cause of the error at the time of occurrence of the error.

A bus data transfer monitoring unit for monitoring the number of data transfer retries on the I / O bus is provided. The bus data transfer monitoring unit counts the number of data transfer retries during a specific time, and the count value exceeds a specific value. In this case, it may be determined that there is a problem with the access, and the recorded bus information such as the address signal, the request signal, and the control signal of the bus access may be reported.

As described above, since the number of retries of data transfer during a specific time is counted, a state in which retries of data transfer on the I / O bus occur frequently is detected.
It is possible to prevent the performance of the system from deteriorating and to detect a failure of the I / O device.

Further, a bus cycle time-out monitoring unit for monitoring a time-out of a bus access on the I / O bus is provided, and when a bus access on the I / O bus is hung up, this is detected and forced. The bus access may be terminated, and an error signal indicating the occurrence of an error may be output to notify the recorded bus information such as an address signal, a request signal, and a control signal of the bus access.

As described above, since the hang-up of the bus access on the I / O bus is detected and the bus access is forcibly terminated, the hang-up state is released even if the I / O bus hangs up. After that, the cause of the hang-up error can be identified.

As described above, according to the information processing apparatus having the I / O bus monitoring function, the bus information when the bus access is performed on the I / O bus is recorded.
It is possible to notify the bus information of the / O bus.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an information processing apparatus with an I / O bus monitoring function according to the present invention, the bus information of an I / O bus is monitored.
An information processing apparatus with an I / O bus monitoring function of one embodiment for notifying O bus bus information will be described.

FIG. 1 is a diagram showing a schematic configuration of an information processing apparatus with an I / O bus monitoring function according to this embodiment. In FIG. 1, 1-1 and 1-2 are CPUs, 2 is a HOST bus,
3 is an I / O bus bridge, 4-1 to 4-3 are I / O devices, 5 is an I / O bus, 6 is a bus monitor, 7 is an error signal monitoring unit, 8 is a bus cycle address buffer, and 9 is a bus. A cycle control signal buffer, 10 a bus cycle master buffer, 11 a bus data transfer monitor, 12 a bus cycle timeout monitor, 13 an error report register, 14 an error monitor, 15 an error reporter, 16 a timer, 17 is a counter, 18 is a timer, and 19 is an error flag.

As shown in FIG. 1, in the information processing apparatus having an I / O bus monitoring function, a bus monitor 6 for monitoring the I / O bus 5 is connected to the I / O bus 5.
Is an error report register 13 having an error flag 19
Is connected to the error reporting device 15 via the.

The bus monitor 6 of the information processing apparatus having an I / O bus monitoring function includes an error signal monitoring unit 7, a bus cycle address buffer 8, a bus cycle control signal buffer 9, a bus cycle master buffer 10, a bus cycle It has a data transfer monitoring unit 11, a bus cycle timeout monitoring unit 12, and an error monitoring device 14.

The error signal monitoring unit 7 of the bus monitor 6
A processing unit that monitors an error signal indicating whether an error has occurred in the I / O bus 5 and notifies the error monitor device 14 that an error has occurred in the I / O bus 5.

The bus cycle address buffer 8, the bus cycle control signal buffer 9, and the bus cycle master buffer 10 of the bus monitor 6 respectively provide bus cycle information, which is bus information, when a bus access is performed on the I / O bus 5. This buffer records the values of the address signal, control signal, and request signal indicating the bus master.

The bus data transfer monitoring section 1 of the bus monitor 6
1 monitors the number of retries of data transfer on the I / O bus 5, counts the number of retries of data transfer during a specific time, and when this count value exceeds a specific value,
A processing unit that determines that there is a problem with the access and outputs an error signal indicating that an error has occurred.

The bus cycle timeout monitoring unit 12 of the bus monitor 6 monitors the timeout of the bus access on the I / O bus 5 and, when the bus access on the I / O bus 5 is hung up, And forcibly terminates the bus access and outputs an error signal indicating the occurrence of an error.

The error monitor device 14 of the bus monitor 6
Is a processing unit that, when the occurrence of an error is detected by the error signal monitoring unit 7, stores the contents of each buffer recording the bus information in the error report register 13 and turns on the error flag 19.

The error reporting device 15 of the information processing device with an I / O bus monitoring function is a device that reports an error when the error flag 19 of the error reporting register 13 is turned on.

When a bus access occurs on the I / O bus 5, the bus monitor 6 of the information processing apparatus having an I / O bus monitoring function, when a bus access occurs, a bus cycle address buffer 8, a bus cycle control signal buffer 9, and a bus cycle master buffer 10 , And the values of the bus cycle address signal, the bus cycle control signal, and the request signal indicating the bus cycle master of the bus cycle are stored in each buffer.

Here, the value of the bus cycle address signal and the value of the request signal indicating the bus cycle master are the same during one bus access, but the value of the bus cycle control signal changes with time. Then, the state of the bus cycle control signal is stored in the bus cycle control signal buffer 9.

FIG. 2 is a flowchart showing a processing procedure for processing when an error occurs on the I / O bus 5 of the information processing apparatus with an I / O bus monitoring function according to the present embodiment.

As shown in FIG. 2, in the processing when an error occurs on the I / O bus 5 of the information processing apparatus having the I / O bus monitoring function, the occurrence of the error is caused on the I / O bus 5 by the error signal. This shows the processing procedure when a report is made.

The error signal monitoring unit 7 of the information processing apparatus having the I / O bus monitoring function performs the I / O
The error signal on the bus 5 is monitored, and when it is confirmed that an error signal indicating that an error has occurred on the I / O bus 5 has been output, the process proceeds to step 202 to perform error processing.

The error monitor device 14 executes step 20
2 from the error signal monitoring unit 7 to the I / O bus 5
When notified that an error has occurred above, step 2
In the process 03, the contents of the bus cycle address buffer 8, the bus cycle control signal buffer 9 and the bus cycle master buffer 10 are logged to the error report register 13 and the error flag 19 is turned on.

The error notification device 15 periodically checks the contents of the error report register 13 and determines in step 2
When it is detected that the error flag 19 is turned on in the process of 04, an LED is turned on, a buzzer sounds, or an error notification is sent to another monitoring system or the like on the network.

The contents of the error report register 13 stored by the error monitor device 14 can be used when investigating the cause of an error that has occurred in the I / O bus 5, which means that a bus error has occurred. Helps identify the factors.

As described above, in the information processing apparatus with the I / O bus monitoring function of the present embodiment, the address signal, the control signal, and the bus master of the bus cycle, which are the bus information of the I / O bus 5 at the time of occurrence of the error. Since the value of the request signal is recorded, it is possible to notify the user or other information processing devices connected to the network of bus information that helps identify the cause of the error when an error occurs.

FIG. 3 is a flowchart showing a processing procedure of a process when a bus retry is detected in the information processing apparatus with an I / O bus monitoring function according to the present embodiment.

As shown in FIG. 3, in the processing at the time of detecting the bus retry of the information processing apparatus having the I / O bus monitoring function,
This shows a processing procedure when a bus access retry occurs many times on the bus 5 and it is determined that there is an abnormality in the system.

In the information processing apparatus having the I / O bus monitoring function, first, in step 301, the timer 16 and the counter 17 in the bus data transfer monitoring unit 11 inform the timer 16 and the counter 17 of the maximum time and the maximum number of times of detecting the bus access retry. set.

The bus data transfer monitoring unit 11 performs step 3
In the process 02, the bus cycle control signal buffer 9 is monitored, and if there is no control signal pattern indicating data transfer despite the activation of the access, the counter 17
Is decreased by “1”.

Then, the bus data transfer monitoring unit 11 checks the value of the counter 17 in the process of step 303, and if the result of decreasing the value of the counter 17 is "0", proceeds to the process of step 305, where the I / O is performed. An error signal indicating that an error has occurred on the bus 5 is output.

When an error signal indicating that an error has occurred on the I / O bus 5 is output, in step 306, the error monitor device 14 controls the bus cycle address buffer 8, the bus cycle control signal buffer 9, The contents of the bus cycle master buffer 10 are logged in the error report register 13 and the error flag 19 is turned on.

The error reporting device 15 which periodically checks the error report register 13 detects that the error flag 19 is on, and reports the occurrence of an error.

The bus data transfer monitoring unit 11 checks the value of the counter 17 in the processing of step 303,
If the result of decreasing the value of the counter 17 is not “0”, the value of the timer 16 is checked in the processing of step 304.

The bus data transfer monitoring section 11 has a timer 1
If the value of the timer 16 is "0", the process returns to the step 301 of setting the respective maximum values to the timer 16 and the counter 17 in the bus data transfer monitoring unit 11, and if the value of the timer 16 is "1" or more, If present, bus data transfer monitoring unit 1
The process returns to the process of step 302 in which monitoring is performed according to 1.

As described above, in the information processing apparatus with the I / O bus monitoring function of the present embodiment, the number of retries of data transfer during a specific time is counted, so that the data transfer on the I / O bus 5 is performed. , It is possible to prevent the system performance from deteriorating and to detect a failure of the I / O devices 4-1 to 4-3.

FIG. 4 is a flowchart showing the processing procedure of the information processing apparatus with an I / O bus monitoring function of the present embodiment when a bus hangs up.

As shown in FIG. 4, in the processing at the time of the bus hang-up of the information processing apparatus having the I / O bus monitoring function, the I / O bus
This shows a processing procedure when a hang-up occurs on the bus 5.

FIG. 5 is a diagram showing an example of a timing chart when the bus hangs up in the information processing apparatus with an I / O bus monitoring function of the present embodiment.

As shown in FIG. 5, in the timing chart when the bus hangs up in the information processing apparatus with the I / O bus monitoring function, when the hang-up occurs on the I / O bus 5, Signal status of each signal line and timer 18
Represents the change in the value of.

As shown in FIG. 4, in the information processing apparatus with an I / O bus monitoring function, the timer 18 in the bus cycle timeout monitoring unit 12 is first set to a timer maximum value N in step 401.

The bus cycle timeout monitoring unit 12
In the process of step 402, it is checked whether or not the bus access has been started on the I / O bus 5, and as shown in FIG. 5, the initiator of the bus access outputs a Start # signal for one clock, and outputs the signal to the I / O bus 5. If the access has been started, the process proceeds to step 403 to start decrementing the timer 18.

The bus cycle timeout monitoring unit 12
In the process of step 404, it is checked whether or not the started bus access has been completed. If the bus access has been completed, the process returns to step 401. If the bus access has not been completed, the process returns to step 401. Proceed to 405.

The bus cycle timeout monitoring unit 12
In the process of step 405, the value of the timer 18 is checked. If the value of the timer 18 is not equal to or less than "0", the process returns to step 403. If the value of the timer 18 is equal to or less than "0", the process proceeds to step 406. , I / O bus 5
An error signal is output above and the bus access is terminated.

As shown in FIG. 5, when the initiator of the bus access outputs a Start # signal for one clock and starts the bus access, it is determined that the target of the bus access is the target of the bus access. The detected signal T_exist # is output for one clock.

As described above, the target is T_exist #
Is output for one clock, the initiator of the bus access then outputs I_ready # indicating that the bus access is ready.

However, when the value of the timer 18 is decremented to “0” and the T_ready # indicating that the target is ready for access is not output, the bus cycle time-out monitoring unit 12 sets the I / O bus 5 An error signal (Er) indicating that an error has occurred
rr #), and outputs a T_ready # signal to terminate the bus access.

When an error signal indicating that an error has occurred on the I / O bus 5 is output, in step 407, the error monitor device 14 controls the bus cycle address buffer 8, the bus cycle control signal buffer 9, The contents of the bus cycle master buffer 10 are logged in the error report register 13 and the error flag 19 is turned on.

The error reporting device 15 which regularly checks the error report register 13 detects that the error flag 19 is on, and reports the occurrence of an error.

In the information processing apparatus with the I / O bus monitoring function, this prevents the I / O bus 5 from hanging up, and informs the CPU 1-1 that an error has occurred on the I / O bus 5. And 1-2.

As described above, the information processing apparatus with the I / O bus monitoring function of the present embodiment detects the hang-up of the bus access on the I / O bus 5 and forcibly terminates the bus access. Even if the / O bus 5 hangs up, it is possible to specify the cause of the hang-up error after releasing the hang-up state.

As described above, according to the information processing apparatus with the I / O bus monitoring function of the present embodiment, since the bus information when the bus access is performed on the I / O bus is recorded, an error occurs. It is possible to notify the bus information of the I / O bus at the time.

Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention. It is.

[0071]

According to the present invention, since the bus information when the bus access is performed on the I / O bus is recorded, it is possible to notify the bus information of the I / O bus when an error occurs. is there.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an information processing apparatus with an I / O bus monitoring function according to an embodiment;

FIG. 2 is a flowchart illustrating a processing procedure when an error occurs on an I / O bus of the information processing apparatus with an I / O bus monitoring function according to the embodiment;

FIG. 3 is a flowchart illustrating a processing procedure of processing when a bus retry is detected in the information processing apparatus with an I / O bus monitoring function according to the embodiment;

FIG. 4 is a flowchart illustrating a processing procedure when a bus hangs up in the information processing apparatus with an I / O bus monitoring function according to the embodiment;

FIG. 5 is a diagram illustrating an example of a timing chart when a bus hangs up in the information processing apparatus with an I / O bus monitoring function according to the embodiment;

[Explanation of symbols]

1-1 and 1-2 CPU, 2 HOST bus, 3 I
/ O bus bridge, 4-1 to 4-3 ... I / O device,
5 I / O bus, 6 bus monitor, 7 error signal monitor, 8 bus cycle address buffer, 9 bus cycle control signal buffer, 10 bus cycle master buffer, 11 bus data transfer monitor, 12 ... Bus cycle timeout monitoring unit, 13: Error report register, 14: Error monitoring device, 15: Error reporting device, 16: Timer, 17: Counter, 18: Timer, 19: Error flag.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tetsuji Tsukihito 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Prefecture Inside Hitachi Asahi Electronics Co., Ltd.

Claims (1)

[Claims] 1. An information processing apparatus having an I / O bus monitoring function for monitoring an error occurring in an I / O bus, wherein an address signal and a control signal of a bus cycle which are bus information during operation of the I / O bus. A buffer for recording a value of a request signal indicating a bus master, an error signal monitoring unit for monitoring an error signal indicating whether an error has occurred in the I / O bus, and the occurrence of an error detected by the error signal monitoring unit. An error monitor device that stores the contents of the buffer recording the bus information in an error report register when the error flag is turned on, and an error notification device that reports an error when the error flag is turned on. An information processing apparatus with an I / O bus monitoring function, comprising: