JP3286822B2 - N multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an N-multiplier circuit, and more particularly to an N-multiplier circuit used for digital signal transmission.

[0002]

2. Description of the Related Art A conventional N-multiplier circuit will be described with reference to the drawings. FIG. 5 shows a conventional doubler circuit, that is, N = 2.
FIG. 4 is a block diagram showing a configuration in the case of FIG. In the figure, the conventional doubler circuit converts a fundamental clock signal of f0 Hz to f0 Hz.
M-bit digital data 200 sampled at s (fs> 2 × f0) Hz is converted to 0 ^M- order held 2 ^M
DA conversion circuit (D / A) 2 for converting a value into an analog signal
1; a low-pass filter (LPF) 22 for extracting a fundamental wave from the zero-order held analog signal 210;
A full-wave rectifier circuit 23 that performs full-wave rectification of the extracted fundamental wave (sine wave) 220 of f0 Hz in an analog manner, and a doubled wave (2 × f0) is obtained from the full-wave rectified analog signal 230.
Hz) 240 band-pass filter (BP
F) 24.

The sampling clock 211 for determining the sampling frequency fs in the DA converter 21 is used.
Is input to a clock terminal CLK of the same circuit, and the digital data 200 is sampled at a sampling interval by the clock 211. M in the figure
SB is the most significant bit, and LSB is the least significant bit.

The operation of the conventional doubler circuit having such a configuration will be described with reference to FIG. In the figure, DA
The digital data 200 input to the conversion circuit 21 is
It is a digital data of a sine wave. In the DA converter 21, the input digital data 200
Is sampled at an interval of fsHz, and is converted to an analog signal 210 that is held in the zero order. The zero-order held analog signal 210 has a waveform in which a harmonic is superimposed on a sine wave as shown in the figure.

The analog signal 210 is applied to the low-pass filter 2
2, the harmonics are removed, and the fundamental wave 2 of f0 Hz
20 are extracted. This fundamental wave 220 is converted to a full-wave rectifier circuit 2
3, when the full-wave rectification is performed in an analog manner, a waveform like an analog signal 230 is obtained.
4, only the doubled wave 240 is extracted. As described above, the doubling process can be realized.

[0006]

In the above-mentioned conventional N-multiplier circuit (N = 2), since the full-wave rectifier circuit and the band-pass filter are constituted by analog circuits, the circuit scale is large and the integration is not easy. It has the disadvantage of hindering. Further, since the fundamental wave is extracted using the band-pass filter, there is a disadvantage that tuning adjustment is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide an N-multiplier circuit which can be easily integrated into an LSI or the like and does not require tuning adjustment. .

[0008]

According to the first aspect of the present invention, digitized sine wave data is set to a half cycle with respect to the cycle of the sine wave data. Conversion means for converting the data into amplitude data representing the distance from the median value; and D for converting the result of the conversion into analog data.
A doubling circuit characterized by having A conversion means and a low-pass filter for removing higher harmonic components of the converted analog data waveform can be obtained. According to the second aspect of the present invention, in the N-multiplier circuit for multiplying the frequency of the digitized sine wave data by N (N is an integer of 2 or more), the sine wave data is subjected to the cycle of the sine wave data. Conversion means for converting the sine wave data into amplitude data representing a distance from the center value of the sine wave data, a DA conversion means for converting the conversion result into analog data, and analog data after the conversion. A low-pass filter for removing harmonic components of the waveform of
It is possible to obtain an N-multiplier circuit which is a memory in which the amplitude data is stored in advance in correspondence with the sine wave data, and wherein an address of the memory access is the sine wave data.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an N-multiplier circuit according to the present invention. As in FIG. 5, an example of the configuration in the case of a 2-multiplier circuit (N = 2) is shown. In the figure, a doubler circuit according to one embodiment of the present invention has a frequency of f0 Hz.
Bit digital data 100 obtained by sampling the fundamental wave clock signal at fs (fs> 2 × f0) Hz.
Is a distance from a median value (a value of 2 ^M / 2) in a code string of 2 ^M values, that is, digital data 110 representing amplitude.
Code conversion circuit (CONV) 1 for converting into a digital signal having a fundamental frequency of 2 × f0 Hz.
1, a DA conversion circuit (D / A) 12 for converting the code-converted digital signal into a zero-order held analog signal 120, and a second harmonic (2 × f0) from the zero-order held analog signal 120. Hz fundamental wave) 130
And a low-pass filter (LPF) 13 that extracts

The sampling clock 121 for determining the sampling frequency fs in the DA converter circuit 12
Is input to a clock terminal CLK of the same circuit, and the digital data 100 is sampled at a sampling interval by the clock 121. M in the figure
SB is the most significant bit, and LSB is the least significant bit.

The operation of the doubler circuit according to the present embodiment having the above configuration will be described with reference to FIGS.

FIG. 2 is a conceptual diagram showing a code conversion operation of the code conversion circuit (CONV) 11. In the figure, 8
The case where an offset binary code of (M = 8) bits is input is shown. This offset binary code is obtained by converting a sine wave into digital data. The code string of 2 ^M values of this input code has the minimum value “00”.
000000 ”to the maximum value“ 11111111 ”, of which the median is“ 10000000 ”
(1/2 + 1 of the maximum value) and "01111111" (1 / 2-1 of the maximum value).

The code conversion in the code conversion circuit 11 converts the median value into "00000000", and converts the median value into an amplitude display indicating a distance from the median value (the value is incremented each time the median value is separated). That is, the minimum value “00000000” and the maximum value “11111” before the conversion.
111 "and the maximum value (large amplitude)" 1111111 "
To 1 ".

2 of the present embodiment including the above code conversion operation
The output of each section of the multiplier circuit is shown in FIG. As shown in the figure, in this embodiment, a zero-order held analog signal 120 output from the DA converter circuit 11 is shown. The analog signal 120 is input to the low-pass filter 13, where the superimposed harmonic component is cut off, and only the second harmonic 130 (2 × f0 Hz fundamental) is extracted. The sampling frequency fs in the DA conversion circuit 12 may satisfy the condition of fs> 2 × f0, but preferably fs = f in order to reduce waveform distortion.
0 / 0.3 is good.

In this embodiment, since the offset binary code is input, the code conversion circuit 11
Can be configured, for example, as shown in FIG. That is, using 9 (M + 1) exclusive OR gates,
The other bits are inverted with the inverted value of the most significant bit (MSB). According to such a configuration, the processing can be performed at high speed because it can be configured only with the gate. Thereby, for example, it can be used for a feedback circuit of a known PLL circuit.

When the processing speed is not considered, R
The code conversion circuit 11 can also be configured using OM (Read Only Memory). That is,
The code shown in FIG. 2 is stored in the ROM in advance, and the fundamental clock signal of f0 Hz is converted to fs (fs> 2 ×
f0) M-bit digital data sampled at Hz is used as the address. As a result, a doubled wave can be output as in FIG. In addition, RO
When M is used, it is possible to output more than 2 times, that is, 3 times wave or 4 times wave. In this case, the code data for obtaining the third and fourth harmonics may be stored in the ROM in advance.

[0018]

As described above, according to the present invention, there is provided a code for converting digitized sine wave data into amplitude data having a period shorter than the period of the sine wave and centered on the median value in accordance with the multiplication ratio. By providing the conversion means, there is an effect that the entire circuit can be digitized, the circuit scale is small, and the integration is easy. Also, by using a low-pass filter instead of a band-pass filter, there is an effect that tuning adjustment is unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an N-multiplier circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a code conversion example in a code conversion circuit in FIG. 1;

FIG. 3 is a waveform chart showing output waveforms of respective parts of the N-multiplier circuit of FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a code conversion circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional N-multiplier circuit.

FIG. 6 is a waveform chart showing output waveforms of various parts of the N-multiplier circuit of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Code conversion circuit 12, 21 DA conversion circuit 13, 22 Low-pass filter 23 Full-wave rectifier circuit 24 Band-pass filter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03B 19/00 H03B 28/00 H03K 5/00-5/26

Claims (2)

(57) [Claims] 1. The method according to claim 1 , wherein the digitized sine wave data is
Conversion means for converting the amplitude data representing the distance from the center value of the sine wave data and a half period relative to the period of the sine wave data, D for converting the conversion result into analog data
A doubling circuit comprising: A conversion means; and a low-pass filter for removing a harmonic component of the converted analog data waveform. 2. The frequency of digitized sine wave data.
In an N multiplier circuit for multiplying a number by N (N is an integer of 2 or more)
The sine wave data is set to be 1 to the cycle of the sine wave data.
/ N period and the distance from the median of the sine wave data
Conversion means for converting the data into amplitude data,
DA conversion means for converting to analog data, and
Low-pass to remove harmonic components of analog data waveform
A filter, and the conversion means converts the amplitude data to the sine wave data.
This is a memory that is stored in advance and
The address of the process is the sine wave data.
N multiplier.