JP3285346B2 - Game system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cartridge mounted on an information processing apparatus for switching an access method to a cartridge according to the type of the mounted cartridge.

[0002]

2. Description of the Related Art A conventional information processing system will be described using a game system as an example with reference to FIGS. 21, 22 and 23. FIG. First, as shown in FIG. 21, the conventional information processing system CGB is roughly divided into program sources 10
0 and the game machine 200. Program source 100
Is configured to store information such as a program necessary for executing the image display game in the game machine 200 and to be detachably connected to the game machine 200.

[0005] The program source 100 includes a ROM 101, and is configured as a cartridge including a RAM 102, a clock 104, and a memory bank controller 105 as necessary. The ROM 101 is constituted by a nonvolatile memory such as a ROM, a flash memory, and an EE-PROM, and stores a game program in a fixed manner.
Further, the ROM 101 stores dot data of an image representing an image of a game character or the like, and, if necessary, a program for exchanging data with another game machine (not shown) or another conventional image. A program for ensuring compatibility with a program recorded in a program source (not shown) of the display game device is stored.
In the following, the program source 100 will be referred to as a cartridge. FIG. 23 shows the appearance of the cartridge 100.

[0004] The RAM 102 is composed of a writable and readable memory typified by a RAM, and includes an area for storing temporary data related to the progress of the game.

[0005] The memory bank controller 105 has a ROM 10
When the memory space of one is larger than the memory space that can be handled by the CPU of the game machine 200, the memory space of the ROM 101 is divided into a plurality of banks, and given to the ROM 101 as an upper address based on bank data given by the CPU. In addition, the RAM 102 is similarly accessed. The ROM 101, the RAM 102, and the memory bank controller 105 are connected to the game machine 2 via the connector 103.
00 is detachably connected.

The game machine 200 mainly includes an operation key unit 20.
2. Central processing unit (CPU) 203, connector 20
4, RAM 205, display controller 206, liquid crystal display 20
7, an interface 208, and a connector 209. The CPU 203 has a RAM as a working memory for temporarily storing data for processing a game.
205 and a display controller 206 are connected. A liquid crystal display (LCD) 207 is connected to the display controller 206. Further, the CPU 203 includes an interface 20
8, the connector 209 is connected. Connector 20
9 is connected to a connector 209 of another game machine 200 via a cable when exchanging game data with an owner (player) of another game machine 200. Note that C
The PU 203 is connected to the cartridge 100 via the connector 204.

FIG. 22 shows the external structure of the information processing system CGB. The information processing system CGB includes the game machine 20
0 on the connector 204 (FIG. 21) provided on the back side.
Connector 103 of cartridge 100 storing memory
(FIG. 21). Game console 20
The operation key unit 202 is mounted below the surface (flat surface) of the housing 201, and the liquid crystal display 207 is mounted above the operation key unit 202. And inside the housing 201,
A circuit board on which the circuit components shown in FIG. 21 are mounted is housed.

The operation keys 202 include a direction switch 202a for instructing the movement direction of a character which can be moved by a cursor or a player, an operation switch 202b for instructing the movement of the character including movement, and a start switch 20.
2c, and a select switch 202d.

In this information processing system CGB,
As the CPU 203, an 8-bit CPU is used. Therefore, the ROM 101, the RAM 102, the memory bank controller 105, and the connector 103 are also configured with an 8-bit data width. Further, in the information processing system CGB in the 8-bit specification, the driving voltage of the ROM 101 and the RAM 102 is 5V. The data width means a signal width including all data signals, address signals, and control signals exchanged between a central processing unit such as a CPU and a memory.

The information processing system C configured as described above
In GB as well, it is necessary to improve the performance of CPUs in accordance with technical innovations of components represented by CPUs and the like and increasing demands of users for processing capabilities. However, as a result of technological innovation, the processing bits of the current CPU are different from those in the information processing system CGB. For example, the CPU performs 32-bit processing, and accordingly, it is necessary to use a memory system having a 32-bit specification. Under such circumstances, the connectors 103 and 204
It is also desirable to adopt a 32-bit specification. In addition, the higher performance of the CPU, besides the increase in the number of processing bits,
In some cases, the memory space that can be handled is increased (the number of bits of the address signal is increased). For example, information processing system CG
In B, the number of bits of the address signal of the CPU 203 is 16 bits.
Then, for example, there is a case where 24 bits are used. At this time, it is necessary to use a memory system corresponding to this. It is desirable to adopt a connector corresponding to this.

In a data processing system using a cartridge, an integrated circuit (IC) whose power consumption is reduced due to the advance of semiconductor technology in a newly released model.
In general, the drive voltage of a semiconductor memory such as a ROM and a RAM built in a CPU and a cartridge may be different between a lower model and a higher model.
For example, while the drive voltage of the memory system in the information processing system CGB is 5 V, it is set to 3.3 V in the new information processing system. In such a case, if a cartridge for a model with a low drive voltage is used by mounting it on a model with a high drive voltage, an excessive voltage may be applied to the semiconductor memory in the cartridge and the semiconductor memory may be destroyed.

[0012]

However, the conventional information processing system CGB has acquired many users for many years and has accumulated cartridges 100 storing various kinds of programs. Therefore, as described above, the bus transfer mode between the CPU and the memory and the connector are set to, for example, 32
If the voltage supplied to the memory system is unified to 3.3 V and the voltage supplied to the memory system is unified to 3.3 V, the cartridge 100 which is a great amount of software resources accumulated for the conventional information processing system CGB can be replaced with a new information processing apparatus. I can't take advantage of it.

As a technique for ensuring the compatibility of such cartridges, a technique disclosed in Japanese Patent Application Laid-Open No. 11-333144 is known. This technology uses a monochrome display cartridge for color display information processing when the number of processing bits of the CPU and the number of bits of the address signal are the same and the display screen of the information processing device is changed from a monochrome display screen to a color display. It can be used for equipment. In this case, it is assumed that the number of connection terminals for connecting the game cartridge to the information processing apparatus, the number of processing bits of the CPU, and the number of bits of the address signal are common between the lower model and the higher model.

On the other hand, optical recording media (CD-ROM, D
In a game machine using VD), the type of medium is CD-
There is also known a stationary video game machine that ensures compatibility between different ROMs and DVDs.

However, Japanese Patent Application Laid-Open No. H11-3331 discloses
The technology disclosed in Japanese Patent No. 44 cannot be used when the number of processing bits of the CPU and / or the number of bits of the address signal are different between the lower model and the higher model, and the compatibility of the game cartridge in such a case cannot be used. Could not be secured.

On the other hand, optical recording media (CD-ROM, D
In the video game machine using VD), compatibility is ensured because the program data read from the medium is temporarily transferred to a large-capacity RAM in the video game machine and stored for use. Not applicable to the machine.

The information processing apparatus of the present invention uses an 8-bit CPU for the conventional information processing system CGB and a new information processing apparatus for maintaining the compatibility of the program (cartridge) with the conventional information processing system CGB. And a 32-bit CPU. When a cartridge for the information processing system CGB is inserted, it operates with an 8-bit CPU system, and when a new game cartridge dedicated for an information processing device is inserted, it operates with a 32-bit CPU system.

Further, the information processing apparatus of the present invention is configured to connect a cartridge for the information processing system CGB and a cartridge dedicated to a new information processing apparatus to one (common) connector (bus) (information). This is an 8-bit specification connector adapted to the processing system CGB).
It goes without saying that the use of a common connector has advantages such as reduction in manufacturing cost, prevention of confusion of the user, and reduction in size.

Here, a plurality of types of memories having different numbers of bits of data signals must be connectable to one connector. Specifically, it is necessary to transfer an 8-bit data signal and a 32-bit data signal via an 8-bit specification connector. Further, when the CPU of the new information processing device increases the memory space that can be handled as compared with the CPU of the information processing system CGB, the number of bits of the address signal increases, and the data width to be transferred further increases. As described above, it is necessary to appropriately switch the bus transfer mode in accordance with a combination in which the CPU and the external bus have different data widths. Further, a new cartridge dedicated to an information processing device needs to have a mechanism corresponding to the above-described difference in data width, that is, a bus transfer mode capable of transferring 32-bit data via an 8-bit connector. .

In general, for bus control, a separate bus which is divided into an address bus and a data bus, and a multi-bus which uses a common bus in a time-division manner with an address and data (or an upper address and a lower address) are used. There is a plex bus, and these two types of bus specifications are selected according to the specifications of the processor or the memory. Here, a technique capable of switching between a bus system of a separate system and a system of a multiplex system is disclosed in Japanese Patent Application Laid-Open No. Hei 5-204820 (hereinafter referred to as "prior art 1") and Japanese Patent Publication No.
No. 42263 (hereinafter referred to as “prior art 2”). According to these conventional techniques, one processor accesses both a separate type memory (hereinafter, referred to as “first memory”) and a multiplex type memory (hereinafter, referred to as “second memory”). It becomes possible.

However, in the case of the prior art 1 and the prior art 2, the output is made to the first memory (or
Since the number of bits of the data signal input from the first memory and the number of bits of the data signal output to the second memory (or input from the second memory) are the same, It cannot be applied to a plurality of types of memories having different bit numbers of signals.

In the case of the prior arts 1 and 2, the central processing unit determines which of the first and second memories is to be accessed based on the address space. For this reason, the present invention is applicable only when the first and second memories are simultaneously and fixedly connected to the central processing unit, and selectively and exchanges one of a plurality of types of memories (eg, game cartridges). Not applicable when possible connector connection.

Whether the stored memory and program are dedicated to a new information processing device or an information processing system CGB
Nothing has been proposed regarding a memory stored in a cartridge provided with a function for identifying the use of the cartridge. Furthermore, no technique has been proposed in which the CPU has a plurality of operation modes and switches the operation mode according to the cartridge.

Therefore, the present invention provides an information processing apparatus system capable of executing a new or old cartridge by identifying a new or old cartridge and switching an access method to the cartridge according to the cartridge. For the purpose, of this information processing system,
In particular, it is an object of the present invention to provide a cartridge mounted on an information processing apparatus.

A mechanism corresponding to a multiplex bus transfer mode capable of transferring data via a connector having a relatively small data width to an information processing device for processing data having a relatively large data width is provided. An object of the present invention is to provide a cartridge including the same.

Further, when the drive voltage of the cartridge is different between the old and new cartridges, it is another object of the present invention to provide an information processing system capable of executing the old and new cartridges by switching the drive voltage supplied to the cartridge. In particular, an object of the present invention is to provide a cartridge to be mounted on an information processing apparatus.

[0027]

Means for Solving the Problems and Effects of the Invention In order to achieve the above object, the present invention has the following features. The first invention is the first game already released.
A first cartridge for the game machine and the first game machine.
A second game machine having interchangeability and a second game machine for the second game machine;
A game system composed of cartridges
The first cartridge has a first data width.
1 connector, and a first semiconductor having the first data width
A body memory, wherein the second cartridge is provided with the first data.
Connector having a data width, and the first data width
A second semiconductor memory having a larger second data width;
The second game machine includes the first cartridge and the first cartridge.
An insertion recess into which the second cartridge can be inserted,
A third core having the first data width, provided inside the unit.
Connector, near the side end of the insertion recess and the third connector
The first cartridge is provided near the
The housing of the first cartridge when inserted into the recess
Alternative selector pushed down by the tip of the
Switch and the selector switch is pushed down
Is a mode equivalent to the central processing means of the first game machine.
Start up, and with the selector switch not pressed down
Is a central processing to be started in a mode dedicated to the second game machine.
Means, and state in which the selector switch is pushed down
Now, for the semiconductor memory connected to the connector,
Access under normal bus control, and the selector switch
When the connector is not pushed down, the half connected to the connector
Multiplex control access to conductor memory
Bus control means, wherein the second cartridge is
At least the left and right to avoid contact with the selector switch
Notch formed at the tip in the insertion direction on either side
Unit, and between the game machine and the second semiconductor memory
That control time-division control of address and data exchange
Plex bus conversion means is further provided.
You.

A second invention is an invention dependent on the first invention.
Wherein the first semiconductor memory stores the first game
It stores the program for the central processing means of the machine.
And the second semiconductor memory is dedicated to the second game machine.
The program for the mode is stored.

A third invention is an invention dependent on the first invention.
Wherein the first semiconductor memory is driven by a first voltage
Wherein the second semiconductor memory is driven by a second voltage.
Wherein the second game machine is connected to the selector switch.
When the switch is pushed down, it is connected to the connector.
Supplying the first voltage to the semiconductor memory,
If the connector switch is not pushed down,
The second voltage is supplied to the semiconductor memory connected to the
It is characterized by further comprising a voltage supply means for supplying.

A fourth invention is an invention according to the first invention, wherein a first cartridge for a first game machine already released and a second game compatible with the first game machine are provided. And a second cartridge for the second game machine, wherein the first cartridge has a first connector having the first data width and a first connector having the first data width. Equipped with semiconductor memory,
The second cartridge has a first data width.
2 connector, and a second semiconductor memory having a second data width larger than the first data width, wherein the second game machine has an insertion recess in which the first cartridge and the second cartridge can be inserted, A third connector having the first data width provided inside the concave portion, provided near the side end of the insertion concave portion and near the third connector, the third connector is provided when the first cartridge is inserted into the insertion concave portion; An alternative selector switch pushed down by the front end portion of the housing of the first cartridge, and in a state where the selector switch is not pushed down, the second
In the state where the selector switch is depressed in the mode dedicated to the game machine, the central processing
In a state in which the central processing unit is started in a mode equivalent to a stage and the selector switch is not pressed down, the semiconductor memory connected to the connector is accessed by multiplex control, and in a state where the selector switch is pressed down, A bus control means for accessing the semiconductor memory connected to the connector by a normal bus control, wherein the second cartridge does not come into contact with the selector switch; A multiplex bus conversion means for multiplexing and using a notch formed in a portion and a partial terminal between the game machine and the second semiconductor memory at a first timing and a second timing; It is characterized by.

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where an information processing apparatus according to an embodiment of the present invention is applied to a game machine (or a game system constituted by the game machine) will be described with reference to FIGS. I do. Note that FIGS. 1 and 2
1 is an external view for explaining the principle of an embodiment of the game system of the present invention. FIG. 3 is a perspective view showing an aspect in which the second cartridge and the first cartridge are used for a second game machine which is a feature of the game system of the present invention.

In FIG. 1 and FIG. 3A, the game system includes a first game machine 10 such as two types of portable game machines using cartridges 20 and / or 40 as information storage media for game programs and the like. A second game machine 30 is included. The first game machine 10 corresponds to the game machine 200 in FIG. 21 described above, and the first cartridge 20 is a program source 100 in FIG.
Is equivalent to Further, a first game machine cartridge (hereinafter simply referred to as “cartridge” or “game cartridge”) detachably used in the first game machine 10.
20 and a second game cartridge 40 detachably used in the second game machine 30. Note that the first game machine 10 has a low-performance CPU (for example, a C equivalent to an 8-bit circuit unit 361 in FIG. 5 described later).
PU), and is a lower model (old type) having a low processing capacity. On the other hand, the second game machine 30 has a high performance CPU (for example, a 16-bit or 32-bit 16
CPU with more than bits; uses a 32-bit circuit unit 362 in FIG. further,
The second game machine 30 includes a CPU (8-bit circuit unit 361 in FIG. 5 described later) equivalent to the CPU of the first game machine 10 for compatibility.

The housing 21 of the first cartridge 20
Is a rectangular shape (or substantially square) having a vertical length of a1 and a horizontal length of b1, and its thickness is selected as c1. On the left and right side surfaces of one main surface of the first cartridge 20, inclined surfaces 211 for preventing reverse insertion of the front and back sides are formed. The first cartridge 20 includes a CPU of the first game machine 10 or a CPU of the first game machine 10 included in the second game machine 30 in the housing 21.
RO that stores a game program to be executed by a CPU (8-bit circuit unit 361 described later) equivalent to
A circuit board (not shown, details will be described later) on which a semiconductor memory such as M22 is mounted is built in. Note that R
The number of bits of the data signal of the OM 22 is 8 bits, the number of bits of the address signal is 16, and the driving voltage is 5V. An opening 212 is formed on one side surface of the first cartridge 20, and a plurality of connection terminals (not shown, formed on one side of the circuit board from the opening 212).
The details will be described later). Further, an edge connector (not shown) is constituted by the plurality of connection terminals formed on the circuit board.

The first game machine 10 includes a housing 11 having a liquid crystal display 12 formed near an upper region of one main surface (the surface shown in FIG. 1A) and a lower region. It has a movement direction instruction switch 13a and an operation instruction switch 13b. A cartridge insertion recess (hereinafter, referred to as “insertion recess”) for mounting the first cartridge 20 is provided near an upper region of the other main surface (the back surface illustrated in FIG. 1A) of the first game machine 10. ) Is formed. The insertion recess 14 is provided with the outer dimensions (length × width × thickness = a1 × b) of the first cartridge 20 so that the first cartridge 20 can be stored or mounted.
1 × c1).
The length in the vertical direction may be shorter than a1). Also,
Inside the insertion recess 14, a connector (not shown) for electrically connecting the first cartridge 20 to various electronic components (to be described in detail later) such as a CPU in the first game machine 10 is mounted. Is done. Therefore, when the first cartridge 20 is mounted in the insertion recess 14, the first cartridge 20 is completely fitted in the insertion recess 14,
Connector of first game machine 10 and first cartridge 2
The plurality of connection terminals of the circuit board 0 are electrically connected and used. At this time, the first game machine 10 supplies a first drive voltage (for example, 5V) to the first cartridge 20.

On the other hand, the housing 41 of the second cartridge 40 has a length a2 (a2 <a1) shorter than that of the first cartridge 20 and a horizontal plane b1 having the same width as the first cartridge 20. And the thickness thereof is selected to be the same c1 as that of the first cartridge 20. In this manner, by making the lateral length and thickness of the second cartridge 40 the same as those of the first cartridge 20, both cartridges can be inserted into the cartridge insertion recess 34 of the second game machine 30. . It goes without saying that the horizontal length direction and the thickness direction of the cartridges 20 and 40 are determined in accordance with the gist of the present invention. Further, inclined surfaces 411 are formed on the left and right side surfaces of one main surface of the housing 41, similarly to the first cartridge 20. Also, the second cartridge 40
In order to distinguish the first cartridge 20 from the case where the first cartridge 20 is mounted, a cutout portion 412 as an example of the detected portion is formed at least at one of the left and right side surfaces in the insertion direction. The notch 412 may be provided on both left and right side portions for the reason described above. Furthermore, the second
Cartridge 40 has a vertically upper side (upper side)
A protrusion 413 is formed on at least one of the left and right sides (both sides if necessary) of the right side to serve as a stopper during insertion. Therefore, the width b of the upper side of the second cartridge 40
2 is selected to be slightly larger than the lower width b1 (= the width of the first cartridge 20). The second cartridge 40 has a ROM (FIG. 6 described later) storing a game program to be executed by a 32-bit CPU (32-bit circuit unit 362 described later) of the second game machine 30.
Reference numeral 42; hereinafter, in the case of members shown in other drawings, reference numerals are shown in parentheses), a semiconductor memory such as a RAM (43) for storing backup data, and various integrations such as a multi-access control unit (44). A circuit board (45) on which a circuit (IC) is mounted is built in. ROM4
2, the number of bits of the data signal is 16 bits, the number of bits of the address signal is 24 bits, and the driving voltage is 3.
3V. The number of bits of the data signal of the RAM 43 is 8 bits, the number of bits of the address signal is 16 bits, and the driving voltage is 3.3V. An opening 414 is formed in a lower side surface portion of the second cartridge 40, and a plurality of connection terminals (or contacts; contacts; FIG. 9) formed on the side of the circuit board (45) from the opening 414.
46) is exposed. The edge connector (4) is provided by the plurality of connection terminals (46) formed on the circuit board (45).
7) is configured.

The second game machine 30 includes a housing 31 having a liquid crystal display 32 formed near a central area of one main surface thereof (the surface shown in FIG. 1B). A movement direction instruction switch 33a and an operation instruction switch 33b are provided in an empty area outside of. The other main surface of the second game machine 30 (FIG. 1)
An insertion recess 34 for mounting the second cartridge 40 is formed in the vicinity of the upper region of the back surface illustrated in FIG. The insertion recess 34 is provided in the second cartridge 30 so that the second cartridge 30 can be stored or mounted.
(Length x width x thickness = a2 x b1 x c1) (the length in the vertical direction may be shorter than a2). Further, a connector (37) for electrically connecting the second cartridge 40 to various electronic components such as a CPU in the second game machine 30 is mounted inside the insertion recess 34. Therefore, when the second cartridge 40 is mounted in the insertion recess 34, the second cartridge 40 is used in a state where the second cartridge 40 is completely fitted in the insertion recess 34. At this time, the second game machine 3
0 supplies the second drive voltage (for example, 3.3 V) to the second cartridge 40.

Next, referring to FIGS. 2 and 3B,
The first game machine 10 and the second game machine 30 have separate second cartridges 40 and first cartridges 20 respectively.
The case where is attached will be described.

As shown in FIG. 2A, when the second cartridge 40 is mounted on the first game machine 10,
The vertical length a2 of the cartridge 40 of the first game machine 10
The length is shorter than the vertical length a1 required to connect to the connector inside the housing, and the protrusion 413 is caught on the upper side of the housing 11 next to the insertion recess 14, so that the second cartridge 4
The 0 connection terminal (46) does not reach the connector of the first game machine 10 and is not properly connected. That is, the second cartridge 40 is mounted with the connection terminal (46) portion separated from the connector in the first game machine 10. Therefore, the power supply voltage of the first game machine 10 is not supplied to the connection terminal (46) of the second cartridge 40, that is, the various IC components including the semiconductor memory built in the second cartridge 40, And the like can be effectively prevented from being destroyed by overvoltage.

On the other hand, as shown in FIGS. 2B and 3B, the first cartridge 40 is
Is attached, the vertical length a of the first cartridge 20
1 is longer than the vertical length a2 of the insertion concave portion 34 of the second game machine 30 (a2 <a1), so that the first cartridge 20
Is connected to the connector (3) in the second game machine 30.
7) and are electrically connected. At this time, since the vertical length a2 <a1, the first cartridge 20 is set in the second game in a state where the portion a1-a2 (difference) in the vertical length direction of the first cartridge 20 is exposed from the insertion recess 34. It is to be mounted on the machine 30 and used. At this time, the second game machine 30 applies a second drive voltage (eg, 3.3
A first drive voltage (5 V) is supplied to the first cartridge 20 instead of V) (details will be described later).

Therefore, the first cartridge 20
The present invention can be used not only for the first game machine 10 but also for the second game machine 30, and compatibility with a higher model is ensured.
On the other hand, the second cartridge 40 includes the second game machine 30.
Can be used with the first game machine 10 but cannot be used with the first game machine 10.
Since the game device 10 is not electrically connected to the game device 10, destruction of a semiconductor memory or the like due to an overvoltage can be effectively prevented.

The difference between the driving voltages of the first cartridge 20 and the second cartridge 40 is that the second cartridge 40, which is a cartridge for a higher model, is driven at a low voltage for the purpose of power saving. This is because electronic components such as semiconductors are used. However, when such effects are not expected and power consumption reduction is not required, the same power supply voltage may be used in both game machines. In that case, the second game machine 30 is provided with the first cartridge 2
Depending on which of the cartridge 0 and the second cartridge 40 is mounted, it is not necessary to switch the supply voltage to the cartridge.

Next, a method for identifying the first and second cartridges 20 and 40 will be described in detail with reference to FIG. FIG. 4 is an explanatory diagram showing a method of detecting the first and second cartridges 20 and 40 by cartridge shape detection switches (hereinafter, referred to as “detection switches”) 35 by distinguishing the first and second cartridges 20 and 40 in shape. It is. Hereinafter, a method of detecting the first cartridge 20 and the second cartridge 40 separately by the detection switch 35 will be described.

As the detection switch 35, for example, an alternative selector switch is used, and is provided near the connector 37. The detection switch 35 selectively connects one of the 3.3 V output terminal and the 5 V output terminal of the DC-DC converter (383), and selects the power supply selected as the power supply terminal of the cartridge connected to the connector 37. Are connected to provide a circuit. In the initial state, the detection switch 35 is configured to select 3.3V.

FIG. 4A shows a state before and after the insertion of the second cartridge 40 into the insertion recess 34 of the second game machine 30 as viewed from the side. In this example, the insertion recess 34
The detection switch 35 is provided in the vicinity of the side end of the second cartridge 40. When the second cartridge 40 is mounted in the insertion recess 34, the detection switch 35 does not contact the second cartridge 40 due to the notch 412. Therefore, since the detection switch 35 maintains the initial state, the second game machine 30 detects that the cartridge is the second cartridge 40 and supplies the power (3.3 V) for the second cartridge 40. .

On the other hand, FIG. 4B shows a state before and after insertion of the first cartridge 20 into the insertion recess 34 of the second game machine 30 as viewed from the side. First cartridge 20
Is mounted in the insertion recess 34, the notch 412 is not formed in the housing 21, and the detection switch 35 is pushed down by the tip of the housing 21, so that the second game machine 30 Upon detecting that the cartridge is the cartridge 20, the power supply (5V) for the first cartridge 20 is supplied.

In the example shown in FIG. 4, an example in which the notch 412 is provided in the second cartridge 40 has been described, but the notch is provided in the first cartridge 20 instead of the second cartridge 40. May be. Further, a protrusion may be provided at a position where the protrusion comes into contact with the detection switch 35 of the second game machine 30 instead of the notch. However, in these cases, the initial state of the detection switch 35 must be at a position where the detection switch 35 is connected to the 5 V output terminal, and the content of the subsequent processing is different from the method of the configuration shown in FIG.

In this example, the first and second cartridges 20 and 40 are identified by the detection switch 3.
5 has been described in detail by making the first and second cartridges 20 and 40 make mechanical contact with each other based on the difference in the shapes of the first and second cartridges 20 and 40. However, the cartridge shape detection switch 35 is set to the first and second cartridges 20 and 40.
It is also possible to identify the first and second cartridges 20 and 40 by non-contact without contacting the first and second cartridges. Examples of such non-contact type cartridge identification include a photoelectric sensor type and a reed switch type.

FIGS. 5A and 5B show examples of the photoelectric sensor type. FIGS. 5A and 5B show a transmission type example in which the first and second cartridges 20 and 40 are identified based on whether or not the light L is transmitted. FIG.
In both cases (a) and (b) of FIG. 5, the cartridge shape detection switches 35-1 and 35-2 include a light emitting unit 35a and an optical sensor 35b. FIG.
In the case shown in (a), a rib 35s 'provided with an opening 418' is further included. On the other hand, FIG.
In the case shown in (1), a rib 35s "having no opening is provided in place of the rib 35s '. The rib 35s' or the rib 35s" configured as described above is attached to the first and second cartridges 20 and 40. Provided, light emitting unit 35
By providing the light sensor 35a and the optical sensor 35b in the insertion recess 34, the cartridge can be identified based on whether or not the light L transmits.

FIGS. 5C and 5D show an example of a reflection type for distinguishing the first and second cartridges 20 and 40 based on whether or not the light L is reflected. In this example, the cartridge shape detection switches 35-3 and 35-4 include the light emitting / receiving unit 35ab in both the cases of FIGS. 5C and 5D. The example illustrated in FIG. 5C further includes the above-described rib 35s ′, and the example illustrated in FIG.
It further includes a rib 35r having a reflecting surface 419 similar to s "but reflecting the light L. The rib 3 thus configured
5s' or ribs 35r are provided on the first and second cartridges 20 and 40, and the light emitting / receiving unit 35a is provided.
By providing “b” in the insertion recess 34, the cartridge can be identified based on whether or not the light L is reflected.

In addition to the above-described method, a magnetic material is added to the first and second cartridges 20 and 40, and the selector (35s) of the cartridge shape detection switch 35 provided in the insertion recess 34 is provided by the magnetic material. The first and second cartridges 20 and 40 can be identified by using a reed switch method for driving the first and second cartridges.

Next, referring to FIG. 6, an outline of the system blocks of the game system and the game machine cartridge will be described. FIG. 6 is a block diagram of the game machine and the game machine cartridge. The first
The details of the second cartridges 20 and 40 will be described later.

In FIG. 6, the information processing system includes:
Broadly speaking, the first and second cartridges 20 and 40
And a second game machine 30. First and second
Of the second game machine 30
Stores information such as a program necessary for executing the image display game, and can be detachably connected to the second game machine 30 as described above.

The second game machine 30 has a liquid crystal display (LC)
D) 32, cartridge connector 37, central processing unit (CPU) 360, and power supply unit 3.
80. The CPU 360 includes an 8-bit circuit unit 361 that performs 8-bit arithmetic processing having the same performance as a CPU (not shown) built in the first game machine 10 of a model (lower model) that has already been released and has low performance. And a 32-bit circuit unit 362 that performs high-performance arithmetic processing (for example, 32-bit arithmetic processing) unique to the second game machine 30. The I / O buffer controller 363 is connected to the 8-bit circuit section 361 and the 32-bit circuit section 362 via a bus, and the video RAM (V-
RAM) 364, working RAM (W-RAM) 36
5, the LCD controller 367 and the peripheral circuit 368 are connected. The peripheral circuit 368 performs processes such as audio processing, DMA (direct memory access), timer, and input / output control.

The liquid crystal display 32 and the power supply unit 380 are connected to the CPU 360.
3. The sound amplifier 391 and the speaker 392 are connected. The power supply unit 380 includes a power supply 381, a power switch 382, a DC-DC converter 383, and a voltage detection IC 384. The power supply 381 is preferably composed of a battery, and is provided with a DC-DC
Power is supplied to converter 383. The DC-DC converter 383 converts the DC power supplied from the power supply 381 to a plurality of different DC voltages (for example, −15 V,.
5V, 3.3V, 5V and 13.6V).
Then, the CPU 360 operates the first cartridge 2 according to the operation of the operation key 33 by the user (or the player).
0 or RO contained in the second cartridge 40
The program stored in M22 or M42 is executed, a game image based on the processing result of the program is displayed on LCD 32, and sound (or sound effect) is output from speaker 392.

Further, the CPU 360 has an insertion recess 34.
Is connected. Connector 37
A detection switch 35 such as a selector-type micro switch is provided in connection with. As described above, the detection switch 35 detects which of the first cartridge 20 and the second cartridge 40 has been inserted into the insertion recess 34 (that is, whether the first cartridge 20 or the second cartridge 40 has been mounted on the second game machine 30). It is. For example, the detection switch 35 detects the presence of the notch 412 when the second cartridge 40 is inserted, detects that the second cartridge 40 is mounted, and detects that the first cartridge 20 is inserted. When there is no notch 412, it detects that the first cartridge 20 has been mounted. When the detection switch 35 detects the second cartridge 40,
The power supply voltage of 3.3V is selected and the second cartridge 40 is selected.
To supply. On the other hand, when the detection switch 35 detects the first cartridge 20, it selects the power supply voltage of 5 V and supplies it to the first cartridge 20. Also, the CPU 36
0 includes the switching circuit 369. This switching circuit 369 is
The 8-bit circuit section 36 responds to the output of the detection switch 35.
One of the 1 and 32-bit circuit units 362 is activated.

Next, FIG. 7 shows a block diagram of a main part for identifying the first and second cartridges 20 and 40 in the second game machine 30 shown in FIG. That is, in the second cartridge 40, the ROM 42 and the RA
M43 forms a 3.3V interface memory. The 3.3V interface memory can perform data transfer in multiplex mode (for details,
See below). In the first cartridge 20, the ROM 22 is a 5V interface memory.

The CPU 360 includes a switching circuit 369 for selectively driving one of the 32-bit circuit unit 362 and the 8-bit circuit unit 361 based on the value of the register 362f supplied from the voltage detection IC 384. . More specifically, the 32-bit circuit unit 362 includes a second boot ROM
362e, second CPU core 362a, register 362
f, and a multiplex / 8-bit bus controller 362b. The “second” here means the second
Means a 32-bit operation unique to the game machine 30.

The 8-bit circuit section 361 includes a first boot ROM 361c, a first CPU core 361a, and an 8-bit bus controller 361b. Here, the “first” means an 8-bit operation unique to the first game machine 10.

The reset circuit 385 resets the CPU 360.

The detection switch 35 has an alternative selector 35s. The selector 35 s selectively connects one of the 3.3 V output terminal and the 5 V output terminal of the DC-DC converter 383 to connect the first or second cartridge 20 or 40 inserted into the insertion recess 34. To supply an output from the selected output terminal. In this example, the selector 3
5s is normally biased to connect to the 3.3V output terminal, ie, when the cartridge is not inserted into the insertion recess 34. That is, in the second game machine 30, the drive voltage of the memory system is based on 3.3V.

In this example, the type of the cartridge (first
Alternatively, a method for uniquely selecting the output voltage by using the second cartridge 20 or 40) will be described. As described above, when the first cartridge 20 is inserted into the insertion recess 34, a part thereof is connected to the selector 35s.
The detection switch 35 is provided at a position where the detection switch 35 comes into contact with.

With this configuration, as the first cartridge 20 is inserted into the insertion recess 34, the selector 35 s is moved by the contact portion of the first cartridge 20.
Pushed to V output terminal side. Then, the selector 35 s
Apart from the 3.3 V output terminal, which is the standard position, at the other available position, it is securely connected to the 5 V output terminal. After the selector 35s is connected to the 5V output terminal, the first cartridge 20 is electrically connected to the connector 37 and the DC-DC converter
A DC output of V is supplied to the first cartridge 20.

On the other hand, as described above, during the process of inserting the second cartridge 40 into the
The shape is such that it does not abut s. Therefore, even when the second cartridge 40 has been mounted in the insertion recess 34, the selector 35s is still positively connected to the 3.3V output terminal. As a result, 3.3 V of D is supplied from the DC-DC converter 383 to the second cartridge 40.
A C output is provided.

FIG. 8 is a circuit diagram of the 8-bit circuit unit 36 shown in FIG.
FIG. 3 is a block diagram showing details of a 1-bit and 32-bit circuit unit 362. In FIG. 8, an 8-bit circuit 361 includes a first
CPU core 361a, first access control unit (8-bit bus controller) 361b, and first boot ROM 36
1c. The first CPU core 361a has a first boot R
An access control unit that processes a start-up program stored in the OM 361c and performs a game process based on a first game machine program stored in a ROM 22 built in the first cartridge 20; The ROM 22 built in the first cartridge 20 is accessed via the 361b.

The 32-bit circuit 362 includes a second CPU core 362a, a second access control unit (or multiplex / 8-bit bus controller) 362b, and a second boot ROM 362e. The access control unit 36
2b specifically includes a multiplex bus controller 362c and an 8-bit bus controller 362d. The second CPU core 362a includes a boot ROM 362e.
The processing is performed based on a program for the second game machine stored in the ROM 42 incorporated in the second cartridge 40, while processing the startup program stored in the second cartridge 40. The ROM 42 and the RAM 43 incorporated in the second cartridge 40 are accessed via the. Specifically, the multiplex bus controller 362c reads the ROM 42 of the second cartridge 40,
Address data A0 to A23 for accessing data No. 2 are supplied to the ROM 42 at a first timing, and data D0 to D15 are received at a second timing, thereby sharing some bus lines. Further, the 8-bit bus controller 362d is provided with a RAM included in the second cartridge 40.
When writing / reading data to / from the memory 43,
Access control similar to that of an 8-bit CPU is performed. The multiplex bus controller 362 depends on whether the CPU accesses the ROM 42 or the RAM 43.
Either c or the 8-bit bus controller 362d is selected (specifically, as described later, selected according to the memory space accessed by the CPU).

Next, the internal structure of the second cartridge 40 will be described. FIG. 9 is a perspective view showing the detailed structure of the second cartridge 40. In FIG. 9, the housing 41 of the second cartridge 40 is divided into an upper housing 41a and a lower housing 41b. The lower housing 41b has side walls formed on the side and upper sides, and fitting recesses 415 are formed on inner portions of the left and right side walls. A projection 416 for positioning the circuit board 45 and a projection 417 are formed on the inner flat surface of the lower housing 41b near the fitting recess 415. Upper housing 4
1a is provided with a protrusion (not shown) at a position facing the protrusion 417, and the protrusion of the upper housing 41a fits between the protrusion 417 and the side wall, thereby forming the upper housing 41a. And the lower housing 41b is restricted from sliding, so that bending in the lateral direction is prevented.
In the upper housing 41a, a rib that engages with the side wall is formed at a portion facing the side wall of the lower housing 41b, and an engaging protrusion 418 is formed at a position that faces the fitting recess 415.

On the circuit board 45, a one-chip IC 48 containing a ROM 42 and a multi-access control unit 44 as an example of multiplex bus conversion means is mounted, and a RAM 43 and a backup battery 49 are mounted as necessary. You. Further, the circuit board 45 includes the ROM 4
2. A desired circuit pattern is formed to appropriately connect the RAM 43 and the battery 49 to the circuit, and to establish electrical connection between each component and the outside. Further, a notch 451 that engages with the protrusion 416 is formed in the peripheral portion of the circuit board 45. Then, on one side below the circuit board 45,
A plurality of connection terminals 46 (46-1 to 32) are formed at predetermined intervals in the horizontal direction. These connection terminals 46-1 to 32
Is exposed from the opening 414 of the housing 41 and the second
Is connected to the connector 37 of the game machine 30. Therefore, an edge connector 47 is constituted by one side below the circuit board 45 and the plurality of connection terminals 46-1 to 46-32 formed on the one side. The edge connector 4
The configuration of 7, that is, the shape of one side of the circuit board 45 and the positions, intervals, and the number of terminals of the plurality of connection terminals are the same as those of the first cartridge 20.

In this embodiment, the ROM 42
Although the multi-access control unit 44 and the multi-access control unit 44 are one-chip ICs, the independent multi-access control unit 44 may be connected to the ROM 42 by wiring. This configuration has an advantage that it can be easily manufactured. It is needless to say that the ROM 42 and the ROM 22 may be non-rewritable mask ROMs or rewritable flash ROMs.

Next, the first and second cartridges 20
And the detailed functional structure of 40 will be described. In addition,
FIG. 10 is a block diagram showing details of the first cartridge 20 and the second cartridge 40. FIG.
ROM 22 of first cartridge 20, ROM 42 of second cartridge 40, and multi-access control unit 44
FIG. 4 is a circuit diagram showing a connection state between an IC 48 including a connector and a connector 47. As shown in FIGS. 10A and 11, the ROM 22 included in the first cartridge 20 has a plurality of lead terminals. These read terminals are, for example, address terminals A0 to A15 connected to a 16-bit address bus, data terminals D0 to D7 connected to an 8-bit data bus, and control signal terminals (/ WR: write bar, / RD). : Lead bar, / CS: chip select bar) and power supply terminal (VDD).
-1 to 32. The IC 48 included in the second cartridge 40 has the ROM 42 and the multi-access control unit 44 formed on one chip, and has a plurality of lead terminals. The lead terminal of the IC 48 is the lower 16 bits of the 24-bit address data.
Terminals A0 / D0 through which bit address data and 16-bit data are multiplexed (multiplexed)
A15 / D15, terminals A16-A for upper 8 bits of address data of 24-bit address data
23, control signal terminals (/ WR, / RD, / CS, / CS
2) and a power supply terminal (VDD). Terminal A
0 / D0 to A15 / D15 are the first terminals of the edge connector 47 (46-6 to 21; numbers after the hyphen correspond to terminal numbers 6 to 21 shown in FIG. 12 described later). And the second timing are multiplexed (multiplex system).

As shown in FIG. 10 (b), in the second cartridge 40, the / CS signal is
2), and / CS2 is connected to the RAM 43.
That is, when the / CS signal is output, the IC 48
When the (ROM 42) is activated and the / CS2 signal is output, the RAM 43 is activated.
The / CS signal and the / CS2 signal are output by the access control unit 362b based on address data from the second CPU core 362a, which will be described later.

Next, the first and second cartridges 20
And 40 cartridge interfaces. FIG. 12 is a diagram illustrating the relationship between the purpose of use of each terminal of the first cartridge 20 and the terminal of the second cartridge 40 or the function of each terminal. In FIG.
The connection terminal 46-1 is arranged in the vertical direction of the left end column (“NO.” Column).
The first cartridge 20 (“ROM2”) for the first game machine 10 is indicated in the horizontal axis direction.
2), the ROM 42 of the second cartridge 40 for the second game machine 30 (the “ROM 42” column), and the RAM 43 of the second cartridge 40 for the second game machine 30.
The function of each terminal when accessing ("RAM 43" column) is shown. Here, the second cartridge 4
0 when accessing the RAM 43, the connection terminal 46-1
29 to 46-32 are the same as those of the first cartridge 20. However, the ROM 42 of the second cartridge 40
When the access is made, the connection terminals 46-6 to 29 are connected to the first terminals.
Are used as address terminals A0 to A23 (that is, terminals A16 to A23 are upper addresses). The connection terminals 46-6 to 46-21 are used as data terminals D0 to D15 at the second timing. Therefore, the connection terminals 46-6 to 21 become address lines in the case of the first timing, and become data lines in the case of the second timing. , Multiplex scheme). Therefore, in the following description, the connection terminals 46-6 to 21
Are denoted by symbols AD0 to AD15, and symbols A16 to A16 of connection terminals 46-22 to 29 used only as an address bus.
A description will be given separately from A23.

When the second cartridge 40 is mounted, the second game machine 30 has a 32-bit circuit section 36.
2 is activated. The internal data signal of the 32-bit circuit unit 362 is 32 bits. On the other hand, since the data signal terminal of the cartridge interface is 16 bits as described above, when inputting / outputting 32-bit data, the data is input / output twice in 16-bit units.

Next, the memory space in the second game machine 30 will be described. FIG. 13A shows the 32-bit circuit unit 362 of the CPU 360 of the second game machine 30.
FIG. 1 is a memory map showing a memory space as viewed from FIG.
3B is a memory map showing a memory space viewed from the 8-bit circuit unit 361 (or the CPU of the first game machine 10). As shown in FIG. 13A, in the 32-bit circuit unit 362, the address 00000000h
~ 0800000h contains internal ROM, internal RAM,
I / O and registers are assigned. In addition, addresses 080000000h to 0E000000h have R
OM42 is assigned and address 0E000000h
The RAM 43 is allocated to ０0E00FFFF.

The switching process for accessing the second cartridge 40 from the second game machine 30, accessing the ROM 42, and accessing the RAM 43 is performed as follows. First, the second CPU core 362
When a outputs an address in the range of 0800000h to 0E000000h, the / CS signal is output by the access control unit 362b and the ROM 42 is activated. On the other hand, if the second CPU core 362a is 0E0000
When an address in the range of 0h to 0E00FFFFh is output, the / CS2 signal is output and the RAM 43 is activated.

On the other hand, as shown in FIG. 13B, in the 8-bit circuit unit 361, addresses 0000h to 800h
An internal ROM, an internal RAM, an I / O, a register, and the like are allocated to 0h, and a ROM 22 is allocated to addresses 8000h to FFFFh.

Next, multiplex conversion using an address counter that enables sequential access will be described. FIG. 14 is a configuration diagram of a multi-access control unit 44 provided in the second cartridge 40 in order to realize access by the multiplex method. In FIG. 14, the multi-access control unit 44
Is configured by a multiplex conversion circuit using an address counter 441 in order to switch between sequential access and random access. As the address counter 441, a 24-bit counter is used, and has both functions of holding address data and incrementing. At the input / output terminal of the multi-access control unit 44, A [23: 1] input to the address counter 441.
6] means upper addresses A23 to A16, and AD [1
5: 0] is shared by the lower addresses A15 to A0 and the data buses D15 to D0 in a time sharing manner. Further, a terminal LOAD of the address counter 441 receives a / CS signal (chip select bar; symbol “/” indicates low active), and a terminal CLOCK has a / RD signal (lead bar). Is entered. Based on these four types of inputs, the address counter 441 outputs a memory address bus MA [23: 0] signal for accessing the ROM 42. A data bus M connected to a bus line of the ROM 42
D [15: 0] is AD [15:] of the terminals 46-6 to 46-21.
0] and outputs data D15 to D0.

Next, the ROM 42, the RAM 43 and the RO
The read / write access operation in M22 will be described. FIG. 15 shows that the second game machine 30 stores the memory (ROM 22) of the first cartridge 20 and the memory (ROM 42 and RAM 4) of the second cartridge 40.
6 is a time chart for performing a read / write access operation for 3). In particular, FIG. 15A shows the reading operation of the ROM 42 of the second cartridge 40, and FIG.
FIG. 15B shows a write operation in the RAM 43.
FIG. 15C shows a read operation in the RAM 43, and FIG.
(D) shows the reading operation of the ROM 22 of the first cartridge 20. Note that the case where the first game machine 10 performs a read operation on the ROM 22 of the first cartridge 20 is the same as in FIG.

In FIG. 15A, in order from the top,
Ck indicates the waveform of the system clock, and AD [15:
0] indicates the multiplex transfer operation of the address and data at address A0 / data D0 to A15 / D15 at connection terminal numbers 6 to 21 shown in FIG. 12, and / CS indicates the multiplex transfer operation of the connection terminal shown in FIG. The operation of the chip select bar at No. 5 is shown.
12 shows the operation of the lead bar at the connection terminal number 4 shown in FIG. 12, and A [23:16] indicates the addresses A16 to A23 at the connection terminal numbers 22 to 29 shown in FIG.
, And the lowermost row t0 to t
Reference numeral 13 denotes a time synchronized with the falling edge of the system clock Ck.

When reading data from the ROM 42, random access and sequential access can be selectively performed. That is, the second game machine 3
When the address data is output from the second CPU core 362a, the multiplex bus controller 362c of “0” performs the first timing (for example, times t1 and t9).
Output the address data to the buses A [23:16] and AD [15: 0]. The address counter 441 loads (or latches) upper address data supplied from the bus A [23:16] and lower address data supplied from the bus AD [15: 0] at the falling edge of the / CS signal, and counts the count value. It is supplied to the ROM 42 as read address data A0 to A23 (MA [23: 0]). Subsequently, the multiplex bus controller 362c outputs a / RD signal at a second timing (for example, time t3). The multi-access control unit 44 outputs the data D0 to D15 (MD [15:
0]) to the terminals 46-6 to 21 (AD [15: 0]), and is supplied to the 32-bit circuit unit 362 via the I / O buffer controller 363 of the second game machine 30.

The address counter 441 outputs the signal /
The / RD signal is input to the terminal CLOCK so that the count value is incremented each time RD is output. This implements sequential access control.

As described above, the ROM 42 stores the times t1 to t
4 and random access control during time t5 to t8 and time t9 to t1.
Random access control is performed again during the period 2. That is, the / CS signal is set to be low from the time t1 to the time t8. On the other hand, the / RD signal is generated between times t3 and t
4. It is set low intermittently between times t5 to t6 and times t7 to t8. In this state, after a read address is output to AD [15: 0] from before time t1 to after time t2, sequential access is performed from time t4 to before time t9, and data is sequentially transferred to three blocks. Is read. After time t9, random access control is performed.

Note that the sequential access is a control method for reading out memory contents at consecutive addresses. Therefore, if the addresses are consecutive, C
There is no need to output the address from the PU, and the control signal (/
RD) alone can count up the address of the memory. That is, data can be read at high speed as much as there is no need to output an address. At the start of the execution of the program, the program data may be collected and read out sequentially in advance, so that the program may be started smoothly.

The random access is a control method for reading out the contents of a memory at a non-consecutive address. It is necessary to input an address every time the memory is read, and data reading is slow.

As described above, the multiplex system for accessing the IC 48 by combining random access control and sequential control is employed for the following reason. In other words, multiplexed buses
While there is an advantage that the number of pins (number of pins) of the interface bus is small, some of the connection terminals are shared by the address bus and the data bus, so that data can be output only after an address is input, and a normal The access speed is slower than the bus. However, the problem is
This can be improved by the above-described sequential access control. However, in order to execute the sequential access control, a special circuit (address counter) corresponding to the sequential access is required on the memory side.

On the other hand, writing or reading of the RAM 43,
Alternatively, reading from the ROM 22 is realized by random access. A time chart of this operation is shown in FIG.
(B) to (d). Since the access in this case is separate for the address bus and the data bus as described above,
The normal access method is used instead of the multiplex method.

Next, the operation of the game system (particularly, the second game machine 30) will be described. Note that FIG.
Is a flowchart for describing a specific operation of the game system. First, prior to the start of game play, in step S1, one of the first and second cartridges 20 and 40 is inserted into the insertion recess 34 by the user, and the second game machine 3
0 and connected to the connector 37.
After the power switch 382 is turned on by the user in step S2, the following processing is performed.

First, in step S3, it is determined whether the mounted cartridge is the first cartridge 20 or the second cartridge 40 based on the state of the selector 35s of the detection switch 35.

In step S3, the second cartridge 40
When it is determined that the
Is performed when the cartridge 40 is mounted. That is, in step 4, based on the fact that the selector 35s is connected to the off side, the power supply voltage (3.3 V) generated from the DC-DC converter 383 is selected and supplied to the second cartridge 40, The process proceeds to step S5.

In step S5, in order to memorize and hold that the second cartridge 40 is mounted,
A logic "1" (high level) is loaded into the register 362f for storing the cartridge type. Then, the process proceeds to step S6.

In step S6, the reset circuit 38
5 releases the reset of the CPU 360 and activates it. Then, the process proceeds to step S7.

In step S7, when the 32-bit circuit section 362 for the second game machine 30 in the CPU 360 is activated, the second CPU core 362a is turned on by the second boot ROM.
The startup program stored in 362e is executed.
Then, the process proceeds to step S8.

In step S8, the second CPU core 3
62a is based on the fact that the value stored in the cartridge type register 362f is "1",
Proceed to.

In step S9, the processing based on the program in the second boot ROM 362e is continued. Then, the process proceeds to step S10.

In step S10, the access control section 362b is operated to set the R in the second cartridge 40.
Read control of OM42 (read of RAM 43 as necessary
Write control) is performed. At this time, the read control of the ROM 42 is performed by the multiplex method as described above. In other words, for each access, address data A0 to A15 (lower address) and A16 to A24 (upper address) are generated at the first timing and supplied to the ROM 42 via the terminals 46-6-29. At the second timing, the data D0 to D15 are read via the terminals 46-6 to 46-21. As a result, the terminals 46-6 to 46-21 are multiplexed.
Such bus switching is performed by the multi-access control unit 44. In the writing and reading control of the RAM 43, the terminals are not used multiplely (not in the multiplex system).
According to the normal access method. Then, the process proceeds to step S
Proceed to 11.

In step S11, the second CPU core 362a executes the game program for the second game machine read from the ROM 42, generates a game image and displays the game image on the liquid crystal display 32, and displays the effect of the game. The sound is output to the speaker 392. Then, the process proceeds to step S12.

In step S12, it is determined whether or not the game is over. If it is determined that the game is not over, the process returns to step S10, and the operations in steps S10 to S11 are repeated until the game is over.

On the other hand, when the first cartridge 20 is mounted on the second game machine 30, in step S3 described above, the detection switch 35 detects that there is no notch 412, and First cartridge 20 for
Is determined to be mounted. If it is determined that the cartridge is the first cartridge 20, the process proceeds to the next step S21.

In step S21, a process when the first cartridge 20 is mounted is performed. That is, based on the fact that the detection switch 35 is connected to the ON side, the power supply voltage (5 V) generated from the DC-DC converter 383 is selected by the detection switch 35 and supplied to the first cartridge 20. You. Then, the process proceeds to step S22.

In step S22, a register 362 for storing the cartridge type is stored in order to store the fact that the first cartridge 20 is mounted.
A logic "0" (low level) is loaded into f. Thereafter, after the same processing as in steps S6 and S7 described above is performed, it is determined in step S8 that the value of the register is logic "0", and the flow advances to step S23.

In step S23, switching circuit 369
Is started, and is switched from the 32-bit circuit unit 362 to the 8-bit circuit unit 361. Then, the process proceeds to step S24.

In step S24, the second CPU core 362a is deactivated and the first CPU core
61a is activated. Then, the process proceeds to step S25.
Proceed to.

In step S25, the first CPU core 361a executes a start-up program stored in the first boot ROM 361c. Then, the process proceeds to step S
Proceed to 26.

In step S26, the read control of the ROM 22 built in the first cartridge 20 is performed by the 8-bit bus controller 361b. In this case, the first C is output at the timing shown in FIG.
Address data for processing of the PU core 361a is generated. Then, the process proceeds to step S27.

In step S27, the game processing for the first game machine is executed based on the game program for the 8-bit game machine read from the ROM 22 of the first cartridge 20. Then, the process proceeds to step S
Proceed to 28.

In step S28, it is determined whether or not the game is over. If it is determined that the game is not over, the process returns to step S26, and the operations of steps S26 and S27 are repeated until the game is over.

Hereinafter, examples other than those described above as the cartridge identifying means will be described with reference to FIGS. 17, 18, 19, and 20.

First, referring to FIGS. 17 and 18, an identification code corresponding to the type of the cartridge is stored in a storage medium provided in the cartridge, and the identification code is read out when the power is turned on. An example of identifying whether the cartridge is the second cartridge 40 or the first cartridge 20 will be described.

FIG. 17 is a main block diagram showing the identification processing of the first and second cartridges 20 and 40 as in FIG. The second game machine 30r in the present example is different from the second game machine 30 shown in FIG.
The second cartridge 40r and the detection switch 35 are respectively connected to the second cartridge 40r and the voltage selector 38.
Has been replaced by Further, the voltage detector 384 and the register 362f in the second game machine 30 are omitted. The voltage selector 38 is connected to the 32-bit circuit unit 362 and is controlled by a control signal output from the 32-bit circuit unit 362.

The second cartridge 40r has a notch 4
Instead of 12, an identification code for identifying the type of itself is recorded in an identification code area 421 provided in the 3.3V interface memories 42 and 43. The voltage selector 38 is, like the detection switch 35, a DC-DC
The switch for selecting the output from the converter 383 is operated electronically, not mechanically. As a result of such a change, in this example, the voltage detection IC 384 and the register 362f shown in FIG. 7 are unnecessary. The CPU and the information processing apparatus having the above-described changes are referred to as CPU 360r and second game machine 30r, respectively, to distinguish them from CPU 360 and second game machine 30 shown in FIG.

Next, the operation of the second game machine 30r for identifying a cartridge using an identification code will be described. When the power of the second game machine 30r is turned on, a voltage of 3.3 V is supplied to the first or second cartridge 20 or 40. And the second
The CPU core 362a starts.

The second CPU core 362a includes the first and second CPU cores 362a.
Attempts to read the identification code stored in a specific area of the memory in the cartridges 20 and 40 of the first embodiment. If the read is successful, if the read identification code is a code indicating the second cartridge 40r, the second CP
The U core 362a continues the processing.

On the other hand, if the read identification code does not indicate the second cartridge 40r, or if the read of the identification code has failed, the cartridge is identified as the first cartridge 20. As a result, 32
The bit circuit unit 326 causes the voltage selector 38 to select the 5V voltage. Then, the second CPU core 362a activates the switching circuit 369.

The switching circuit 369 is connected to the second CPU core 362
a, while activating the first CPU core 361a.

Next, the operation of the second game machine 30r in this example will be described with reference to the flowchart shown in FIG. It should be noted that in the flowchart shown in FIG.
3, S5, S6, S21, and S22 have been deleted, step S7 has been replaced with step S116, step S8 has been replaced with step S118, while step S120 has been newly inserted between steps S118 and S23. .

Hereinafter, the operation of the second game machine 30r will be described with emphasis on the steps unique to this example. First, in step S1, the first or second cartridge 20 or 40 is inserted into the insertion recess 34 of the second game machine 30r. Then, in S2, the power switch 382 of the second game machine 30r is turned off by the user.
N.

In step S 4, 3.3 V DC is supplied from the DC-DC converter 383 to the cartridge via the voltage selector 38. Then, the process proceeds to the next step S116.

At step S116, CPU 360
The second CPU core 362a in r starts to execute the processing described in the second boot ROM 362e.
Then, the identification code stored in the identification code area of the inserted cartridge is read. That is, when the second cartridge 40r is inserted into the connector 37, the identification code is read from the identification code area 421.

On the other hand, when the first cartridge 20 is inserted into the connector 37, the identification code indicating the second cartridge 40r is not read out as described above. Then, the process proceeds to the next step S118.

In step S118, step S1
The type of the cartridge inserted into the connector 37 is determined based on the content of the identification code read in 16. In this example, it is determined whether or not the inserted cartridge is the second cartridge 40r.

Yes, that is, the second cartridge 40
If it is determined that it is r, the process proceeds to step S
The processing of 9 to S12 is executed.

On the other hand, if No in step S118, that is, if it is determined that the cartridge is not the second cartridge 40r but the first cartridge 20,
The process proceeds to step S120.

In step S120, the voltage selector 3
8, 5V is selected instead of 3.3V. Then, the process executes the processes of steps S23 to S28 described above.

Here, steps S116 and S118
Will be described in more detail. When the second cartridge 40r is mounted, the processing is performed as described above. On the other hand, when the first cartridge 20 is mounted, since the 3.3 V voltage is supplied in step S4, even if an attempt is made to access the first cartridge 20 in step S116, normal access cannot be performed. In addition, even if access is successful, the first cartridge 20 does not have the identification code area 421 itself.
As a result, in step S116, since the identification code of the first cartridge 20 is not read out, it is determined that the first cartridge 20 is mounted, that is, No.

The drive voltage of the second cartridge 40r and the drive voltage of the first cartridge 20 are common (for example, 3.3
As V), if a dedicated memory for storing an identification code accessed by common bus control (for example, separate bus control) is separately housed in the cartridge, the second CPU core 362a can determine the type of the cartridge. Regardless, the dedicated memory can be accessed, and the cartridge identification code can be correctly read from the identification code area 421 or the identification code area of the first cartridge 20.

Next, referring to FIGS. 19 and 20, the first and second cartridges 2 utilizing the short-circuit of the signal line will be described.
A method for identifying the types 0 and 40 will be described.
FIG. 19 is a block diagram showing the main parts relating to the identification processing of the first and second cartridges 20 and 40, as in FIG.

[0131] The second game machine 30rr in this example is:
In the second game machine 30 shown in FIG. 7, the second cartridge 40 and the detection switch 35
Cartridge 40rr and a voltage selector 38, and the insertion recess 34 has a voltage selector 38
, Two signal lines W are newly provided.
The second cartridge 40rr has an insertion recess 3
4 is provided with a short-circuit line S for short-circuiting the two signal lines W in a state where the signal line W is attached to the signal line W.

The second game machine 3 configured as described above
At 0rr, the signal line W is not short-circuited even if the first cartridge 20 is mounted in the insertion recess 34. But,
When the second cartridge 40rr is mounted in the insertion recess 34, the two signal lines W are short-circuited by the short-circuit line S.
The second game machine 30rr identifies the type of the cartridge by detecting the short-circuit state of the two signal lines W. The voltage selector 38 selects one of 3.3 V and 5 V based on the short-circuit state of the signal line W.

When the first and second cartridges 20 and 40rr are identified by the short circuit of the two signal lines W, the operation of the second game machine 30rr uses the identification codes to identify the first and second cartridges. This is substantially the same as the case of the second game machine 30r that identifies the game machines 20 and 40. However, the second game machine 30rr
The CPU core 362a detects a short-circuit state of the signal line instead of reading the identification code. In this case, since only the short-circuit state is detected, the short-circuit state can be correctly detected even when the first cartridge 20 is mounted and a voltage of 3.3 V is supplied.

Next, the operation of the second game machine 30rr in this example will be described with reference to the flowchart shown in FIG. It should be noted that in the flowchart shown in FIG.
3 is deleted, and step S104 is newly inserted between steps S2, S4, and S21.

Hereinafter, the operation of the second game machine 30rr according to the present embodiment will be described with emphasis on steps unique to the present embodiment. First, in step S1, the cartridge is inserted into the insertion recess 34 of the second game machine 30rr. Then, in S2, the user turns on the power switch 382 of the second game machine 30rr.

In step S104, it is determined whether signal line W is short-circuited. If Yes, that is, if it is determined that the signal line W is short-circuited by the short-circuit line S provided in the second cartridge 40rr, the processes in steps S4 to S12 described above are executed.

On the other hand, if No, that is, if it is determined that the signal line W is not short-circuited because the first cartridge 20 does not have the short-circuit line S, the above-described steps S21 to S2
8 is executed.

As described above, according to the present invention, switching is automatically performed so that access control suitable for the mounted model can be performed depending on which cartridge of the upper model or the lower model is mounted. Can be used.

Further, according to the present invention, even if the data width of the connector is not sufficient when a processor having a relatively large number of data processing bits is employed in an information processing device, a game device, or the like, the data processing bit of the processor is not required. A memory having the number of data bits corresponding to the number can be connected to a common bus. Also, in a case where a plurality of types of processors having different data processing bit numbers are mounted on an information processing device, a game device, or the like for software compatibility or the like, a memory corresponding to each processor is connected to a common bus. Can be accessed.

Further, in the present invention, even when the supply voltage to the cartridge and the operation mode are different depending on the type of the built-in memory, the cartridge is identified and the supply voltage and the central processing means are determined according to the identification result. By switching the operation mode, there is an effect that the memory in the cartridge can be accessed.

Further, the present invention incorporates a multiplex bus transfer mode technology that not only supports two types of memories having different numbers of bits of address signals but also supports two types of memories having different numbers of bits of data signals. At the same time, it is possible to provide a cartridge provided with a function of identifying whether it is dedicated to an upper model or a lower model.

Although the present invention has been described in detail, the above description is merely illustrative of the present invention in every respect.
It is not intended to limit its scope. It goes without saying that various improvements and modifications can be made without departing from the scope of the invention.

[Brief description of the drawings]

FIG. 1 is an external view for explaining the principle of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is an external view for explaining the principle of the information processing apparatus according to one embodiment of the present invention.

FIG. 3 is a perspective view showing a mode in which a second cartridge and a first cartridge are used for a second game machine in the information processing apparatus shown in FIG. 1;

4 is an explanatory diagram of a cartridge identification method in the information processing device shown in FIG.

FIG. 5 is an explanatory diagram of a method for identifying a cartridge using a photoelectric sensor system.

FIG. 6 is a block diagram illustrating a system configuration of the information processing apparatus illustrated in FIG. 1;

FIG. 7 is a block diagram showing a configuration of a main part of a cartridge identification function in the information processing apparatus shown in FIG. 6;

FIG. 8 is a block diagram showing a main part relating to bus control in the 8-bit circuit unit and the 32-bit circuit unit shown in FIG. 6;

FIG. 9 is a perspective view showing a detailed structure of a second cartridge shown in FIG.

FIG. 10 is a block diagram showing a detailed structure of the first and second cartridges shown in FIG.

11 is a circuit diagram showing a connection state between an IC including a ROM of the first cartridge, a ROM of the second cartridge, a multi-access control unit, and a connector shown in FIG. 6 and a connector;

FIG. 12 is an explanatory diagram illustrating a cartridge interface of the information processing apparatus illustrated in FIG. 6;

13 is an explanatory diagram showing a memory map in the first and second cartridges shown in FIG.

FIG. 14 is a block diagram illustrating a configuration of a multi-access control unit.

FIG. 15 is a time chart for explaining a read / write access operation in a ROM and a RAM of the first and second cartridges shown in FIG. 6;

FIG. 16 is a flowchart illustrating an operation of the information processing apparatus illustrated in FIG. 6;

FIG. 17 is a main part block diagram relating to cartridge identification processing based on an identification code, different from the example shown in FIG. 7;

18 is a flowchart illustrating a cartridge identification method in the information processing device illustrated in FIG.

FIG. 19 is a main part block diagram relating to cartridge identification processing based on a short-circuit state, different from the examples shown in FIGS. 7 and 17;

20 is a flowchart illustrating a cartridge identification method in the information processing device illustrated in FIG.

FIG. 21 is a block diagram showing a configuration of a conventional information processing system.

FIG. 22 shows a conventional information processing system C shown in FIG.
It is an external view of GB.

FIG. 23 is an external view of the cartridge shown in FIG. 21.

[Explanation of symbols]

 Reference Signs List 10 first game machine 20 first cartridge 11, 21, 31, 41 housing 22, 42 ROM 30 second game machine 12, 32 liquid crystal display 13, 33 operation switches 14, 34 Insert recess 35 Detection switch 360 CPU 361 8-bit circuit section 362 32-bit circuit section 380 Power supply unit 37 Connector 40 Second cartridge 412 Notch section 413 Projection section 43 RAM 44 Multi-access Control unit 45 ... Circuit board 46 ... Connection terminal 47 ... Edge connector 48 ... IC

──────────────────────────────────────────────────続 き Continuation of front page (51) Int.Cl. ⁷ Identification code FI G06F 13/36 520 G06F 13/36 520E (56) References JP-A-64-44588 (JP, A) JP-A-61-67140 (JP, A) JP-A-9-106444 (JP, A) JP-A-10-255910 (JP, A) JP-A-7-204349 (JP, A) JP-A-11-333144 (JP, A) Kaihei 2-64753 (JP, A) Taisuke Nishijima, From the history of standardization to the outline of the standard I just want to know about this PC Card Standard, Interface, Japan, CQ Publishing Co., Ltd., December 1, 1999, Volume 25 No. 12, p. 56-68 Yuichi Kawahara, RISC Home PC MSX TurboR, Monthly ASCII, Japan, ASCII Corporation, November 1, 1990, Vol. 14, No. 11, p. 365-368 Emergency Bulletin MSX turboR, MSX magazine, ASCII, Japan, ASCII, October 1, 1990, Vol. 8, No. 10, p. 52-53 (58) Fields investigated (Int.Cl. ⁷ , DB name) A63F 9 / 22,13 / 00,13 / 08 G06F 3/08 G06F 12/00-12/06 G06F 13/16-13 / 18 G06F 13/36 G06K 17 / 00,19 / 07

Claims (4)

(57) [Claims] 1. A first cartridge for a first game machine that has already been released, and a second cartridge compatible with the first game machine.
A game system comprising a game machine and a second cartridge for the second game machine, wherein the first cartridge has a first connector having a first data width, and a first connector having a first data width. A second connector having a first data width; and a second semiconductor memory having a second data width larger than the first data width. An insertion recess into which the first cartridge and the second cartridge can be inserted; a third connector having the first data width provided inside the insertion recess; a third connector near a side end of the insertion recess and the third connector. The first cartridge is provided in the vicinity, and is pushed down by the distal end portion of the housing of the first cartridge when the first cartridge is inserted into the insertion recess. In the state where the selector switch is depressed, the mode is started in the same mode as the central processing means of the first game machine, and in the state where the selector switch is not depressed, the second game is executed. In a state in which the central processing means which is started in a dedicated mode for the machine and the selector switch is depressed, the semiconductor memory connected to the connector is accessed by a normal bus control, and in a state in which the selector switch is not depressed. A bus control means for accessing the semiconductor memory connected to the connector by multiplex control, wherein the second cartridge is at least one of the left and right side end portions in the insertion direction so as not to contact the selector switch. Notch formed in the game machine, and the game machine and the second semiconductor memory And a multiplex bus conversion means for time-divisionally controlling exchange of addresses and data between the game system and the game system. 2. The first semiconductor memory stores a program for a central processing unit of the first game machine, and the second semiconductor memory stores a program for a mode dedicated to the second game machine. The game system according to claim 1, wherein the game system stores a program. 3. The first semiconductor memory is driven by a first voltage, the second semiconductor memory is driven by a second voltage, and the selector switch of the second game machine is pushed down. In the state, the first voltage is supplied to the semiconductor memory connected to the connector, and when the selector switch is not depressed, the second voltage is supplied to the semiconductor memory connected to the connector. The game system according to claim 1, further comprising a voltage supply unit that performs the operation. 4. A first cartridge for a first game machine that has already been released, and a second cartridge compatible with the first game machine.
A game system including a game machine and a second cartridge for the second game machine, wherein the first cartridge has a first connector having the first data width, and a first connector having the first data width. Wherein the second cartridge includes a second connector having the first data width, and a second semiconductor memory having a second data width larger than the first data width. An insertion recess into which the first cartridge and the second cartridge can be inserted; a third connector having the first data width provided inside the insertion recess; a third connector near a side end of the insertion recess. The first cartridge is pushed by the front end portion of the housing of the first cartridge when the first cartridge is inserted into the insertion recess. 2's alternative selector switch being defeated, in the state where the selector switch is not pushed down, the
Starting in the mode dedicated to the second game machine, in a state where the selector switch is pushed down, the center of the first game machine is
A central processing unit that starts in a mode equivalent to the processing unit; and a state in which the semiconductor switch connected to the connector is accessed by multiplex control when the selector switch is not pressed down, and the selector switch is pressed down. A bus control means for accessing the semiconductor memory connected to the connector by a normal bus control, wherein the second cartridge is inserted into at least one of the right and left side surfaces so as not to contact the selector switch. A multiplex bus conversion means for multiplexing a part of a terminal between the game machine and the second semiconductor memory at a first timing and a second timing by using a notch formed at a tip portion; A game system, characterized in that: