JP3282116B2 - Display drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving device for displaying a fixed pattern and an arbitrary dot pattern (hereinafter referred to as "character pattern" for simplicity). The present invention relates to a display driving device in which the relative display power of a pattern (expressed by brightness, contrast, etc.) is improved.

[0002]

2. Description of the Related Art As a method of controlling a display panel capable of displaying a fixed pattern and a character pattern, a method using a display drive control IC capable of displaying both the fixed pattern and the character pattern has been conventionally known. There has been a method of using both a dedicated display drive control IC and a character pattern dedicated display drive control IC.

[0003]

However, in the former method, the drive timing period of the fixed pattern is the same as the drive timing period of the character pattern, and the display power (luminance) of the fixed pattern portion depends on the corresponding display panel. ,
There is a problem in that the display power of the character pattern portion does not match the contrast and the visual impression is unnatural.
In addition, the latter method has a problem that the display drive control device itself is prevented from being reduced in size and an input / output circuit configuration between the display panel and the display drive control device is complicated.

[0004] It is an object of the present invention to provide a display driving apparatus which solves the problem and eliminates visual unnaturalness while taking the former method.

[0005]

Means for Solving the Problems] The present invention To this end, multiple
Number of common signal lines and multiple segment signal lines
A display element for an arbitrary dot pattern and a fixed
Display elements for the turn are arranged, and the
Selected according to the plurality of common signal and display data to be I Bed
By 1 or more, which is to input a plurality of segment signals which become active at the same time, driving the display element for the display element and the fixed pattern for the arbitrary dot pattern
In the display driving device designed to dynamic, the plurality of co
Display for the fixed pattern when the mon signal is input
Times to obtain the logical sum of two or more of the above common signals for an element
A common signal selection circuit including a common signal selection circuit.
The output of the circuit is input to the plurality of common signal lines,
The plurality of segment signals are the plurality of segment signals.
Display element for the arbitrary dot pattern input to the line
Number of common signals per row of common signal lines for children
The common signal for the display element for the fixed pattern
The number of common signals per line was increased .

In the present invention, the display element for the fixed pattern is provided.
A circuit that obtains the logical sum of a plurality of common signals for the
An agate can be used.

[0007]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of a display panel 1 of the embodiment, and FIG. 2 is a block diagram of a display drive control IC 2 for driving the display panel 1.

The common signal input terminal group 101 of the display panel 1 according to the present embodiment has the character pattern terminals COM1 to C
OM8, COM9 to COM16, COM17 to COM2
4, 4 blocks like COM25 to COM32 (vertical 4
Characters), and the terminal for the fixed pattern is COM
M and one.

Reference numeral 102 denotes a group of segment signal input terminals, and SEG1 to SEG5, SEG6 to SEG10, SE
As shown by terminals G11 to SEG15 and SEG16 to SEG20, four blocks (for four horizontal characters) are provided. That is, one character pattern is a common 8 × segment 5 and is composed of a total of 16 character patterns.

[0010] 103 is a dot LCD, 104 are fixed pattern LCD in advance a specific pattern is formed for constituting a character pattern, one of the LCD also common Shin
Signal lines and segment signal lines . Further, 105 is a common signal selection circuit, the common signal input terminal group 106 consisting of the terminal COMM1~COMM4 the terminal COM1-COM3 2 and the fixed pattern for a character pattern, pin COMM1~COMM4 input
And an OR gate 107 connected to the

In the display driving control IC 2 shown in FIG.
01 is the character digit (indicating the number of the character to be displayed in the horizontal direction)
A display address register for outputting the address (position) data of the display data memory 202; a display data memory for outputting a character code of a character to be displayed based on an address command from the display address register 201; COM1 to COM32, COMM1
A common address register for outputting any one of the COMM4.

Reference numeral 204 denotes a character generator ROM, which uses the character code output from the display data memory 202 and the common address data output from the common address register 203 to output the common address of the character pattern selected by the character code. Is read out.

Reference numeral 205 denotes a fixed pattern common position detecting unit for detecting a common address of a fixed pattern from the common addresses sequentially output from the common address register 203, and 206 denotes a fixed pattern common position detecting unit 2
The fixed pattern data address register 207 updates a fixed pattern data address every time a detection signal is output from the reference pattern 05. Output address data from the fixed pattern data address register 206 is output only when a detection signal is output from the fixed pattern common position detection unit 205. Is a selector for selecting.

A character generator RAM 208 stores character pattern character data and fixed pattern data. Reference numeral 209 denotes a character generator ROM / RAM selection circuit which, when outputting a detection signal from the fixed pattern common position detection unit 205, operates the selector 210 to output the character generator R / R.
The output data from the AM 208 is selected, and at other times, the output data from the character generator RAM 208 or the character generator ROM 204 is selected.

Reference numeral 211 denotes a parallel / serial conversion circuit that converts parallel data output from the selector 210 into serial data, 212 denotes a shift register that accumulates the obtained serial data for one row (for all segment lines),
A latch 213 temporarily holds the latch and sends it to the segment terminal group 102 of the display panel 1. The display panel 1
The circuit for sending a signal to the common signal selection terminal group 106 is not shown.

When the display address of the first digit is output from the display address register 201, the character code output from the display data memory 202 specified by the address and the first common address data output from the common address register 203 are used. , Character generator ROM 204 or character generator RAM 2
From 08, data on the common line specified by the common address data out of the character pattern selected by the character code is output.

For example, in the example of FIG. 1, the first character "A" is selected in the character code, and the common signal is the first COM1.
Becomes active, the data is “011”.
"10", which is converted into serial data by the conversion circuit 211 and stored in the shift register 212. At this time,
One of the character generator ROM 204 and the character generator RAM 208 is selected by a character generator ROM / RAM selection circuit 2 for capturing a character code.
The switching is performed by the selector 210 which is switched by 09.

Next, when the display address of the next digit is output from the display address register 201, the display data memory 2
02, the next character code is read out, and the character code and the common address output from the common address register 203 (this does not change until one line of character code reading is completed) are used as the character generator ROM 204. Or character generator RAM 208
Of the character patterns selected by the character code from
The data on the common line specified by the common address data is output.

For example, in the example of FIG. 1, the character "B" of the next digit is selected by the character code, and the common signal is the first COM.
1 is active, the data is “11”.
110 ”, which is converted into serial data by the conversion circuit 211 and stored in the shift register 212.

As described above, when the first common address is designated, the character code is sequentially selected one line at a time, one digit at a time, and the segment data on the common signal line corresponding to the common address is determined. The data is accumulated in the shift register 212, latched by the latch 213, and simultaneously input to each terminal of the segment signal input terminal group 102 of the display panel 1 at a predetermined timing. At this time, the terminal COM of the common signal input terminal group 101 of the display panel 1 is connected.
1 signal becomes active. Therefore, this terminal COM
The dot LCD 103 selected by the segment signal on one line is driven only during the active period of the signal of the common terminal COM1.

Thereafter, the common address is changed to the next address (C
OM2), the same operation as described above is performed, and when the signals up to the signal at the common terminal COM8 are sequentially activated,
“A” to “D” in FIG. 1 are driven and displayed. Continue further
When the common address is sequentially updated, "E" to "H" are sequentially displayed, followed by "I" to "L", "M" to "P".
Is displayed, and this is repeated thereafter.

As described above, the signal of the terminal of the common signal input terminal group 106 of the common signal selection circuit 105 in FIG. 1 is changed from COM1 → COM2 →... By the common signal output (not shown) of the display drive control IC2.・ ・ ・ → COM8 → C
OMM1 → COM9 → ・ ・ ・ ・ → COM16 → COMM
2 → COM17 → ・ ・ ・ ・ → COM24 → COMM3 →
COM25 becomes active repeatedly in the order of COMM4. At this time, the timing period during which the signal of each terminal becomes active is the same.

Hereinafter, this timing period is called a duty. This duty is common signal input terminal group 10
A period (called one frame) in which one of the 36 terminals COM1 to COMM4 of No. 6 is swept by one cycle is represented as a denominator, and a timing period in which a signal of one common terminal is active is represented as a numerator.

Next, the display of the fixed pattern will be described. When the fixed pattern common position detecting unit 205 detects the timing at which the common position (COMM1) becomes active, the fixed pattern address register 206 reads the first digit fixed pattern of the common position from the character generator RAM 208. That is, in this case, the fixed pattern common position detector 205 causes the selector 207 to output the output from the fixed pattern data address register 206 to the character generator RA.
M208 and input to character generator ROM /
The selector 210 causes the output of the character generator RAM 208 to be converted by the RAM selection circuit 209 to the conversion circuit 211.
, The shift register 212 accumulates segment data for each digit of the common position. In the example of FIG. 1, four digits are sequentially stored.

Since the initial value of the fixed pattern data address register 206 is fixed, the common position CO
When MM2, COMM3, and COMM4 are detected,
The address will be updated from the same initial value for each,
Therefore, the segment data corresponding to COMM1 to COMM4 is the same.

Each of the signals COMM1 to COMM4 has the same duty as each of the signals COM1 to COM32, but the terminals COMM1 to COMM4 of the common signal input terminal group 106 of the common signal selection circuit 105 are connected to the OR gate 107. Since I'm inputting, this OR gate 1
07, the duty of the signal of the terminal COMM of the common signal input terminal group 101 receiving the output of each terminal COMM1
To COMM4, that is, four times the sum of the duties of the signals.

That is, the terminal CO for character pattern in the common signal input terminal group 101 composed of 33 terminals in total.
While the duty of each of the M1 to COM32 (32) signals is 1/36, the fixed pattern terminal C
The duty of the OMM (1) signal is 4/36 = 1/9
And quadruple.

As a result, the character pattern dot LCD 10
Since the fixed pattern LCD 104 is driven at a duty four times as large as the duty at which the fixed pattern LCD 4 is driven, the area of the fixed pattern LCD 104 is smaller than the dot LC for the character pattern.
Even if the area is larger than D103, the same display power (luminance, contrast, etc.) can be exhibited.

The logical sum obtained by the OR gate 107 is
If all the terminals COMM1 to COMM4 are not used and a selection circuit is provided and an arbitrary number of the selection circuits are used, the duty for driving the fixed pattern can be changed. That is, in the above embodiment, four common timings for driving the same fixed pattern are provided in the entire common signal sweep period. However, if three or two common timings are taken in, the fixed pattern is driven. Can be reduced to ／ or の of the above embodiment.

In the above embodiment, the common signal input terminal group 101 is connected to the 32 common terminals CO for character patterns.
Although the description has been given of the combination of M1 to COM32 and one common terminal COMM for a fixed pattern, the present invention is not limited to this, and when two or more common terminals for a fixed pattern are used, the same applies. Of course, it can be applied.

In the above embodiment, the common signal selection circuit 105 is provided on the display panel 1 side.
It can also be built into the C2 side.

Further, in the above embodiment, the dot LCD 103 or the fixed pattern LCD 1 is used as a display element of the display panel 1.
Although the LCD is used as in the case of 04, LEDs and other display elements may be used.

Further, since the fixed pattern LCD 104 and the dot LCD 103 usually have a large area, the load of the common signal for the fixed pattern is larger than the load of the common signal for the character pattern. By making the driving duty relatively large,
The display power of the fixed pattern and the character pattern can be matched, but if this is generalized, when the duty of the common signal of the character pattern is 1 / n (n: a positive number exceeding 1), the fixed pattern The duty of the common signal
It may be 2m / n (m: a positive number exceeding 0).

[0034]

As described above, according to the present invention, an arbitrary dot pattern
Per line of common signal line for display element for turn
Of the display elements for the fixed pattern
Number of common signals per common signal line
The driving duty of the display element for the arbitrary dot pattern and the driving duty of the display element for the fixed pattern are different.
Thus , the visual unnaturalness due to the difference in display power between the two display elements can be eliminated. This can be realized by one display drive control IC because the display element of the fixed pattern only needs to be driven twice or more within one round of the display of the arbitrary dot pattern and the display of the fixed pattern.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a display panel of one embodiment of a display driving device of the present invention.

FIG. 2 is a block diagram of a display drive control IC according to the embodiment.

[Explanation of symbols]

1: display panel, 101: common signal input terminal group, 10
2: segment signal input terminal group, 103: dot LC
D, 104: fixed pattern LCD, 105: common signal selection circuit, 106: common signal input terminal group, 107: OR gate, 2: display drive control IC, 201: display address register, 202: display data memory, 203: common Address register, 204: character generator ROM, 205: fixed pattern common position detection unit, 2
06: fixed pattern data address register, 207:
Selector, 208: character generator RAM, 2
09: character generator ROM / RAM selection circuit, 210: selector, 211: parallel / serial conversion circuit, 212: shift register, 213: latch.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI G09G 3/36 G09G 3/36 (72) Inventor Kenichi Ogasawara 1-17-10 Nishiikebukuro, Toshima-ku, Tokyo (56) References JP-A-58-88786 (JP, A) JP-A-3-28883 (JP, A) JP-A-56-155990 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (2)

(57) [Claims] A plurality of common signal lines and a plurality of segments are provided.
Table for an arbitrary dot pattern at a predetermined intersection of the
Display element and the display element for the fixed pattern
A plurality of common signal to be repeated active and display data
By one or more selected inputs and <br/> plurality of segment signals to be simultaneously active in response to the data, for a display device and the fixed pattern for the <br/> any dot pattern
Of the display driving apparatus to drive the display device, together with the plurality of common signal is input, the fixed pattern
Of two or more of the above common signals for display elements for
A common signal selection circuit including a circuit for obtaining a logical sum;
The output of the monitor signal selection circuit is
And the plurality of segment signals are input to the plurality of segments.
Segment signal line and the dot pattern
Of common signal lines per row for display elements for
From the number of monitor signals, the display element for the fixed pattern
Number of common signals per common signal line
Display driving apparatus according to claim manner things become. 2. A multiple element for a display element for the fixed pattern.
The circuit that obtains the logical sum of the number of common signals is an OR gate.
Display driving device according to claim 1, characterized in that that.