JP3282114B2 - Clock tuning method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock tuning system for adjusting a clock skew between units such as a CPU unit constituting an information processing apparatus.

[0002]

2. Description of the Related Art In an information processing apparatus of this type, a CPU board or the like constituting a system is provided as a unit, and signals are transmitted and received between the units.

[0005] By the way, with the recent increase in the speed of electronic computer systems, there has been a demand for a shorter clock cycle, and the clock propagation delay between units using the same clock source occupies the clock cycle. And the propagation delay may hinder the clock cycle shortening. For this reason, it has become necessary to ensure the clock skew during operation of the device to a minimum value by performing highly accurate clock tuning.

In clock tuning for assuring clock skew of a device, a phase adjustment circuit is provided in a clock propagation path, and after assembling a unit or a device, a clock state is changed while checking a phase, and an optimum clock phase is determined. It is a technology to gain.

As a method of clock tuning, there is a method of correcting a manufacturing variation of a clock path by operating a phase adjustment circuit while measuring a delay time from a clock input to a test clock output in a single unit. Although the method can adjust the clock phase within a single unit, it cannot correct for manufacturing variations in clock paths between different units.

In order to reduce the clock skew between the units, there has been proposed a method of connecting a plurality of units in the apparatus and adjusting the clock phase using a circuit which actually operates.

FIG. 2 shows an example of this. FIG. 2 shows clock tuning between units A and B constituting a CPU board or the like. In FIG.
A and CiB are clocks input to the unit A and the unit B, respectively. The gate circuit (FF) functioning as a signal output circuit has an output terminal CO.
A1 to COA3 are provided, and individual clock adjusters (TA1 to TA3) are provided for each path of the gate circuit. Then, the unit clock adjustment unit (TA0) and the individual clock adjustment units (TA1 to TA3) of each path are adjusted so that a target clock phase can be obtained by the signal output circuit (FF). When the clock adjustment between the units A and B is performed in this system, the clock synchronization between the units is ensured while finely adjusting the unit clock adjustment unit 2 for each unit.

[0008]

However, when clock tuning is performed between a plurality of units using the above-described conventional technique, there is a high possibility that signal error detection will fail during tuning.

This will be specifically described with reference to FIG. Originally, ACK and BCK are synchronized, and the test signals (AIN1,...) Of the unit B are received corresponding to the test signals (AOUT1,...) From the unit A.

Here, the range indicated by "O" in the figure is a time range in which a clock error is not detected, that is, from the falling edge of the clock in the "earliest case" of the clock B supplied to the unit B, to the "latest time". The range in which the unit clock can be adjusted between the falling of the clock in the “case”, that is, in the unit B, is shown.

[0011] Ideally, the clock to be adjusted BCK
Is preferably located at the center of the error non-detection area (）). In the figure, a portion other than the error non-detection area, that is, a range where clock adjustment is not possible is defined as an error detection time (×), and when a falling edge of BCK is detected within this range, a clock shift is detected. It was determined that the error exceeded the allowable range.

As is apparent from FIG. 1, in the prior art, since the width of the error detection time "x" is narrow, the BKC
If the data is shifted in the early time direction, or shifted in the late time direction, the data that should normally arrive next is recognized as correct data, or the parity occurs as a result of an even number of errors. There has been a problem that an error form that has returned to a value indicating properness cannot be reliably detected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to adjust the clock phase of a transmission side or a reception side between a plurality of units by deliberately shifting them so that a unit on a reception side is adjusted. An object of the present invention is to reliably detect an error and realize highly accurate clock tuning.

[0014]

According to the present invention, as shown in FIG. 1 which is a principle diagram, first, an individual clock adjusting unit 3 for each unit is controlled by a main adjusting unit 6 so that the clock phases of the units are matched. After that, the individual clock adjusting unit 3 is controlled again to intentionally generate a different clock phase for each gate circuit.

[0015]

In the receiving unit, the clock tuning is executed based on the test signal received with the clock phase shifted intentionally. At this time, since the clock phase is shifted for each gate circuit, error detection is performed. The range of time (x) can be widened.

That is, by narrowing the width of the error non-detection time (（), the allowable range of the clock phase shift is also narrowed. According to the present invention, more precise clock tuning is enabled by pseudo-generating a clock phase different from the actual clock mode at the time of clock tuning.

[0017]

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows an embodiment of the present invention, which includes a unit A and a unit B which receive a clock supplied from the same clock source 1, and a main adjustment device 6 is provided between both units. ing.

As shown in FIG. 8, the unit clock adjusting unit 2 and the individual clock adjusting unit 3 have a configuration in which a fixed delay gate 7 is connected to a branch line 10 branched into a plurality of systems. The delay time can be adjusted by selecting which branch line 10 by the selector 8.

The gate circuit (FF) is constituted by a flip-flop latch, and opens and closes the gate circuit (FF) in synchronization with the clock signal, and sends and receives an inspection signal from the signal generation source 4.

In this embodiment, there are three gate circuits (FF) for transmission (FFA1 to FFA3, FFB4 to FFA4).
FFB6), three for reception (FFB1 to FF3)
B3, FFA4 to FFA6) are housed in both units A, B.

The signal generation source 4 has a function of adding a rule such as parity to the data. The inspection signal from the signal generation source 4 is synchronized with a clock by the gate circuit (FF) and the other unit is checked. Sent to

The receiving-side gate circuit (FFB1 to FFB)
3, FFA4 to FFA6) are connected to a detection unit (CB, CA). The detection unit (CB, CA) detects the received inspection signal and sends the result to the main adjustment device 6.

Here, as shown in FIG. 7, the main adjustment device 6 has a unit A tuning value holding unit 11 for recording a tuning result for each unit and a unit B tuning value holding unit 12. These values are the adjustment values of the individual clock adjustment unit 3 in each unit, and the values are used to perform tuning latch for each unit. Further, a system tuning setup value 13 is held as an initial value, and is used at the time of system installation or reset.

The determination calculation section 14 of the main adjustment device 6 includes the detection section 5 (CA) of the unit A and the detection section 5 of the unit B.
The error information from (CB) is input, and a predetermined calculation process is performed to output an adjustment value.

Each unit has a unit clock adjusting unit 2 for adjusting the unit clock, and each gate circuit (F
F) and an individual clock adjuster 3 for individually adjusting the clocks to the clock wiring are provided on the clock wiring.

In this embodiment, both the units A and B have the same configuration. In the figure, the main adjusting device 6 controls only the unit clock adjusting unit (TB0) of one unit B, but may control the unit clock adjusting unit (TA0) of the unit A. Good.

Next, a method of clock tuning between units in the above device configuration will be described. First, the main adjustment device 6 sends the individual unit adjustment units (TA1 to T
By controlling A6), the clock phase of each gate circuit is matched. Further, the clock B is similarly adjusted. This process completes the clock tuning for each unit.

Next, clock tuning between the units A and B is performed. First, in the unit A, the main adjustment device 6 adjusts these individual clock adjustment units (TA1 to TA3) for the three gate circuits (FFA1 to FFA3) on the transmitting side with the phase synchronization. Each clock is shifted by one bit. That is, as shown in FIG. 5, the first individual clock adjusters (TA1, TB
4) is a clock that reflects ACK as it is, the second individual clock adjuster (TA2, TB5) uses the ACK one bit earlier (ACK-E), and the third individual clock adjuster (TA3, TB6) Uses the ACK delayed by one bit (ACK-L).

Next, the individual clock adjusters (TB4 to TB6) for the three gate circuits (FFB4 to FFB6) on the transmitting side in the unit B as described above.
Is adjusted to generate a clock phase shifted one bit at a time.

At this time, the individual clock adjusting unit (TA)
The individual shift amounts of 1 to TA3, TB4 to TB6) are stored in the main adjustment device 6. By shifting the clock phase on the transmission side by one bit for each gate circuit in this manner, the range from the earliest clock fall to the latest clock fall is the range in which the data output of the test signal is prohibited. (The range indicated by the mesh pattern in the figure), and the range of the error detection time (×) is expanded in the detection unit (CB, CA).

That is, according to the present embodiment, by shifting the clock phase in each of the plurality of gate circuits (FFs) on the transmission side, it is possible to widen the range for reliably determining an error during clock tuning.
An erroneous determination due to a clock shift can be prevented.

In the main adjusting device 6, the unit clock adjusting unit (TB0) on the unit B side based on the outputs from both the detecting units (CB, CA) of the unit B and the unit A.
To adjust.

The unit clock adjusting section (TB)
At the stage where the adjustment of (0) is completed, the main adjustment device 6 controls the individual clock adjustment units (TA1 to TA3, TB4 to T4) on the transmission side.
B6) is restored, and the clock phases in the clocks A and B are made to coincide again.

That is, after clock tuning is completed, ACK-E is delayed by one bit and ACK-L is advanced by one bit. This allows ACK, ACK-L and A
CK-E matches, and clock tuning is completed.

As described above, according to the present embodiment, precise clock tuning is realized by transmitting the check signal in which the clock phase of the transmitting side is shifted only at the time of clock tuning.

After the completion of the clock tuning, the error non-detection time (（) is expanded again as shown in FIG. 4, so that there is no effect even if a slight shift of the clock occurs.

[0037]

Embodiment 2 FIG. 6 shows clock tuning in another embodiment of the present invention. In the first embodiment, the individual clock adjustment units (TA1 to TA3, TB4 to
The range of the error detection time (×) is expanded by shifting the clock of TB6) one bit at a time and transmitting the clock. In this embodiment, however, the individual clock adjustment unit (T
A1 to TA3, TB4 to TB6) are made to have the same clock, and the individual clock adjustment units (TB1 to T
B3, TA4 to TA6) are shifted by one bit and received.

That is, after controlling the individual clock adjusting units (TA1 to TA6, TB1 to TB6) on the transmitting side to match the clock phases on the transmitting side, the individual clock adjusting units (TB1 to TB3, TA4) on the receiving side are controlled. To TA6) to match the clock phase on the receiving side.

Next, the individual clock adjusters (TB1 to TB3, TA4 to TA6) on the receiving side are shifted one bit at a time. That is, as shown in FIG.
Individual clock adjustment units (TB1, TA
4) is adjusted to the position (E) where the clock phase is advanced by one bit, and the third individual clock adjusting unit (TB3, TA6)
Is adjusted to a position (L) one bit behind the clock N.

At this time, the individual clock adjusting unit (TB)
1 to TB3, TA4 to TA6) are stored in the main adjustment device 6. An error non-detection time (O), that is, from the clock falling when the clock N is advanced in the unit clock adjusting unit (TB0) to the clock falling when the clock N is delayed, that is, The allowable deviation range was set.

In the second embodiment as well, after the falling of the clock N in the later case, the time between the clock L and the clock E in the earlier case can be set as the error detection time (×). (×) can be widened, and precise error checking is possible.

That is, the main adjusting device 6 controls the unit clock adjusting unit (TB0) to adjust the clock BCK so as to be located substantially at the center of the error non-detection time (O).

After the adjustment of the unit clock adjusting section (TB0) is completed, the main adjusting device 6 returns the individual clock adjusting sections (TB1 to TB3, TA4 to TA6) to the original state.
The clock phases in the clocks A and B are made to coincide again.

[0044]

According to the present invention, an error is reliably detected by receiving a check signal by intentionally shifting the clock phase of the transmission side or the reception side between a plurality of units, so that errors can be detected between different units. Highly accurate clock tuning becomes possible.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an explanatory view showing a clock adjustment mechanism in a unit unit according to the related art.

FIG. 3 is a block diagram showing an embodiment of the present invention.

FIG. 4 is a timing chart of clock tuning in the related art.

FIG. 5 is a timing chart of clock tuning in the first embodiment of the present invention.

FIG. 6 is a timing chart of clock tuning in Embodiment 2 of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a main adjustment device according to an embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a clock adjustment unit according to the embodiment.

[Explanation of symbols]

1. Clock source 2. Unit clock adjustment unit (TA0, TB0) 3. Individual clock adjustment unit (TA1 to TA6, TB1 to TB1)
TB6) 4. Signal source 5. Detector (CA, CB) 6. Main adjustment device 7. Delay gate 8. Selector 10. Branch line 11. Unit A tuning value holding unit 12. Unit B tuning value holding unit 13. Setup value for system tuning 14. Judgment calculation unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-45039 (JP, A) JP-A-5-110550 (JP, A) JP-A-4-76610 (JP, A) JP-A-2- 197912 (JP, A) JP-A-61-276441 (JP, A) JP-A-59-105123 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/10 G06F 1 / 12 G06F 13/42 H04L 7/00

Claims (3)

(57) [Claims] 1. One unit (A) or another unit (B) is adjusted by transmitting and receiving a test signal from one unit (A) to another unit (B) using the same clock source (1). A clock tuning method, wherein a unit clock adjusting unit (2) for adjusting a delay time of a clock supplied from a clock source (1) for each unit.
An individual clock adjusting unit (3) for adjusting a clock for each gate circuit (FF) in the unit; and one unit (A) through the gate circuit (FF).
A signal generation source (4) for transmitting a test signal from the control unit to the other unit (B), a detection unit (5) for detecting the received test signal, and a signal generator based on a detection result of the detection unit (5). Or a main adjustment device (6) for controlling the other unit clock adjustment unit (2) or the individual clock adjustment unit (3), wherein the main adjustment device (6) is provided for each of the units, and a gate circuit in the unit. After the clock phases of the (FF) are once matched, the individual clock adjusting unit (3) is controlled so that the clock circuit intentionally becomes different for each of the gate circuits (FF), and the individual clock adjustment units (3) are received at different clock phases. A clock tuning system characterized in that the unit clock adjusting unit (2) of one unit (A) or the other unit (B) is adjusted and controlled based on the plurality of test signals. 2. The test signal is controlled by a main adjusting device (6) to control an individual clock adjuster (3) on the transmitting side in the unit, and is used for a fixed time between a plurality of gate circuits (FF) on the transmitting side. 2. The clock tuning method according to claim 1, wherein the clock tuning method is generated by shifting each of them. 3. The test signal is controlled by an individual clock adjuster (3) on the receiving side in the unit by a main adjuster (6), and is shifted by a fixed time between a plurality of gate circuits (FFs) on the receiving side. The clock tuning method according to claim 1, wherein