JP3710308B2 - Phase adjustment method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for adjusting the phase of a data transfer path when performing synchronous transfer of data between functional blocks, and is particularly suitable for synchronous transfer of data between functional blocks of devices such as parallel computers and data exchanges. The present invention relates to a phase adjustment method.
[0002]
[Prior art]
Conventionally, the path delay in the case of synchronously transferring data between functional blocks of an apparatus is obtained by replacing the transfer path (path) with an electric circuit modeled by using an electric circuit simulation, or the transfer path is determined for each part. The delay results obtained by separating and experimenting for each part were applied to each part, and the delay of the entire transfer path was obtained using a simplified special formula. Then, verify whether the path delay meets the designed time for the obtained path delay. If not, review the transfer path, change the circuit, and calculate the delay for the changed transfer path again. This was done by the above method. Further, the circuit change and the delay calculation were repeated until the delay calculation result of the transfer path satisfied the designed time.
[0003]
In order to mitigate such trial-and-error repetition, for example, in Japanese Patent Laid-Open No. 7-283819, a delay circuit is inserted in the transfer path and the transfer is actually performed, and a transfer error occurs according to the result. It has been shown that there is no delay set in the delay circuit. According to the present invention, in a transfer path for performing synchronous transfer between functional blocks in the apparatus, only a delay circuit is initially provided in the transfer path, and an adjuster sets a delay for the transfer path in the delay circuit. On the other hand, the system includes a control unit so that an appropriate delay does not have to be set in the delay circuit each time the adjuster connects a new system. The control unit automatically transmits a test packet for each transfer path to a plurality of transfer paths, and transfers the test packet correctly while changing the delay of the delay circuit provided in the transmission unit from a maximum value to a gradually decreasing direction. The obtained delay MAX and the delay MIN that can correctly transfer the test packet while changing the delay of the delay circuit provided in the transmission unit from the minimum value to the direction of gradually increasing are obtained, and the delay provided in the transmission unit for each transfer path is obtained. A function for setting a delay of (MAX + MIN) / 2 in the circuit, a function for storing a delay set for each transfer path, and a delay stored when the apparatus is started up for the delay for each transfer path It has a function to set in the circuit.
[0004]
For example, Japanese Patent Laid-Open No. 2-168754 discloses a circuit that compares the phases of two signals and detects the degree of the phase difference, and further relates to a circuit that corrects skew. For example, there is JP-A-63-305612.
[0005]
[Problems to be solved by the invention]
When designing a device that performs synchronous data transfer between functional blocks, it is important that the delay calculation result of the transfer path matches the actual delay. In synchronous transfer, transmission data hit by the transmission clock supplied to the transmission latch on the transmission side passes through the transfer path, and the transmission data is received at the timing hit by the reception clock supplied to the reception latch on the reception side. This is done by being taken into the latch. That is, synchronous transfer cannot be performed unless it is ensured that the delay of the transfer path does not collide with the reception clock of the reception latch.
[0006]
In general, it is very difficult to accurately calculate the delay from the transmission latch to the reception latch in advance, and even if it is obtained, the amount of calculation is enormous, and all transfer paths are calculated. It is impossible. Therefore, a large delay including an uncertain factor is assumed for each part in advance, and these are calculated using a simplified calculation formula so that a transfer error does not occur in an actual transfer path. However, assuming a large delay in advance means that the delay is unnecessarily large, which hinders optimal timing design.
[0007]
One of the points to be considered in the timing design is to ensure that the input data does not change in the time zone including the setup time and hold time specified in the latch in order to correctly capture the data in the reception latch. That is. Since the time zone during which input data should not be changed exists before and after the clock signal given to the latch, the delay of the transfer path is adjusted so that the data uncertain area of the transmission data does not come during that time zone. It is necessary to do (timing design). The other is the change in the delay of the transfer path due to the skew and jitter of the clock supplied to the latch, the variation in the manufacturing process, the electrical characteristics of the transfer path, the operating environment such as temperature, voltage and humidity. is there.
[0008]
The important thing in timing design is to design with sufficient margin in advance, taking into account the variation in delay due to the environment, so that the device can continue to operate normally in the assumed operating environment, that is, the operating margin Is designed to be large. Specifically, to increase the operation margin is to design the uncertain area of data at a point as far as possible from the time zone obtained by adding the setup time and hold time of the latch. If the operating margin is designed to be small, even if the uncertain area of the data is within the designed time zone, the operating environment shown above will be used if it is close to the time zone that includes the latch setup time and hold time. The data indeterminate area expands due to various noises caused by changes, moves to the larger delay side, or moves to the smaller side. Entering the time zone with time added will cause malfunction. Therefore, in order to prevent the transfer data from easily becoming an error due to noise in the environment and manufacturing variations due to mass production, the uncertain area of the data should be located at a point as far as possible from the time zone including the setup time and hold time. Designing delays is a challenge.
[0009]
On the other hand, in order to reduce development costs and product costs, common design and parts can be shared. Also, devices such as parallel computers often use the same parts because of their characteristics. Accordingly, there are a plurality of different transfer paths between parts of the same type, and timing design for these different transfer paths becomes a problem. In other words, variations and delays vary depending on the environment for each transfer path, but in the case of common design, the delay design is representative of the maximum variation of the variation, and it takes a lot of time to close the design, The problem is that an optimal delay design cannot be achieved. Therefore, it is one problem to provide a means for designing parts in common without designing a delay using the maximum variation of variations for each transfer path.
[0010]
In the prior art, since it is necessary to control each of a plurality of different transfer paths one by one, the control when there are many transfer paths is not considered, and there is a problem that the time for performing the adjustment becomes very long. . In addition, since no consideration is given to the spread of the uncertain area of the data, and it is expected that a transfer error will occur at any delay despite the fact that the delay to be checked is discrete, When the uncertain area is smaller than the variable unit of the delay circuit, a phenomenon that a transfer error does not occur in any delay occurs, resulting in a problem that an incorrect delay is set.
[0011]
Furthermore, in the prior art, the value to be set in the delay circuit is determined at the adjustment stage after the introduction of the device, and thereafter, the stored value is set to the delay circuit again when the device is initially set. For this reason, there has been a problem that it is impossible to cope with aging of each element and change of operating environment after the introduction of the device.
[0012]
The first object of the present invention is to simultaneously adjust a phase setting (delay setting) for each transfer path in a device having a plurality of different synchronous transfer paths in a transmission / reception unit of each transfer path. In a system that can change the configuration of a device in a scalable manner, such as a parallel computer by instructing to perform phase adjustment, that is, a device in which transfer paths increase in a scalable manner, the procedure for adjusting the phase can be changed without changing it. This is to complete all phase adjustments in the apparatus in the time required to adjust the phase of one transfer path.
[0013]
The second object of the present invention is to correctly detect the uncertain area even when the undetermined area of the data is smaller than the basic delay unit that can be changed by the variable delay circuit, and the operation margin is always maximized. The purpose is to be able to set the delay without error.
[0014]
Another object of the present invention is to make it possible to detect that there is some failure in the transfer path by a pattern in which received data is checked with individual delays that can be changed by the variable delay circuit.
[0015]
[Means for Solving the Problems]
  In the present invention,A phase adjustment pattern generation means is provided in the transmission section in the synchronous transfer path, and a variable delay means, a data check means in the reception section corresponding to the transmission section,Edge detection means,Phase control means is provided. The phase adjustment pattern means included in the transmission unit continuously generates phase adjustment pattern data that generates the maximum noise in the transmission path. From the phase adjustment pattern generation means by the data switching selector included in the transmission unit. When the generated phase adjustment pattern data is selected, the phase adjustment pattern data is transmitted to the receiving unit. The phase adjustment pattern data that has propagated through the transmission path connecting the transmission unit and the reception unit is delayed by the variable delay means of the reception unit, then received by the reception latch of the reception unit, and the data received by the reception latch is correct Whether or not the data check means.At the same time, the data delayed by the variable delay means of the receiving unit is judged by the edge detection means as to whether or not the data has been switched within the time corresponding to the delay unit that can be changed by the variable delay means. The phase control means sequentially changes the delay of the variable delay means, and uses the data check result for each delay or the data check result and the edge detection result to set a delay that maximizes the operating margin in the variable delay means.
[0016]
  Specifically, the phase control means includes a first storage means for storing a data check result of the data check means for each delay amount of the variable delay means, and an edge detection result of the edge detection means for each delay amount of the variable delay means. The second storage means for storing the data, the pattern that the data check result data for the total delay amount of the variable delay means can take, and the data that combines the data check result data and the edge detection result data for the total delay amount of the variable delay means And a table of predetermined values corresponding to the optimum delay amount of the variable delay means and a stored value pattern of the first storage means or the first storage means based on the stored value of the first storage means. Control theory for selecting a delay amount corresponding to a pattern obtained by combining both stored values of the second storage means and setting the delay amount in the variable delay means And means.
[0017]
  In the present invention,The phase control means uses the data check result and edge detection result for each delay to detect that there is some failure in the transfer path by comparing it with a pattern that is not normally possible, and reports it to the outside. It has a function.Specifically, in the table, whether there is a failure in the transmission path to correspond to the pattern that the data check result data can take and the pattern that the data check result data and the edge detection result data can take. An error bit indicating whether or not is added. The control logic means refers to the table and transfers the data according to the error bit of the entry corresponding to the pattern of the storage value of the first storage means or the pattern of the storage values of both the first storage means and the second storage means. Determine if the route is faulty.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
  An embodiment of the present invention will be described below with reference to the drawings.
  FIG. 1 illustrates the present invention.ExampleFIG. In FIG. 1, 1 indicates a transmission unit of one functional block, and 2 indicates a reception unit of the other functional block. The transmission unit 1 includes a selector 11, a transmission latch 12, and a phase adjustment pattern generation circuit 13. The reception unit 2 includes a variable delay circuit 21, a reception latch 22, a data check circuit 23, an edge detection circuit 24, and a phase control circuit 25. Reference numerals 101 to 108 are data lines, which are generally composed of a plurality of bits, but the transmission path between the functional blocks may be composed of 1 bit.
[0019]
The phase adjustment needs to be completed before the device synchronously transfers data between the function blocks. At that time, it is necessary to cause the transmission system to generate in advance the maximum noise generated when the apparatus uses the transmission system. The phase adjustment pattern generation circuit 13 is a circuit that automatically generates pattern data for generating maximum noise in the transmission system.
[0020]
Transmission system noise includes noise generated from a power supply for driving the transmission system and noise (crosstalk or the like) generated when a signal propagates through the transmission system. A special pattern is prepared in the phase adjustment pattern generation circuit 13 in order to generate the noise to the maximum. In this embodiment, as shown in FIG. 2, when a pattern in which one cycle “1” continues and then one cycle “0” continues for all bits of the path for phase adjustment is repeated for a predetermined time, A pattern in which 2 cycles “1” continues, a pattern in which 2 cycles “0” continues is repeated for a specified time, a pattern in which 3 cycles “1” continues, and a cycle in which 3 cycles “0” continues is repeated for a specified time. The same pattern is repeated from 1 to 3 cycles so that only the bits have the opposite pattern to the other bits. Then, the process is repeated until all the bits are opposite to each other, and then a pattern is repeatedly generated from all the bits 0 and 1 in one cycle. Although only data for one bit is shown in FIG. 2, the phase adjustment pattern generation circuit 13 continues to periodically generate such a pattern for each bit (including parity bits).
[0021]
During the phase adjustment operation, in the transmission unit 1, the selector 11 selects the data line 102, and outputs phase adjustment pattern data that generates maximum noise in the transmission system generated by the phase adjustment pattern generation circuit 13 to the data line 103. The transmission latch 12 takes in the phase adjustment pattern data on the data line 103 in synchronization with the transmission clock 113 and sends it to the data line 104. Switching of the selector 11 is instructed from an external system control unit or the like, but is omitted in FIG.
[0022]
In the receiving unit 2, the phase adjustment pattern data is received by the data line 105, passes through the variable delay circuit 21, and is output to the data line 106. As will be described later, in this embodiment, the variable delay circuit 21 can change the delay amount in eight stages. The reception latch 22 captures the phase adjustment pattern data on the data line 106 in synchronization with the reception clock 114 and outputs it to the data line 107. In synchronization with the reception clock 114, the data check circuit 23 always checks whether or not the phase adjustment pattern data has been correctly latched in the reception latch 22, in other words, whether or not the output of the reception latch 22 is correct data. ing. Further, the edge detection circuit 24 has a data uncertain area of the phase adjustment pattern data immediately before the reception latch 22 on the data line 106, that is, the data switching after passing through the variable delay circuit 21 falls within a predetermined range with reference to the reception clock 114. Detect if it exists. The phase control circuit 25 changes the delay amount of the variable delay circuit 21 through the control line 111 based on the data check result / edge detection result from the data check circuit 23 and the edge detection circuit 24 for each delay while sequentially changing the delay amount. The delay amount of the delay circuit 21 is controlled so as to maximize the margin.
[0023]
After the phase adjustment, the operation is switched to normal operation. In the normal operation, in the transmission unit 1, the selector 11 selects normal transmission data on the data line 101 in response to an instruction from the outside, and the transmission latch 12 captures the transmission data in synchronization with the transmission clock 113 and transfers it to the data line 104. Send it out. The reception unit 2 receives normal data from the transmission side through the data line 105, the variable delay circuit 21 delays the data by a predetermined amount, and the reception latch 22 captures the data in synchronization with the reception clock 114, to the data line 107. Output. Here, since the delay amount of the variable delay circuit 21 is set by the phase control circuit 25 so as to always keep the operation margin at the maximum, the data can be reliably latched in the reception latch 22.
[0024]
Hereinafter, the data check circuit 23, the edge detection circuit 24, and the phase control circuit 25 will be described in detail.
[0025]
FIG. 3 shows a configuration example of the data check circuit 23. The data check circuit 23 includes a check circuit 301 that checks data on the data line 107 and a check latch 302 that indicates that the result of inspection by the check circuit 301 is an error. The check circuit 301 is a parity check circuit, for example, but may be a circuit other than this. For example, a CRC circuit or a compare check circuit may be used. In other words, the check circuit 301 can determine whether or not the reception data is definitely latched in the reception latch 22 and, as a result, can be any circuit that can output whether the reception data is normal or abnormal. The check latch 302 captures the check result of the check circuit 301 in synchronization with the clock 114, and the information is reported to the phase control circuit 25 through the control line 109. The check latch 302 is reset by the phase control circuit 25 through the control line 110.
[0026]
  FIG. 4 shows a configuration example of the edge detection circuit 24. Reference numerals 401 to 407 denote latches, 408 denotes a fixed delay circuit, and 409 to 415 denote logic elements. When the data of the input data line 108 is captured by the latch 401 and the latch 403, if the switching of the capture clock and the input data overlaps, the outputs of the latch 401 and the latch 203 are in a metastable state. It is known that this metastable state is eliminated in a certain time due to the characteristics of the latch. In this embodiment, the metastable state is removed by re-acquiring with the latch 402 and the latch 404 after one clock. latch405,406The signal on the input data line 108 is latched401And the value latched by the latch 403 after passing through the fixed delay circuit 408, as a result of comparing the value latched in step 408. The latch 407 is a latch that holds “1” when the comparison results are different. That is, when the latch 407 is “1”, the data between the clock position where the signal of the input data line 108 is supplied to the edge detection circuit 24 and the position advanced by the delay of the fixed delay circuit 408 from the clock. This indicates that there is an indeterminate area. Information of the latch 407 is reported to the phase control circuit 25 through the control line 112.
[0027]
FIG. 5 shows a configuration example of the variable delay circuit 21. Reference numerals 501 to 507 denote delay unit circuits having a certain delay amount (delay) Δβ. Reference numerals 511 to 517 denote selectors for switching delays, which are controlled via the decoder 520 by a control signal given from the phase control circuit 25 through the control line 111. The selectors 511 to 517 select the signal from the delay unit circuit (Δβ) when the select signal from the decoder 520 is not valid, and select the received data on the data line 105 when the select signal from the decoder 520 is valid. To do. For example, if the value of the control signal on the control line 111 is “2”, only the selector 515 selects the received data on the data line 105, and the other selectors 511, 512, 513, 514, 516, 517 are delay units. The signals from the circuits 501, 502, 503, 504, 506 and 507 are selected. Accordingly, since the received data on the data line 105 passes through the selector 515 and passes through the delay unit circuit 506, the selector 516, the delay unit circuit 507, and the selector 517, the delay in the variable delay circuit 21 is two times Δβ. It becomes the value which added 3 pieces. Thus, according to the value of the control signal on the control line 111, the number of delays Δβ until the received data on the data line 105 passes to the data line 106 is determined, and the delay of the variable delay circuit 21 is determined. In order to suppress delay variation due to the value of the control signal on the control line 111, the same selector as the selector 511 is added to the entrance of the head delay unit circuit 501, and a new 7 signal is extracted from the decoder 520, and the select signal It is also possible to connect the selector to which the line is added in the same manner as the selectors 511 to 517.
[0028]
FIG. 6 shows a configuration example of the phase control circuit 25. The control logic unit 601 is a logic unit that controls the overall operation of the phase control circuit 25. The control logic unit 601 is connected to an external system control unit or the like via a system control line or a system report line, but is omitted in FIG. SQBSY 602 is a flip-flop that indicates whether or not the phase control circuit 25 is performing a phase adjustment operation, and serves to prevent malfunction caused by double activation of the phase control circuit. PDATA 603 is a register for storing the data check result in the data check circuit 23 for each delay unit, and CDATA 604 is a register for storing the edge detection result in the edge detection circuit 24 for each delay unit. In this embodiment, the delay can be changed in 8 stages in the variable delay circuit 21, and the values of PDATA 603 and CDATA 604 are correspondingly configured with 8 bits in each register. The OR circuit 605 is a circuit that logically sums the values of PDATA 603 and CDATA 604 in units of bits, and the selector 606 is a circuit that selects either the output of the PDATA 603 or the output of the OR circuit 605 with the control signal 608 from the control logic unit 601, RDATA 607 Is a register for storing the output of the selector 606. The register of RDATA 607 is 8 bits like PDATA 603 and CDATA 604.
[0029]
The set value for the delay variable delay circuit 21 having the maximum operating margin is obtained in advance from a combination of the values of PDATA 603 and CDATA 604. In this embodiment, the table (1) 610 and the table (2) 620 of the list based on the calculation result are created and stored in the phase control circuit 25. FIG. 9 is an example of the table (1) 610. Yes, whether or not to use the CDATA value from the PDATA value is shown in the column of presence / absence of use of the edge detection result. “1” indicates that the value of CDATA 604 is used, and “0” indicates that the value of CDATA 604 is not used. The control logic unit 601 controls the operation of the selector 606 by a control signal 608 with reference to the edge detection result use determination table (1) 610. FIG. 10 is an example of Table (2) 620 and shows a conversion table for obtaining the delay of the variable delay circuit 21 from the value of RDATA 607. However, at the same time as the delay that maximizes the operation margin is defined from the RDATA 607 value, the RDATA 607 value that cannot be a normal transmission path is also defined in the table (2) 620 to indicate that there is some failure in the transmission path. Also defines an error field. However, if there is a delay in which transmission data can be normally received even if there is some failure in the transmission path, a setting value is defined so that the operation margin is maximized.
[0030]
Next, the operation of the phase control circuit 25 shown in FIG. 6 will be described with reference to FIGS. FIG. 7 is an overall operation flow of the control logic unit 601 in the phase control circuit 25. If there is an instruction to perform phase adjustment from the outside, it is first determined whether or not SQBSY 602 is “1” (step 702). SQBSY 602 of “1” indicates that the phase control circuit 25 is in the middle of phase adjustment operation. In this case, the phase adjustment request is ignored and the phase control circuit 25 is activated twice. Prevents malfunction caused by being applied. When SQBSY 602 is “0”, that is, when the phase adjustment operation is not performed by the phase control circuit 25, the phase adjustment request is accepted and SQBSY 602 is set to “1” at the same time as entering the phase adjustment operation (step 703). ). Next, initialization for phase control is performed (steps 704, 705, and 706). First, the values of the PDATA register 603 and the CDATA register 604 are set to “0” (step 704). The symbol “*” in FIG. 7 indicates the array element numbers (0 to 7) of the registers 603 and 604 and also indicates the value set in the variable delay circuit 21. Next, the variable i is set to “0” (step 705), and the delay is set to “0” in the variable delay circuit 21 (step 706). This completes the initialization for phase control, and thereafter the following operation is repeated for each delay set in the variable delay circuit 21.
[0031]
First, the check latch 302 provided in the data check circuit 23 is cleared to “0” through the control line 110 (step 707). Then, a determination time for continuously checking the received data by the data check circuit 23 and the edge detection circuit 24 is set (step 708). The determination time is set as a unit of time during which one cycle of various phase adjustment patterns generated by the phase adjustment pattern generation circuit 13 in the transmitter 1. The inspection is started from an arbitrary position of the phase adjustment pattern data. However, the determination time to be set may be able to detect noise that changes over a longer time as the determination time becomes larger. In the corresponding delay for the time set in step 708, the check result of the received data in the data check circuit 23 is fetched from the control line 109 and stored in the PDATA (i) 603, and at the same time, the edge check of the received data in the edge detection circuit 24 The result is fetched from the control line 112 and stored in CDATA (i) 604 (steps 709 and 710). After the determination time has elapsed, “1” is added to the variable i in order to check data for the next delay (step 711), and a delay corresponding to i is set in the variable delay circuit 21 (step 712). If the changed variable i is equal to or smaller than “8” (step 713), the process returns to step 707, and the received data for the delay corresponding to the variable i is checked again and stored in PDATA (i) 603 and CDATA (i) 604. To do. If the changed variable i is “8” or more, it means that the check of received data for all delays that can be changed by the variable delay circuit 21 is completed, and PDATA
The delay with the maximum operation margin is determined from the values of (*) 603 and / or CDATA (*) 604, and the delay is set for the variable delay circuit 21 (step 714).
[0032]
As described above, since the phase adjustment operation is completed, SQSY 602 is set to “0” to notify the outside that the phase adjustment operation is completed (step 715). The timing for performing the phase adjustment operation is of course performed in the process of starting up the device, but in order to always keep the operation margin at the maximum, even during operation of the device, it is usually in the transfer path. Phase adjustment is performed in anticipation of no data.
[0033]
FIG. 8 is an operation flow for explaining step 714 shown in FIG. 7 in detail. When the check results for all delays that can be changed by the variable delay circuit 21 are stored in PDATA (*) 603 and CDATA (*) 604, first, using the values of PDATA (*) 603, the table of FIG. (1) The presence / absence of use of the edge detection result is read from 610 (step 802). As a result of reading, when the presence / absence of use of edge detection is “1”, the OR circuit 605 selects the operation result obtained by logically summing PDATA (*) 603 and CDATA (*) 604 for each bit. RDATA (*) 607 is set. Whether or not edge detection is used
When it is “0”, the selector 608 selects the value of PDATA (*) 603 with the selector 608 and sets it to RDATA (*) 607 as it is (steps 803, 804, 805). Next, using the value of RDATA (*) 607, the delay amount and the error are read from the table (2) 620 in FIG. 10 (step 806). Then, the read delay amount is set in the variable delay circuit 21 through the control line 111 (step 807). If the read error value is “1”, an error is indicated to the phase control circuit 25. Then, step 714 is completed (step 809). If the read error value is “0”, step 714 is completed as it is.
[0034]
For example, when the value of PDATA (*) 603 is “00000011” and the value of CDATA (*) 604 is “00001111”, the value of the 904th row of table (1) 610 and the value of PDATA (*) 603 in FIG. Therefore, the presence / absence of use of edge detection can be read as “1” from the table of FIG. Since the presence / absence of use of edge detection is “1”, PDATA (*) 603 and CDATA (*) 604 are logically ORed for each bit, and RDATA (*) 607 is “00001111”. This RDATA
(*) The value of 607 matches the 1005th line of Table (2) 620 in FIG. Therefore, the control logic unit 601 of the phase control circuit 25 sets the delay amount value “1” read from the row 1005 in the table of FIG. In this case, since the error column in the 1005th line of the table of FIG. 10 is “0”, no error is set in the phase control circuit 25.
[0035]
Next, an example of a waveform in the phase adjustment operation of this embodiment will be described with reference to FIG. The waveform output from the transmission unit 1 is switched in synchronization with the transmission clock 113, so that the data indeterminate region is generated like the waveform of the transmission data on the data line 104. The transmission data is subjected to various noises while reaching the receiving unit 2 through the transfer path, and the range of data uncertainty is wider than the transmission data of the data line 104 like the reception data of the data line 105. The reception data on the data line 105 passes through the variable delay circuit 21 to become a waveform 106 and is latched in the reception latch 22 by the reception clock 114. Here, the waveform of the received data on the data line 106 changes like the waveforms of delays 0 to 7 in the variable delay circuit 21. As for the relative relationship (skew) between the reception clock 114 and the transmission clock, the phase is constant although there is jitter. One purpose of this phase adjustment is to maximize the operating margin. This is equivalent to bringing the reception clock 114 in the middle of the data deterministic area avoiding data indeterminacy of the reception data of the data line 106 in the relationship between the reception clock 114 and the reception data of the data line 106. is there. In other words, the center of the data fixed area where the data uncertain of the received data on the data line 106 is avoided is aligned with the reception clock 114. In other words, maximizing the operating margin delays either the reception data on the data line 106 or the reception clock 114, and the data uncertain area of the reception data on the data line 106 matches the latch point of the reception clock 114. In other words, the latch point of the reception clock 114 is in the middle of the data fixed area avoiding the data undefined area. In the example of the waveform in FIG. 11, when the value of PDATA (*) is determined as “11000001” and the value of CDATA (*) is determined as “11000011”, the delay amount “4” has the maximum operating margin. It can be easily understood that the value is obtained.
[0036]
Next, the delay unit circuits 50 to 507 (Δβ) and the total delay mounted on the variable delay circuit 21 shown in FIG. 5 and the delay of the fixed delay circuit 408 mounted on the edge detection circuit 24 shown in FIG. 4 will be described. The minimum total delay required for the variable delay circuit 21 is generated by transmitting the transmission data of the data line 104 from the latch 12 of the transmission unit 1 in synchronization with the transmission clock 113, and receiving data of the data line 106 by the transmission clock 113. Therefore, it is only necessary to bring the phase of the received data in the middle of the data deterministic area avoiding data indeterminacy of the received data on the data line 106. Good things are easy to understand. The delay of the delay unit Δβ is a value obtained by dividing the total delay into n equal parts. As the delay of the delay unit Δβ is smaller, it can be set to the middle of the data deterministic area where data uncertainties are avoided, that is, a delay with the largest operation margin, but the logic scale of the variable delay circuit 21 becomes larger. As a result, it becomes difficult to mount the LSI on the LSI and the logic for implementing the function to be performed cannot be entered. Therefore, considering the balance of the operation margin of the entire apparatus, that is, only the transfer path protrudes and is wasted. Therefore, it is necessary to determine the value of the delay unit Δβ so that the operation margin does not increase.
[0037]
Next, when the delay unit Δβ is determined, the delay of the fixed delay circuit 408 in the edge detection circuit 24 is determined. The edge detection circuit 24 is a means provided so as to compensate for the result of discrete check by the data check circuit 23. That is, since the data check circuit 23 checks the received data only at points with respect to the stepwise delay that can be set by the variable delay circuit 21, it does not check the received data between points, that is, by the delay unit Δβ. . The purpose of the edge detection circuit 24 is to check the area where the received data is not checked. Therefore, it can be easily understood that the fixed delay circuit 408 may have at least the delay unit Δβ. However, as can be seen from FIG. 11, when the delay of the fixed delay circuit 408 increases, the area detected by the edge detection circuit 24 indicated by the right-down diagonal line increases, so that the data indeterminate area looks large, As a result, the delay set in the variable delay circuit 21 is set to the earlier side of the delay from the middle of the data determination area avoiding data uncertainties, and the operation margin is reduced.
[0038]
Next, FIG. 12 shows an example of a system to which the phase adjustment method of the present invention is applied. Reference numeral 1201 denotes a system control unit that controls the phase adjustment of all functional blocks, and reference numerals 1210, 1211, and 1212 denote functional blocks A, B, and C. There are four transfer paths between the functional block (A) 1210 and the functional block (B) 1211. In this example, there are two transfer paths between the functional block (B) 1211 and the functional book (C) 1212. It has a transfer path. Each transfer path includes a transmitter 1 and a receiver 2. FIG. 1 shows a set of these. Reference numerals 1220, 1221, and 1222 denote system control lines for controlling the internal circuits of the transmission unit 1 and the reception unit 2 in the functional blocks (A) 1210, (B) 1211, and (C) 1212 from the system control unit 1201. Yes, 1230, 1231 and 1232 are system report lines reported from the phase control circuit 25 of the receiving unit 2 in each of the functional blocks (A) 1210, (B) 1211 and (C) 1212.
[0039]
Next, an example of a procedure for operating the phase adjustment for the transfer path indicated by 1240 between the functional block (A) 1210 and the functional block (B) 1211 in the system of FIG. 12 will be described with reference to FIG. The system control unit 1201 sets a determination time for continuing to determine received data to the receiving side of the transfer path 1240 that is going to perform phase adjustment by using the system control line 1221 (step 1302). Further, the system control line 1220 switches the selector on the transmission side corresponding to the reception side of the transfer path 1240 to the direction in which the phase adjustment pattern data from the phase adjustment pattern generation circuit is output (step 1303). Then, it instructs the phase control circuit on the phase adjustment reception side of the transfer path 1240 to perform a phase adjustment operation (step 1304). Thereafter, the system control unit 1201 monitors the SQBSY read from the phase control circuit on the receiving side via the report line 1131 in order to know that the phase adjustment operation is completed, and the SQBSY signal becomes “0”. When the error signal is confirmed, the error signal is read from the phase control circuit on the receiving side (step 1306), and if the error signal is “1”, error information determined in advance from the receiving side is collected. The error information is reported to the outside (step 1307). After the error signal is “0” or error information is collected, the system control unit 1201 switches the selector corresponding to the transmission side of the transfer path 1240 to the data path side normally used by the system control line 1220 (step 1308).
[0040]
The series of procedures shown in FIG. 13 can be performed independently by a phase adjustment circuit provided for each transmission path. Further, since there is no different setting for each phase adjustment circuit, these series of procedures can be performed simultaneously by the system control unit 12 that controls the entire system.
[0041]
In the above, one embodiment of the present invention has been described. However, when there are a plurality of transmission units in the same LSI, each transmission unit does not include a phase adjustment pattern generation circuit, depending on the implementation of the LSI. Thus, a plurality of transmission units may share one phase adjustment pattern generation circuit.
[0042]
Also, the transmission path may be composed of 1 bit or a plurality of bits, and the variable delay circuit may change the delay individually for each bit or may change the delay for each of the plurality of bits at the same time. Good. If the delay for each bit is changed at the same time, the noise of each bit appears to be superimposed due to variations in the transmission path of each bit, so that the variable delay circuit can change the delay individually for each bit as much as possible. By making it possible, it is possible to set a fine delay so that the operation margin becomes larger.
[0043]
【The invention's effect】
According to the present invention, no complicated delay calculation is required for each transfer path, and the optimum delay for the transfer path is automatically selected according to the actual transfer result, so that all delay calculations for the transfer path are required. In addition, LSIs can be easily designed in common and the number of LSIs to be designed can be reduced, which has the effect of reducing LSI design costs and manufacturing costs.
[0044]
In addition, since the phase is automatically adjusted in the installation environment after assembling the delay variation due to the operating environment of each device and the delay variation generated in the manufacturing process for each component, the maximum operation of the device for each device. There is an effect that a margin can be obtained automatically.
[0045]
In addition, since the present invention includes an edge detection circuit, even if the data uncertainty region becomes smaller than the checkpoint interval by the delay unit of the variable delay circuit, the data uncertainty region is not lost, so that the maximum operation is achieved. There is an effect that it is possible to set a delay for obtaining a margin.
[0046]
In addition, the present invention has an effect that it is possible to notify the outside that there is some kind of failure in the transfer path by finding a pattern that cannot be designed from the result of checking for each delay unit of the variable delay circuit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is an example of phase adjustment pattern data generated by a phase adjustment pattern generation circuit.
FIG. 3 is an example of a data check circuit in FIG. 1;
FIG. 4 is an example of an edge detection circuit.
FIG. 5 is an example of a variable delay circuit.
FIG. 6 is an example of a phase control circuit.
FIG. 7 is an operation flowchart of the phase control circuit.
FIG. 8 is a detailed operation flowchart of processing for determining the delay amount of the flow of FIG. 7;
FIG. 9 is an example of an edge detection result use determination table;
FIG. 10 is an example of a conversion table for determining a delay amount.
FIG. 11 is an example of a waveform in the phase adjustment operation of the embodiment.
FIG. 12 shows an example of a system configuration to which the present invention is applied.
13 is a flowchart of phase adjustment operation by the system of FIG.
[Explanation of symbols]
1 Transmitter
2 receiver
11 Selector
12 Transmit latch
13 Phase adjustment pattern generation circuit
21 Variable delay circuit
22 Receive latch
23 Data check circuit
24 Edge detection circuit
25 Phase control circuit
101-108 data lines
109 to 112 Control line
113, 114 clock
1201 System control unit
1210, 1211, 1212 functional blocks
1220, 1221, 1222 System control line
1230, 1231, 1232 System report line

Claims (2)

A phase adjustment method for synchronous transfer of data between functional blocks in which a transmitter and a receiver are connected through a data transfer path,
The transmitter has phase adjustment pattern generation means for generating phase adjustment pattern data for adjusting the phase,
The receiving unit arbitrarily delays received data, data check means for checking whether or not the phase adjustment pattern data that has passed through the variable delay means can be correctly latched in the reception latch by the reception clock, and the variable Whether or not there is a data uncertain area within a predetermined range from the reception clock given to the reception latch based on the phase adjustment pattern data immediately before being latched by the reception latch after passing through the delay means The edge detection means for detecting the edge of the data, and the data check result of the data check means and the edge detection result of the edge detection means are sequentially input while changing the delay amount of the variable delay means, and the data check result or Based on both the data check result and the edge detection result, the delay amount of the variable delay means is minimized. And a phase control means for setting the,
The phase control means stores a first storage means for storing a data check result of the data check means for each delay amount of the variable delay means, and an edge detection result of the edge detection means for each delay amount of the variable delay means. The second storage means to store, the data check result data for the total delay amount of the variable delay means, and the data check result data and the edge detection result data for the total delay amount of the variable delay means are combined. Based on a table that predetermines the correspondence between patterns that data can take and the optimum delay amount of the variable delay means, and a stored value pattern of the first storage means, based on a stored value of the first storage means, or Select the delay amount corresponding to the pattern that combines the stored values of both the first storage means and the second storage means Comprising a control logic means for setting the variable delay means Te,
A phase adjustment method characterized by this. The phase adjustment method according to claim 1,
The table shows an error indicating whether or not there is a failure in a transmission path in correspondence with a pattern that the data check result data can take and a pattern that the data check result data and the edge detection result data can take. A bit further,
The control logic means refers to the table, and an error bit of an entry corresponding to a pattern of the stored value of the first storage means or a pattern obtained by combining the stored values of both the first storage means and the second storage means To determine whether there is a failure in the data transfer path .

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