JP3277448B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of driving the same, and more particularly, to a liquid crystal display device in which an active matrix type liquid crystal display device has improved surface roughness due to a selection pulse (gate pulse) jumping into a pixel. The present invention relates to a display device and a driving method thereof.

[0002]

2. Description of the Related Art A conventional active matrix type liquid crystal display device used for a camera-integrated VTR, a liquid crystal projector and the like will be described with reference to FIGS. First, the configuration of a conventional liquid crystal display device will be described with reference to FIG. FIG. 3 is a block diagram showing a main part of a conventional liquid crystal display device.

[0003] This liquid crystal display device is configured by interpolating an H shift register 1, a V shift register 2, a buffer circuit 3, and a pixel portion. The H shift register 1 receives various control signals and is connected to a horizontal switch 4n. The horizontal switch 4n has an electrode pad 4a.
, R, G, and B video signals (for example, in the case of a color liquid crystal panel) are input. A data line 5 is connected to the horizontal switch 4n, and a video signal is input to each pixel unit via the data line 5.

On the other hand, various control signals are input to the V shift register 2, and a gate line 6 in the row direction is connected via a buffer circuit 3. Buffer circuit 3
To the power supply VDD via the electrode pad 3a. The data lines 5 and the gate lines 6 are arranged in a matrix, and a thin film transistor (Thin Film Transistor: hereinafter) as a pixel portion is provided at the intersection.
A liquid crystal cell LC and a storage capacitor Cs are provided, and a common line (common electrode) 8 is formed via the liquid crystal cell LC and the storage capacitor Cs.

Next, an example of a conventional driving method of a liquid crystal display device will be described with reference to FIGS. FIG. 4 is a diagram showing a driving method of a conventional liquid crystal display device.
(A) is a timing chart for writing a “low-level video signal”, and (b) is a timing chart for writing a “high-level video signal”.

In FIG. 3 and FIG. 4A, R, G, and B video signals, various control signals, and a power supply voltage are received from an external IC and a power supply circuit (not shown), and the H shift register 1 and the V shift Supply to register 2. As an example, a gate pulse as shown in FIG. 4A is applied to a predetermined gate line 6, and an n-th horizontal switch 4n is switched by a switching pulse as shown in FIG. Emits. Then, the video signal Vsig applied to the data line 5 changes, for example, from the held “high level” to “low level” and holds the “low level video signal” VL.
Thereafter, the “low-level video signal” VL is applied to the gate-source capacitance C of the TFT 7 at the moment when the gate pulse is turned off.
Under the influence of capacitive coupling due to gs or the like, the signal of ΔVL sinks.

Similarly, when writing a “high-level video signal”, as an example, a predetermined gate line is
When a gate pulse as shown in (b) is applied and the n-th horizontal switch 4n emits a switching pulse to write a “high-level video signal”, the video signal Vsig applied to the data line 5 is held, for example. Changed from “low level” to “high level”
“High-level video signal” VH is held. This VH
Is affected by the capacitance coupling at the moment when the gate pulse is turned off, and the signal of .DELTA.VH will sink. However, ΔVH is a value smaller than ΔVL for the reason described later. These displacement voltages ΔVL and ΔVH can be expressed by the following equations.

That is, ΔVL = (Cgs / Cgs + Cs) · ΔL ΔVH = (Cgs / Cgs + Cs) · ΔH where ΔL = VDD−VL−Vth ΔH = VDD−VH−Vth Cgs: TFT gate-source capacitance Cs: Retention capacity VDD: power supply VL: low-level video signal (approximately 4 V) VH: high-level video signal (approximately 8 V) Vth: threshold level (approximately 1 V)

The reason why ΔVH becomes smaller than ΔVL will be described with reference to FIG. FIG. 5 is a waveform diagram showing a write gate pulse and a video signal level.

In FIG. 5, when the amplitude of the gate pulse is between the power supply VDD (13.5 V) and the ground terminal VSS, the change in potential until the "low-level video signal" VL is reached after the application of the switching pulse is calculated. Then, from the equation, ΔL = 13.5-4-1 = 8.5V.

Similarly, when the change in the potential until reaching the “high-level video signal” VH is calculated, ΔH =
It is expressed as 13.5-8-1 = 4.5V. By substituting these numerical values into the equations to obtain the deviation voltages ΔVL and ΔVH, the deviation voltage ΔVL on the low level side becomes a larger value. That is, it can be seen that the write operation point differs between the “high-level video signal” VH and the “low-level video signal” VL. In particular, the large deviation voltage ΔVL jumps into the pixel portion, and the variation in ΔVL affects the image displayed on the pixel portion. As a specific example, Δ
Since the video signal level changes due to the variation in VL, there is a problem that the uniformity is deteriorated, which is called “surface roughness defect”. The following measures have been taken to improve this uniformity.

Next, with reference to FIGS. 6 and 7, a description will be given of a conventional measure for improving uniformity. FIG. 6 is a block diagram showing an example of conventional measures for improving uniformity, and FIG. 7 is a timing chart thereof.

As a measure for improving the uniformity of the prior art, a power supply V
The control transistor 10 is added from DD via the first divided resistors R1 and R2. A uniformity improvement pulse is input to the control transistor 10 via the input terminal 9. It is configured so as to be taken out as a new power supply VDD0 from the divided portion of the first divided resistors R1 and R2.

A buffer circuit 3 of a conventional liquid crystal display device
The subsequent configuration includes an electrode pad 4a to which a video signal is input, a horizontal switch 4n connected to an H shift register (not shown), and a data line 5 connected to the horizontal switch 4n. Gate lines 6 are connected to the buffer circuit 3, and the data lines 5 and the gate lines 6 are arranged in a matrix. At the intersection of the data line 5 and the gate line 6, a TFT as a pixel portion is provided.
7. A liquid crystal cell LC and a storage capacitor Cs are provided, and a common line 8 is formed via the liquid crystal cell LC and the storage capacitor Cs. In the following description, description of the liquid crystal cell LC is omitted.

As an operation of the conventional technique for improving uniformity having such a configuration, a uniformity improving pulse (denoted as “CLR” in the figure) as shown in FIG. 7 is applied from the input terminal 9. The newly connected power supply VDD0 is
In the "low level" period of the uniformity improvement pulse, a normal power supply voltage is supplied via the dividing resistor R1 as shown in the figure. However, in the "high level" period of the uniformity improvement pulse, the control transistor 10 is turned on. As a result, a voltage drop A divided by the first divided resistors R1 and R2 set in advance occurs. Therefore, the gate pulses G1, G2, G3 generated by the buffer circuit 3 connected to the power supply VDD0 generate pulses including the voltage drop A.

As described above, in the conventional measures for improving the uniformity, the deterioration of the uniformity such as "surface roughness failure" is reduced by a method of lowering the voltage at the timing when the gate pulse of the V shift register is turned "off". I have. However, in this method, since the ratios of the bias voltages remain unchanged without change, there is a possibility that the uniformity may be damaged again due to variations in the manufacturing process and the like.

[0017]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to improve the uniformity by lowering the voltage at the timing when the gate pulse of the V shift register is turned "off". It is an object of the present invention to provide a liquid crystal display device and a driving method thereof, in which a variation in the uniformity improvement measure of the related art is avoided and the effect of further improving the uniformity is enhanced.

[0018]

In order to solve the above-mentioned problems of the prior art, the following measures have been taken. That is, a buffer circuit to which a plurality of gate lines arranged in a row are connected, a V shift register to which a buffer circuit is connected, a horizontal switch to which a plurality of data lines arranged in a column are connected,
In a liquid crystal display device including an H shift register to which a horizontal switch is connected, and a pixel portion provided at each intersection of a gate line and a data line, a power supply terminal of a V shift register, a buffer circuit, or both, is connected to a predetermined position. And connected to a division of the first divisional resistor controlled by the uniformity improvement pulse via a control transistor to which the uniformity improvement pulse is input. Further, the power supply terminal of the first divided resistor is connected to a divided portion of the second divided resistor controlled by the polarity inversion pulse via a control transistor having a predetermined division ratio and receiving the polarity inversion pulse. The power supply terminal of the second divided resistor is connected to a power supply.

In the driving method of the liquid crystal display device having such a configuration, the gate pulse generated by the buffer circuit connected to the power supply terminal of the first divided resistor is controlled by the uniformity improvement pulse to cause a voltage drop. The power supply terminal of the divided resistor 2 is controlled by a polarity inversion pulse. Then, when writing a low-level video signal, the above problem was solved by reducing the amplitude of the gate pulse generated by the buffer circuit to a predetermined value.

Preferably, the gate pulse generated by the buffer circuit is a jump pulse caused by capacitive coupling when writing low-level and high-level video signals.
It is controlled so as to be the same as the deviation voltage which is the only level .

According to the liquid crystal display device and the method of driving the same according to the present invention, with such a configuration, the shift voltage at the time of writing the low-level video signal and the high-level video signal is controlled to be the same. Even in the case where the variation occurs, the influence of the bias voltage does not reach the pixel portion, and it is possible to avoid the deterioration of the uniformity such as "surface roughness defect".

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a liquid crystal display device and a driving method thereof according to the present invention will be described with reference to FIGS. Note that portions common to those described in the related art are denoted by the same reference numerals, and description thereof is partially omitted.

First, the configuration of the liquid crystal display device of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a main part of the liquid crystal display device of the present invention.

The liquid crystal display device of the present invention, in addition to the above-described conventional measures for improving uniformity, further comprises a control transistor as a supplementary circuit 100 of the present invention from the power supply VDD via the second divided resistors R11 and R12. 103 was added. An inverter circuit 102 is connected to the control transistor 103 via an input terminal 101, and a polarity inversion pulse (abbreviated as “FRP” in the figure) is input to the input terminal 101. Then, a new power supply VD of the first divided resistors R1 and R2 is supplied from the divided portion of the second divided resistors R11 and R12.
It was configured to take out as D1.

The configuration after the additional circuit 100 of the present invention includes an electrode pad 4a to which a video signal is input, a horizontal switch 4n connected to an H shift register (not shown),
It is constituted by a data line 5 connected to the horizontal switch 4n. The buffer circuit 3 has a gate line 6
Are connected, and the data lines 5 and the gate lines 6 are arranged in a matrix. A TFT 7 serving as a pixel portion, a liquid crystal cell LC (not shown), and a storage capacitor Cs are provided at an intersection of the data line 5 and the gate line 6, and a common line 8 is formed via the liquid crystal cell LC and the storage capacitor Cs. Have been.

Next, the operation of the method for driving the liquid crystal display device of the present invention will be described with reference to FIGS. FIG. 2 is a timing chart showing a driving method of the liquid crystal display device of the present invention.

As a driving method of the liquid crystal display device of the present invention, a uniformity improvement pulse (CLR) is applied from the input terminal 9 and a polarity reversal pulse (FRP) is applied from the newly provided input terminal 101. I do.
The power supply V connected to the division of the first divisional resistors R1 and R2
DD1 is supplied with a normal power supply electrode via the dividing resistor R1 as shown in FIG. 2 during the "low level" period of the uniformity improvement pulse, but is controlled by the control transistor during the "high level" period of the uniformity improvement pulse. 10 is turned "on", so that the preset division resistors R1, R2
To cause a voltage drop A.

Further, as a feature of the present invention, the power supply VDD1 of the first divided resistors R1 and R2 is connected to the second divided resistor R
11 and R12, for example, 1
This is controlled by the polarity inversion pulse of the H inversion, and during the “high level” period of the polarity inversion pulse, the inverter circuit 102 makes the “low level”, the control transistor 103 is in the “off” state, and the gate pulse is turned off. Output as is.

During the "low level" period of the polarity inversion pulse, the inverter circuit 102 sets the level to "high level", the control transistor 103 is turned "on", and the voltage drop VDD1 is generated in the power supply VDD1. That is, the amplitudes of the gate pulses G1, G2, G3 generated by the buffer circuit 3 connected to the power supply VDD1 are controlled by the polarity inversion pulse. That is, by the polarity inversion pulse,
The gate pulse amplitude of the prior art is used for the “high-level video signal”, and the gate pulse amplitude is controlled to be the same as the operating point for writing the “high-level video signal” for the “low-level video signal”. I do.

That is, the deviation voltage (dive level) ΔVL at the time of writing the “low level video signal” is equal to the dive level ΔV at the time of writing the “high level video signal”.
It is controlled to be the same as VH. This relationship is expressed by the following equation. ΔVL = ΔVH = Thereby, the absolute level of the diving of the “low-level video signal” is reduced, and not only the uniformity such as “surface roughness defect” is improved, but also the process margin at the time of manufacturing can be further expanded. The connection point of the power supply VDD1 is not limited to the buffer circuit 3, but the V shift register 2,
Alternatively, it may be connected to both the V shift register 2 and the buffer circuit 3, and the method is not limited to a circuit method as long as a similar result can be obtained. Hereinafter, the liquid crystal display device of the present invention is operated in accordance with a common law.

The present invention is not limited to the above embodiment,
Various embodiments can be employed. For example, in this embodiment, a liquid crystal display device driven by 1H inversion is illustrated, but the present invention can be applied to a liquid crystal display device driven by another method. Also, an example in which the horizontal and vertical drive circuits are interpolated has been described, but the present invention is also applicable to a liquid crystal display device in which the horizontal and vertical drive circuits are extrapolated. Further, it goes without saying that the present invention can be developed in various forms without being limited to the embodiment described above.

[0032]

As described above, according to the liquid crystal display device and the method of driving the same of the present invention, when the "high-level video signal" is generated by the additional circuit of the present invention, the gate pulse amplitude of the prior art is used and " In the case of "low-level video signal", the amplitude of the gate pulse is controlled to be small so as to be the same as the operating point when writing "high-level video signal". As a result, the diving level at the time of writing the “low-level video signal” becomes equal to the diving level at the time of writing the “high-level video signal”, and the uniformity such as “surface roughness defect” is only improved. Alternatively, it is possible to further increase the process margin at the time of manufacturing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a liquid crystal display device of the present invention.

FIG. 2 is a timing chart illustrating a driving method of the liquid crystal display device of the present invention.

FIG. 3 is a block diagram illustrating a main part of a conventional liquid crystal display device.

4A and 4B are diagrams illustrating a driving method of a liquid crystal display device according to the related art, in which FIG. 4A is a timing chart for writing a “low-level video signal”, and FIG. FIG. 7 is a timing chart for writing.

FIG. 5 is a waveform diagram showing a write gate pulse and a video signal level.

FIG. 6 is a block diagram showing an example of a conventional technique for improving uniformity.

FIG. 7 is a timing chart showing an example of a conventional technique for improving uniformity.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 H shift register 2 V shift register 3 buffer circuit 4 n horizontal switch 5 data line 6 gate line 7 TFT 8 common line 9, 101 input terminal 10, 103 control transistor 100 additional circuit of the present invention 102 inverter circuit

Claims (3)

(57) [Claims] A buffer circuit to which a plurality of gate lines arranged in a row are connected; a V shift register to which the buffer circuit is connected; a horizontal switch to which a plurality of data lines arranged in a column are connected; In a liquid crystal display device comprising: an H shift register to which the horizontal switch is connected; and a pixel portion provided at each intersection of the gate line and the data line, at least a power supply terminal of the buffer circuit is divided by a predetermined division. Connected to a dividing portion of a first divided resistor controlled via a control transistor to which a uniformity improvement pulse is inputted, and further comprising a power supply terminal of the first divided resistor connected to a predetermined dividing ratio. And connected to a dividing portion of a second dividing resistor controlled via a control transistor to which a polarity inversion pulse is input, and connecting a power supply terminal of the second dividing resistor to a power supply terminal. The liquid crystal display device, characterized in that connected to. 2. A buffer circuit to which a plurality of gate lines arranged in a row are connected, a V shift register to which the buffer circuit is connected, a horizontal switch to which a plurality of data lines arranged in a column are connected, A method for driving a liquid crystal display device comprising: an H shift register to which the horizontal switch is connected; and a pixel unit provided at each intersection of the gate line and the data line, wherein at least a power supply terminal of the buffer circuit includes: A first divisional resistor having a predetermined division ratio and controlled by a uniformity improvement pulse, connected to a division portion of the first divisional resistance; and a power supply terminal of the first divisional resistance having a predetermined division ratio and a polarity Connecting the power supply terminal of the second divided resistor to a power supply, and connecting the power supply terminal of the second divided resistor to a power supply; A gate pulse generated by the buffer circuit connected to the terminal is controlled by a uniformity improvement pulse to cause a voltage drop. Further, a power supply terminal of the second divided resistor is controlled by a polarity inversion pulse, and a low-level video signal A method of driving a liquid crystal display device, wherein the amplitude of a gate pulse generated by the buffer circuit is reduced when writing data. 3. The gate pulse generated by the buffer circuit is at a diving level caused by capacitive coupling when writing a low-level video signal and a high-level video signal.
3. The method according to claim 2, wherein the control is performed so as to be equal to a certain bias voltage.