JP2000194330A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a horizontal scanning driving means by supplying the voltage level of selected gradation voltage obtained when the output state of a logical circuit means is changed to respective video signal lines as video signal voltage. SOLUTION: Plural gradation voltage values are inputted to a 1st selector circuit 123, which selects any one of these gradation voltage values by the upper bit of display data and outputs the selected voltage to a 2nd selector circuit 124. The voltage levels of these gradation voltage values are stepwise changed at prescribed timing within one scanning period. The circuit 124 selects the voltage level of the gradation voltage selected by the circuit 123 at a certain timing by the lower bit of the display data and outputs the selected voltage level to a drain signal line D. Consequently the gradation voltage corresponding to the display data is written in each pixel having a thin film transistor connecting its gate electrode to a selected gate signal line G and an image is displayed on a display part 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and, more particularly, to a technique effective when applied to a circuit for supplying a video signal voltage to each pixel.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switchingly driving the active element is widely used as a display device of a notebook type personal computer or the like. One of the active matrix type liquid crystal display devices includes a TFT (Th
2. Description of the Related Art A liquid crystal display module of a (Film Transister) type is known. In this TFT type liquid crystal display module, since a video signal voltage (grayscale voltage) is applied to a pixel electrode via a thin film transistor (TFT), there is no cross talk between pixels, and a simple matrix type liquid crystal display device is used. Multi-tone display is possible without using a special driving method for preventing crosstalk. In an active matrix type liquid crystal display device, as a driving method for applying a multi-gradation video signal voltage to each pixel in order to enable the multi-gradation display, a method described in JP-A-5-35200 is used. It has been known. The above publication (Japanese Unexamined Patent Publication No.
No. 35200), 2 ^m voltage bus lines are provided, and the gray scale voltage supplied from the 2 ^m voltage bus lines is set to 2 ^{k for} one scanning period (one scanning line). Change in steps. Then, one of the 2 ^m voltage bus lines is selected according to the value of the upper m bits of the n-bit display data, and the lower k (k = nm) of the n-bit display data is selected. Depending on the value of the bit,
One of the voltage levels of the selected voltage bus line that changes in a stepwise manner of the gradation voltage is selected and applied to the pixel electrode of each pixel. For example, when the display data is 3 bits (n = 3), and m is 1 and k is 2,
Two voltage bus lines are provided, and the voltage level of the gray scale voltage on the two voltage bus lines is changed in four steps during one scanning period. The grayscale voltage on one of the two voltage bus lines is selected according to the value of the upper one bit of the data, and the grayscale voltage changes in a stepwise manner on the selected voltage bus line. One of the voltage levels is selected based on the value of the lower 2 bits of the 3-bit display data, and is applied to the pixel electrode of each pixel. According to the driving method described in the above publication, it is possible to reduce the operation speed of a circuit that applies a video signal voltage to each pixel, and to reduce the number of voltage bus lines.

[0003]

In recent years, in a liquid crystal display device, the number of gradations has been increased to 64 gradations or 256 gradations. Then, when 64 gradations or 256 gradations are realized by the driving method described in the above publication, 2 ^k on the selected voltage bus line is realized.
The circuit scale of the selection circuit for selecting the stepwise changing voltage level becomes large, and when the selection circuit is incorporated in the liquid crystal display panel, the area occupied by the selection circuit becomes large, and the liquid crystal display panel becomes large. There was a problem of becoming. SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and it is an object of the present invention to provide a technique that can reduce the circuit scale of a horizontal scanning drive unit in a liquid crystal display device. Is to do. The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0004]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention relates to a liquid crystal display device having two substrates, one of which is transparent and facing each other, and a liquid crystal layer sandwiched between the two substrates. A plurality of video signal lines for applying a video signal voltage to the plurality of video signal lines; a driving unit for supplying a video signal voltage to the plurality of video signal lines; a power supply unit for supplying a plurality of gradation voltages to the driving unit; A display control means for controlling the means, wherein the display control means supplies at least n-bit display data and p kinds of time control signals to the driving means, The section supplies to the driving means 2 ^m gradation voltages of which voltage levels are different and whose voltage level changes with time within one scanning period, and the driving means supplies the driving means from the display control means. N bits transmitted Storage means for storing display data, provided in each of the respective video signal lines 2, according to the bit value of the m bits of the display data of n bits stored in said storage means, is supplied from the power supply unit selecting means for selecting any one of the ^m gradation voltages; and a bit value of each of p bits of n-bit display data provided for each of the video signal lines and stored in the storage means. And p switching means for selecting the time control signal or the first level voltage supplied from the display control unit, and each output of the p switching means provided for each video signal line. When the voltage is the first level voltage,
A logic circuit means for changing an output state, and a logic circuit means provided for each of the video signal lines, wherein the gray scale voltage selected by the selection means in accordance with a change in the output state of the logic circuit means, Output circuit means for supplying a voltage level when the output state changes as a video signal voltage to each of the video signal lines.

Further, the present invention provides a plurality of pixels provided in a matrix, a plurality of video signal lines for applying a video signal voltage to pixels in a column or row direction of the plurality of pixels, and a plurality of video signal lines. A liquid crystal display device comprising: a driving unit for supplying a video signal voltage to the driving unit; a power supply unit for supplying a plurality of gradation voltages to the driving unit; and a display control unit for controlling the driving unit. The display control means supplies at least n bits of display data and n time control signals to the driving means, and the power supply unit supplies the driving means with the voltage level within one scanning period. Supplies a gray-scale voltage that changes with time, the driving means includes storage means for storing n-bit display data transmitted from the display control means, and storage means provided for each of the video signal lines. N switching means for selecting a time control signal or a first level voltage supplied from the display control unit according to each bit value of the n-bit display data stored in the video signal line; A calculation result transmission unit that changes an output state when each output voltage of the n switching units is a first-level voltage; and a calculation result transmission unit that is provided for each of the video signal lines.
Each of the video signal lines is defined as a video signal voltage at a change in the output state of the calculation result transmitting means in a gray scale voltage supplied from the power supply unit in accordance with a change in an output state of the calculation result transmitting means. And an output circuit means for supplying the output circuit means.

[0007] The present invention also relates to a transparent two-sided two-piece structure.
In a liquid crystal display device having two substrates and a liquid crystal layer sandwiched between the two substrates, a plurality of pixels, a plurality of video signal lines for applying a video signal voltage to the plurality of pixels, and the plurality of A liquid crystal having a driving circuit for supplying a video signal voltage to a video signal line, a plurality of display data lines for supplying display data to the driving circuit, and a gradation voltage line for supplying a plurality of gradation voltages to the driving circuit A display device, wherein the driving circuit comprises:
A plurality of display data calculation circuits provided for each of the display data lines and performing calculations based on display data supplied by the display data lines; and a plurality of display data calculation circuits supplied by the gradation voltage lines according to calculation results of the display data calculation circuits A gray scale voltage output circuit for outputting any one of the plurality of gray scale voltages to the video signal line as a video signal voltage; An operation result transmission line to be transmitted to an output circuit, wherein the plurality of display data operation circuits, the gradation voltage output circuit, and the operation result transmission line are provided for each of the video signal lines, and
The plurality of display data operation circuits and the gradation voltage output circuit are connected in series by operation result transmission lines for each of the video signal lines.

According to another aspect of the present invention, there is provided a liquid crystal display device having two substrates facing each other, and a liquid crystal layer sandwiched between the two substrates. A plurality of video signal lines, a drive circuit for supplying a video signal voltage to the plurality of video signal lines, a plurality of display data lines for supplying display data to the drive circuit, and the drive circuit What is claimed is: 1. A liquid crystal display device comprising: a gray scale voltage line for supplying a gray scale voltage that changes periodically; and a plurality of control signal lines for supplying a pulse signal to the drive circuit. Display data provided for each line and supplied by the display data line;
A plurality of arithmetic circuits for performing an arithmetic operation with a pulse signal supplied by a corresponding one of the plurality of control signal lines; and a plurality of arithmetic circuits which are supplied by the gradation voltage line according to values of the plurality of arithmetic circuits. Selecting means for selecting any one of the plurality of gray scale voltages, the plurality of arithmetic circuits and the selecting means are provided for each of the video signal lines, and the display data is , Stored in storage means provided for each of the display data lines.

According to another aspect of the present invention, there is provided a liquid crystal display device having two substrates facing each other and a liquid crystal layer sandwiched between the two substrates, wherein a plurality of pixels and a video signal voltage are applied to the plurality of pixels. A plurality of video signal lines, a driving circuit for supplying a video signal voltage to the plurality of video signal lines, n display data lines for supplying n-bit display data to the driving circuit, A gradation voltage line for supplying a circuit with a gradation voltage that periodically changes in 2 ⁿ stages according to time; and ^{n control} circuits for supplying the drive circuit with data whose value changes in accordance with the change in the gradation voltage. A liquid crystal display device having a signal line, wherein the drive circuit is provided for each display data line, and display data supplied by the display data line;
N arithmetic circuits for performing an arithmetic operation with data supplied by a corresponding control signal line among the n control signal lines; and a grayscale voltage line according to an arithmetic result of the n arithmetic circuits. And an output circuit for selecting any one of the gray scale voltages supplied by the formula (1) and outputting the selected gray scale voltage as a video signal voltage, wherein the n arithmetic circuits and the output circuit It is provided for each video signal line, and the n arithmetic circuits are provided on an extension of each video signal line.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[First Embodiment] FIG. 1 is a block diagram showing an overall schematic configuration of a TFT type liquid crystal display module according to a first embodiment of the present invention. The liquid crystal display module according to the present embodiment includes a liquid crystal display panel (the liquid crystal display element of the present invention) 10, a display control device 11, and a power supply circuit 12. The liquid crystal display panel 10 includes a display unit 110, a vertical pixel line selection circuit (hereinafter, referred to as a horizontal scanning circuit) 120, and a horizontal pixel line selection circuit (hereinafter, referred to as a vertical scanning circuit) 130. . Here, the horizontal scanning circuit 120 is a memory address selection circuit (hereinafter, referred to as a horizontal shift register circuit) 121.
, A digital signal memory array 122, a first selection circuit (upper bit selection circuit) 123, and a second selection circuit (lower bit selection circuit) 124.

FIG. 2 shows a liquid crystal display panel 1 according to the present embodiment.
FIG. 4 is a circuit diagram illustrating an equivalent circuit of an example of 0. In FIG. 2, signals input from the display control device 11 to the horizontal scanning circuit 120 and the vertical scanning circuit 130 and the power supply circuit 12
And the gray scale voltage input to the horizontal scanning circuit 120 from FIG. The display portion 110 of this embodiment includes pixels arranged in a matrix, and each pixel has two adjacent gate signal lines (scanning signal lines or horizontal signal lines).
(G) and two adjacent drain signal lines (video signal lines or vertical signal lines) (D) are arranged in an intersecting region (a region surrounded by four signal lines). Each pixel is, for example,
Polysilicon transistor (hereinafter, Poly-SiTr)
Called. ), And the drain region of each thin film transistor (TFT) for each column of each pixel arranged in a matrix is connected to a drain signal line (D), and is arranged in a matrix. The source region of each thin film transistor (TFT) of each arranged pixel is connected to the pixel electrode (ITO1). Note that the drain region and the source region are originally determined by the bias polarity between them, and in the liquid crystal display device of the present embodiment, the polarities are inverted during the operation, so that the drain region and the source region are switched during the operation. But,
In this specification, for convenience, one is fixed as a drain region and the other is fixed as a source region.

A gate electrode of each thin film transistor (TFT) in each row of each pixel arranged in a matrix is connected to a gate signal line (G), and each thin film transistor (TFT) has a positive bias voltage applied to the gate electrode. Is applied and a negative bias voltage is applied to the gate electrode to turn off. Further, since a liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (counter electrode) (ITO2), the pixel electrode (ITO1) and the common electrode (ITO2) are provided.
O2) is equivalently connected to a liquid crystal capacitor (CLC). Further, a storage capacitor (CST) is provided between the source region of the thin film transistor (TFT) and the common signal line (CN).
G) is formed, and a drive voltage (VCOM) applied to the common electrode is applied to the common signal line (CN). Although FIG. 2 is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. The drain region of each thin film transistor (TFT) for each column of each pixel arranged in a matrix is connected to a video signal line (D), and the video signal line (D) is connected to a second selection circuit 124. Connected. The gate electrode of each thin film transistor (TFT) for each row of each pixel arranged in a matrix is connected to a gate signal line (G).
Are connected to the vertical scanning circuit 130.

The display control device 11 is composed of one semiconductor integrated circuit (LSI), and displays control signals such as a clock signal, a display timing signal, a horizontal synchronizing signal, and a vertical synchronizing signal transmitted from a computer main body. Horizontal scanning circuit 1 based on display data (R, G, B)
20 and the vertical scanning circuit 130. The power supply circuit 12 shown in FIG. 1 supplies grayscale voltages (VA1 to VA8) to the horizontal scanning circuit 120, and also applies drive voltages (positive bias voltage and negative bias voltage) applied to the gate electrode of the thin film transistor (TFT). ) For the vertical scanning circuit 1
30 and a drive voltage of (VCOM) to the common electrode (ITO2).

Next, an outline of the operation of the liquid crystal display module of this embodiment when the display data is 6 bits will be described. When the first display timing signal is input after the input of the vertical synchronization signal, the display control device 11 determines that this is the first display line and outputs a start pulse (SY) to the vertical scanning circuit 130. . In addition, the display control device 11 outputs 1 based on the horizontal synchronization signal.
A clock (CLG), which is a shift clock of one horizontal scanning time period, is output to the vertical scanning circuit 130 so that a positive bias voltage is sequentially applied to each gate signal line (G) of the display unit 110 every horizontal scanning time. I do. Accordingly, the vertical scanning circuit 130 sequentially selects the gate signal lines (G), outputs a positive bias voltage to the selected gate signal lines (G), and outputs a gate electrode to the selected gate signal lines (G). Are turned on for one scanning period.

When a display timing signal is input, the display control device 11 determines that the display timing signal is a display start position, and converts the received simple one-column 6-bit display data into a digital signal memory array 122 of the horizontal scanning circuit 120. Output to At the same time, the display control device 11 sends a start pulse (DX) and a display data latch clock (CL) to the horizontal shift register circuit 121 of the horizontal scanning circuit 120.
D) is output. Thereby, the horizontal shift register circuit 121 sequentially outputs the shift pulse (SH) for capturing the display data to the digital signal memory array 122.
The digital signal memory array 122 sequentially stores the display data by using the display data capture shift pulse (SH), and stores the upper bits of the display data in the first selection circuit 1.
23, the lower bits of the display data are stored in the second selection circuit 12
4 is output.

A plurality of gray scale voltages (eight in FIG. 2) are input to the first selection circuit 123, and the first selection circuit 123 uses the upper bits of the display data to output the plurality of gray scale voltages. The second selection circuit 12 selects any one of the adjustment voltages.
4 is output. In this case, the plurality of gradation voltages are 1
During a scanning period, the voltage level changes stepwise at a predetermined timing. The second selection circuit 124 selects a voltage level at a certain timing of the gray scale voltage selected by the first selection circuit 123 based on the lower bits of the display data, and outputs the selected voltage level to the drain signal line (D). As a result, the gradation voltage corresponding to the display data is written to the pixel having the thin film transistor (TFT) whose gate electrode is connected to the selected gate signal line (G), and the display unit 11
The image is displayed at 0. Note that the horizontal scanning circuit 120 and the vertical scanning circuit 130 shown in FIG. 1 are incorporated in a liquid crystal display panel, are made of Poly-SiTr like a thin film transistor (TFT), and are formed on the same substrate.

FIG. 3 is a circuit diagram showing a circuit configuration of the digital signal memory array 122 shown in FIGS. FIG.
As shown in FIG. 7, the digital signal memory array 122 includes a first latch circuit 122A and a second latch circuit 122B. (SH), the display data from the display control device 11 is sequentially latched. The second latch circuit 122B outputs an output timing control clock (C) from the display control device 11.
LA), the display data captured by the first latch circuit 122A is latched, and the upper three bits of the display data are stored in the first selection circuit (123), and the lower three bits are stored in the second selector circuit 123.
To the selection circuit (124).

FIG. 4 shows the first selection circuit 1 shown in FIGS.
FIG. 23 is a circuit diagram showing a circuit configuration of a selection circuit per 23 drain signal lines (D). In the figure, B6 is the sixth bit of the display data, B5 is the fifth bit of the display data,
4 represents the fourth bit of the display data. As shown in FIG. 4, the selection circuit for one drain signal line (D) in the first selection circuit 123 includes a p-type MOS transistor (hereinafter, simply referred to as PMOS) and an n-type MOS transistor (hereinafter, simply referred to as PMOS). (Hereinafter simply referred to as NMOS)).
8 sets. The 6-bit (B6) positive-phase output or inverted output of the display data is applied to the PMOS and NMOS gate electrodes of each gate circuit (GT1). The PMOS and NMOS of each gate circuit (GT2) are also applied.
The positive-phase output or inverted output of the 5th bit (B5) of the display data is applied to the gate electrode of, and the PMOS and NMOS gate electrodes of each gate circuit (GT3) are connected to the 4 bits of the display data (B3). B4) The positive-phase output or inverted output of the eye is applied. By changing the combination of the positive phase output or the inverted output of each bit applied to the PMOS and NMOS gate electrodes of each of the gate circuits (GT1 to GT3), the eight voltage bus lines (131 to 138) are changed. One of the gradation voltages is selected and output to the second selection circuit 124. In this case, as shown in FIG.
38) The grayscale voltages (VA1 to VA8) have different voltage levels, and the voltage levels change in eight steps within one scanning period.

FIG. 6 shows the second selection circuit 1 shown in FIGS.
FIG. 14 is a circuit diagram showing a circuit configuration of a selection circuit per 24 drain signal lines (D). In the figure, B3 is the third bit of the display data, B2 is the second bit of the display data, B
1 represents the first bit of the display data.
Reference numeral 43 denotes a time control signal line to which a time control pulse having a waveform as shown in FIG. 7 is supplied, for example. FIG.
In, is for the third bit (B3) of the display data,
Is a time control pulse for the second bit (B2) of the display data, and is a time control pulse for the first bit (B1) of the display data. The time control pulse is a pulse in which a High level (hereinafter, simply referred to as H level) voltage level and a Low level (hereinafter, simply referred to as L level) voltage level are alternately repeated. When the period of the time control pulse for one bit (B1) of the display data is k,
The period of the time control pulse for the second bit (B2) of the display data is 2k, and the time control pulse period for the third bit (B3) of the display data is 4k (2 × 2 × k). This time control pulse (-) is shown in FIG.
In the middle period of t _n -t _n−1 , each gray scale voltage rises near the center of the step-like step. This is because the grayscale voltage applied to the drain signal line (D) is determined at the timing of the rise of the time control pulse, so that the drain signal line (D This is to ensure that the gray scale voltage applied to ()) can be determined.

The PMOS (PT1) and NM shown in FIG.
In a CMOS switching circuit (SW1) composed of the OS (NT1), when the positive-phase output of the first bit of the display data is input to each gate electrode and the first bit of the display data is at the H level, time control is performed. Outputs a pulse,
When the first bit of the display data is at L level, VD (H
Level). Similarly, the CMOS switching circuit (SW2) including the PMOS (PT2) and the NMOS (NT2) outputs a time control pulse when the second bit of the display data is at the H level, and outputs the second bit of the display data. Is low level, VD (H level) is output. In addition, PMOS (PT3) and NMOS
The switching circuit (SW3) having a CMOS configuration composed of (NT3) outputs a time control pulse when the third bit of the display data is at the H level, and outputs VD ( H level).

Each of the PMOSs (PT4 to PT6) and each of the NMOSs (NT4 to NT6) form a three-input NAND circuit which receives the output of each switching circuit (SW1 to SW3) as an input. Unless the signal input to each input node (N1, N2, N3) goes to H level, its output node is kept at H level. PMO
S (PT7), NMOS (NT7) and PMOS (P
T11) is a switching transistor in which the reset pulse shown in FIG. 7 is input to each gate electrode. When the reset pulse is at the H level, the PMOS
Since (PT7) is turned off, the electrical connection between the node (N4) and the node (N5) is cut off, and
Since the OS (PT11) is also turned off, the electrical connection between the node (N6) and the node (N8) is cut off. Thereby, the electrical connection between the node (N6) and another node in the circuit is cut off. At the same time, when the reset pulse is at the H level, the NMOS (NT7) is turned on, so that the node (N6) is connected to the power supply potential (VD), and the node (N6) is initialized. When the reset pulse is at L level, the PMOS (PT7) and PM
Since the OS (PT11) is on and the NMOS (NT7) is off, the node (N4) and the node (N5) and the node (N6) and the node (N8) are electrically connected, Further, the node (N6) is disconnected from the power supply potential (VD).

The PMOS (PT8) and NMOS (NT
8) are PMOS (PT7) and NMOS (NT1)
1) is on, the output of the NAND circuit (node (N
4), (N5) and (N6)). Also, PMOS (PT9)
And the NMOS (NT9) include an inverter circuit (IV
An inverter circuit (IV2) having the output of 1) as an input. The output of this inverter circuit (IV2) is a PMOS
When (PT11) is on, the inverter circuit (IV
1), the NMOS (NT7) or NMOS (NT11) is turned off, and when the input of the inverter circuit (IV1) is electrically disconnected from the output of the NAND circuit, these two inverter circuits ( IV1, I
V2) is a latch circuit, and an inverter circuit (IV1,
The state of IV2) is maintained. Here, the PMOS (PT1
The role of 1) is that when the inverter circuit (IV1) is electrically disconnected from the output of the NAND circuit, the potential change of the node (N6) due to dark current or leakage is compensated for by the output of the inverter circuit (IV2). The PMOS (PT11) needs to be a transistor having a substantially large ON resistance. That is, when the output of the NAND circuit changes from H level to L level, PM
H level potential of the inverter circuit (IV2) input via the OS (PT11) (potential of the node (N8))
Does not substantially affect the L-level output of the NAND circuit,
The output of the inverter (IV1) is inverted, and the node (N7)
Needs to be high enough to change the potential of L from L level to H level. To ensure this behavior,
A high resistance may be inserted between the PMOS (PT11) and the node (N6).

The NMOS (NT11) is a switching transistor to which the output of the inverter circuit (IV2) is applied to the gate electrode. The NMOS (NT11) turns on when the node (N6) is at H level, and turns off when the node (N6) is at L level. Become.
That is, once the node (N8) becomes L level, the electrical connection between the node (N5) and the node (N6) is cut off until the node (N8) is set to the initial state by the reset pulse. This node (N8) is connected to the PMOS (PT11)
Is electrically connected to the node (N6) via This is because when the potential of the node (N6) changes from H level to L level, this PMOS (PT11)
8) acts as a resistance component to the H level potential,
It plays a role in making the level state stable.

The PMOS (PT10) and the NMOS (N
T10) is a gate circuit (GT4), and a PMOS (P
The output of the inverter circuit (IV1) is applied to the gate electrode of T10), and the output of the inverter circuit (IV2) is applied to the gate electrode of the NMOS (NT11). When the output of the inverter circuit (IV1) is at L level and the inverter circuit (IV
When the output of 2) is at the H level, the gate circuit (GT4) is turned on and supplies the gray scale voltage selected by the first selection circuit 123 to the drain signal line (D). When the output of the inverter circuit (IV1) is at H level and the output of the inverter circuit (IV2) is at L level, the gate circuit (G
T4) is turned off, and the gray scale voltage selected by the first selection circuit 123 is disconnected from the drain signal line (D). Once the gate circuit (GT4) is turned off, the gate circuit (GT4) maintains the off state until the next reset pulse goes high, so that the gray scale voltage written to each pixel is selected by the first selection circuit 123. At the voltage level that changes with time of the gray scale voltage, the voltage becomes the voltage of the voltage level at the timing when the gate circuit (GT4) is turned off. C0
Is a capacitance element that holds the potential of the drain signal line (D), and this capacitance element (C0) may use the gate capacitance and the wiring capacitance of the MOS transistor.

Now, the lower three bits of the display data are "1,
The operation of the second selection circuit 124 will be described using the case of “0, 1” as an example. The lower three bits of the display data are "1,
In the case of "0, 1", the switching circuit (SW1) outputs the time control pulse, the switch circuit (SW2) outputs the potential of VD, and the switch circuit (SW3) outputs the time control pulse. Before the timing of time t0, the reset pulse goes to the H level, and the node (N6) is set to the initial state of the H level. During this time, the output of the inverter circuit (IV1) changes from H level to L level, and the output of the inverter circuit (IV2) changes from L level to H level. Note that the H level of the reset pulse needs to be set to a time period sufficient for the above-described operation to be reliably performed. When this initial state ends, the NMOS (NT11)
Is turned on, the node (N5) and the node (N6) are electrically connected, and at the same time, the gate circuit (GT4) is also turned on. ). Therefore, the potential of the drain signal line (D) becomes the potential of the voltage level at the timing of the grayscale voltage t0 shown in FIG.

At time t0, the reset pulse is:
The level changes from H level to L level.
(NT7) is turned off, the node (N6) is disconnected from the power supply potential (VD), and at the same time, the PMOS (PT7)
Turns on, the node (N4) and the node (N5) are electrically connected, and the PMOS (PT11) is turned on, and the node (N6) and the node (N8) are electrically connected. That is, the output of the NAND circuit becomes the input of the inverter circuit (IV1). At the timing of time t0,
Since the three inputs of the NAND circuit are at L level, H level, and L level, the output of the NAND circuit is at H level, and the gate circuit (GT4) is turned on and the first
Is supplied to the drain signal line (D). Therefore, the drain signal line (D)
Is the potential of the voltage level at the timing of the grayscale voltage t0 shown in FIG.

At the time t1, the three inputs of the NAND circuit go to H level, H level and L level, but the output of the NAND circuit is still at H level.
The gate circuit (GT4) maintains the ON state, and the gray scale voltage selected by the first selection circuit 123 is supplied to the drain signal line (D). Therefore, the potential of the drain signal line (D) becomes the potential of the voltage level at the timing of t1 of the gradation voltage shown in FIG. Similarly, at times t2 and t
Also at the timings of 3 and t4, one of the three inputs of the NAND circuit is at the L level, the output of the NAND circuit is at the H level, the gate circuit (GT4) maintains the ON state, and the first Is supplied to the drain signal line (D). Therefore, at the timings of times t2, t3, and t4, the potential of the drain signal line (D) becomes the gradation voltages t2 and t shown in FIG.
The potential at the voltage level at the timing of 3, t4.

When the time control pulse rises from the L level to the H level at the timing of time t5, all three inputs of the NAND circuit go to the H level and the output of the NAND circuit goes to the L level for the first time. Thereby, the node (N
5), and the node (N6) goes to L level, the output of the inverter circuit (IV1) changes from L level to H level, and the output of the inverter circuit (IV2) changes from H level to L level. Therefore, the gate circuit (GT
4) is turned off, and the potential of the drain signal line (D) is set to the potential immediately before the time t5, that is, the same potential as the potential at the time t5, and the gray scale voltage selected by the first selection circuit 123 is changed. From the drain signal line (D). At the same time, the potential of the node (N8) changes to L level,
The NMOS (NT11) is turned off, cutting off the electrical connection between the NAND circuit and the inverter circuit (IV1).
Therefore, after this, the reset pulse becomes H level, and this state is maintained irrespective of the output of the NAND circuit, that is, the output from the switch circuits (SW1 to SW3) until the reset pulse is set in the initial state. Therefore, by writing the potential of the drain signal line (D) to the pixel before the reset pulse goes to the H level, the gray scale voltage corresponding to the display data is written to the pixel.

FIG. 8 is a circuit diagram showing a circuit configuration of the first selection circuit and the second selection circuit studied by the present inventors before the present invention. In FIG. 8, first selection circuit 223 has the same circuit configuration as first selection circuit 123 of the present embodiment. The second selection circuit 224 has a circuit configuration similar to that of the first selection circuit 123 of the present embodiment, and includes a PMOS transistor of each gate circuit (GT31 to GT33).
The time control signals on the eight time control signal lines (241 to 248) shown in FIG. 9 are changed by changing the combination of the positive output or inverted output of the lower 3 bits of the display data applied to the gate electrode of the NMOS and the NMOS. (TP1-TP
8) Any one of the time control signals is selected, and the gate circuit (GT4) is changed from ON to OFF by the selected time control signal. The second selection circuit 224 shown in FIG. 8 requires eight time control signal lines (241 to 248) for the lower three bits of the display data, and six time control signal lines per time control signal line. Since transistors are required, 48 transistors are required as a whole, and when these circuits are incorporated in the liquid crystal display panel 10, the area occupied by these circuits increases. . In addition, when the number of bits of the display data is increased and the number of gradations is increased, for example, when the display data has an 8-bit configuration to realize 256 gradations, upper 4 bits and lower 4 bits are separated and the lower 4 bits are divided.
If the time control pulse is selected by bit, 16 time control signal lines are required, and the second selection circuit requires 128 transistors. As described above, in the circuit configuration shown in FIG. 8, the circuit scale is doubled every time the number of bits of the display data is increased by one bit to increase the number of gray scales. The area increases.

On the other hand, according to the circuit configuration of the second selection circuit 124 of the present embodiment, the number of time control signal lines is four including the reset pulse signal line, and the total number of transistors is There are twenty, and the circuit scale can be significantly reduced as compared with the circuit configuration shown in FIG. Also,
In this embodiment mode, the total number of transistors required in the first selection circuit 123 and the second selection circuit 124 is 76 per drain signal line (D). If the bit is 2 bits and the lower bit is 4 bits, the total number of transistors required in the first selection circuit 123 and the second selection circuit 124 is 46 per drain signal line (D) (upper bit The number of signal lines is nine (four voltage bus lines and five time control signal lines (including reset pulse signal lines)). Also,
Assuming that the upper bit is 1 bit and the lower bit is 5 bits, the first selection circuit 123 and the second selection circuit 124
, The total number of transistors required for each drain signal line (D) is 36 (upper bit 6 and lower bit 30), and the number of signal lines is 8 (two voltage bus lines, time control Signal lines (including six reset pulse signal lines).

Further, when the number of bits of the display data increases due to the increase in the number of gradations, the difference between the circuit configuration of the present embodiment and the circuit configuration shown in FIG. 8 becomes more remarkable. For example, if the display data has an 8-bit configuration and the number of upper bits and the number of lower bits are each 4 bits, then in the circuit configuration shown in FIG. 8, 32 input lines (16 voltage bus lines, time control signal lines) 16), and the total number of transistors required in the first selection circuit 223 and the second selection circuit 224 is 274 per drain signal line (D).
(136 high-order bits and 138 low-order bits), but in the circuit configuration of the present embodiment, the number of signal lines is 21 (16 voltage bus lines, time control signal lines (reset pulse signal lines 5), the first selection circuit 22
3 and the total number of transistors required in the second selection circuit 224 is 1 per drain signal line (D).
The number may be 62 (136 high-order bits, 26 low-order bits). In this case, assuming that the number of upper bits is 1 bit and the number of lower bits is 7 bits, in the circuit configuration of the present embodiment,
The number of signal lines required is ten (two voltage bus lines and eight time control signal lines), and the total number of transistors required in the first selection circuit 123 and the second selection circuit 124 is the number of drain signal lines ( D) Only 44 bits (6 high-order bits, 38 low-order bits) are required for each line. As described above, according to the present embodiment, the number of signal lines and the first
It is possible to reduce the total number of transistors required in the selection circuit 123 and the second selection circuit 124.

Second Embodiment FIG. 10 shows a TFT type liquid crystal display module according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a circuit configuration of a second selection circuit 124.
The second selection circuit 124 of the present embodiment includes a node (N
6) and the node (N8), an NMOS (NT12) is connected, and a pulse shown in FIG. 11 is applied to the gate electrode of the NMOS (NT12), and the potential of the node (N6) due to dark current or leakage or the like. It is designed to suppress the change. Also in the present embodiment, the number of signal lines, the first selection circuit 123 and the second selection circuit 124
Can reduce the total number of transistors required.

Third Embodiment FIG. 12 shows a TFT type liquid crystal display module according to a third embodiment of the present invention.
FIG. 4 is a circuit diagram showing a circuit configuration of a second selection circuit 124.
The second selection circuit 124 according to the present embodiment includes a PMOS (PT1) in which the output of the three-input NAND circuit is applied to the gate electrode.
1) and PM in which the reset pulse is applied to the gate electrode
OS (PT7) and NMOS (NT7) are connected between the power supply potential (VD) and the reference potential (GND),
The difference from the first selection circuit 124 of the first embodiment is that the potential at the connection point (node (N5)) between the OS (PT7) and the NMOS (NT7) is input to the inverter circuit (IV1). I do. Second selection circuit 1 of the present embodiment
At 24, when the reset pulse goes high,
The NMOS (NT7) turns on, and the node (N5) goes low.
Level. Thereby, the inverter circuit (IV1)
Is at H level, the output of the inverter circuit (IV2) is at L level, and the gate circuit (GT4) is turned on.

When the reset pulse goes low, N
The MOS (NT7) is turned off and the PMOS (PT7) is turned on. However, when the PMOS (PT11) is off, the node (N5) is in a floating state. However, as described in the first embodiment, since the inverter circuit (IV1) and the inverter circuit (IV2) form a latch circuit, even if the node (N5) is in a floating state, the gate circuit (GT4) is not driven. The ON state is maintained. Then, as in the first embodiment, at time t5
When the output of the 3-input NAND circuit becomes L level, PMO
S (PT11) is turned on, and the node (N5) becomes H level. This causes the output of the inverter circuit (IV1) to go low, the output of the inverter circuit (IV2) to go high, and the gate circuit (GT4) to turn off. This state is maintained until the reset pulse goes high again. You. Also in the present embodiment, the number of signal lines, the first selection circuit 123 and the second selection circuit 124
It is possible to reduce the total number of required transistors.

The second selection circuit 12 of the present invention
The circuit configuration of FIG. 4 is not limited to the configuration shown in each of the above-described embodiments.
It is also possible to employ the circuit configuration shown in FIG. In FIG. 13, NAND1 is a NAND circuit, NOR1.
Is a NOR circuit. N1, N2, and N3 indicate the node (N1), node (N2), and node (N3) shown in FIG. 6, respectively. , NMOS
(NT10) is applied to the gate electrode.

[Fourth Embodiment] FIG. 14 is a block diagram showing a schematic configuration of a whole TFT type liquid crystal display module according to a fourth embodiment of the present invention. The liquid crystal display module according to the present embodiment includes the first selection circuit 1 according to each of the above embodiments.
23 and the second selection circuit 124 are a single selection circuit 3
24. In FIG. 14, the display unit 110
Is a pair of opposed substrates, at least one of which is transparent,
It has a liquid crystal layer sandwiched between the substrates and pixels arranged in a matrix. Each pixel has two adjacent gate signal lines (scanning signal lines or horizontal signal lines) (G) and two adjacent gate signal lines (G). Drain signal lines (video signal lines or vertical signal lines)
(D) is arranged in an intersecting region (a region surrounded by four signal lines). Each pixel has, for example, a thin film transistor (TFT) made of a polysilicon transistor, and each thin film transistor (TFT) of each pixel has a pixel electrode (I
TO1). In FIG. 14, a thin film transistor (TFT) is shown in order to avoid complicating the drawing.
Is represented by a circuit symbol. Although only one pixel is described, a plurality of pixels are actually arranged in a matrix. Each pixel is arranged between two adjacent drain signal lines (D). A gradation voltage according to display data is supplied to each pixel through each drain signal line (D). The selection circuit 324 selects a gradation voltage according to the display data and supplies the selected gradation voltage to each drain signal line (D). Display data is supplied to the selection circuit 324 via the data lines (DD1 to DD3). Since the present embodiment shows a case where the display data is 3 bits, there are three data lines (DD1 to DD3). The number of data lines can be arbitrarily selected according to the display data.
The data lines (DD1 to DD3) are connected to a display data operation circuit 325 provided in the selection circuit 324. The display data operation circuit 325 performs an operation based on the display data. The grayscale voltage is output from the grayscale voltage output circuit 326 according to the calculation result of the display data calculation circuit 325. The display data operation circuit 325 and the gradation voltage output circuit 326 are provided for each drain signal line (D). Further, the display data operation circuit 325 is provided individually for each data line (DD1 to DD3). In this embodiment, since there are three data lines, three display data operation circuits 325 are provided for each drain signal line.

By separately providing the display data calculation circuit 325, it is possible to provide the display data calculation circuit 325 for each data line. Are provided in accordance with the arrangement of. In the present embodiment, the display data calculation circuit 325 is provided near the intersection of the extension of the drain signal line and the data lines (DD1 to DD3). Further, the interval between adjacent data lines is sufficiently wide so that the display data operation circuit 325 is provided. The interval between adjacent data lines has a margin compared to the interval between adjacent drain signal lines (D) which is limited by the size of a pixel. Therefore, by providing the arrangement of the display data operation circuit 325 in accordance with the arrangement of the data lines (DD1 to DD3), an area where the display data operation circuit 325 is provided can be secured. The region where the display data operation circuit 325 is provided is a region surrounded by two adjacent drain signal lines (D) and two adjacent data lines. They are provided in a line on the extension of (D).

In the case of the liquid crystal display element 10 in which the horizontal scanning circuit 120 and the display unit 110 are provided on the same substrate, the horizontal scanning circuit 120 is provided in a limited area around the display unit 110. The arrangement of the display data operation circuit 325 and the grayscale voltage output circuit 326 which constitute the horizontal scanning circuit 120 is also limited. As in this embodiment, the display data operation circuit 325 is provided on an extension of the drain signal line (D).
The width within the interval between two adjacent drain signal lines (D),
By arranging them in a line, a limited area can be used effectively. As described above, the display unit 110 includes:
Two adjacent drain signal lines (D) are provided across the pixel. A display data operation circuit 325 and a gradation voltage output circuit 326 are provided for each drain signal line. Therefore, if the width of the region where the display data calculation circuit 325 or the gray scale voltage output circuit 326 is formed does not fall within the interval between two adjacent drain signal lines (D), the display data calculation circuit 325 or the adjacent display signal calculation circuit 325 may be used. In addition, there is a problem that a region formed with the gradation voltage output circuit 326 overlaps. In this embodiment mode, the display data operation circuits 325 are individually provided for each data line in a line on an extension of the drain signal line (D), so that two adjacent drain signal lines (D) are provided. Display data calculation circuit 32 within the interval
5 can be provided. Further, in this embodiment, a display data operation circuit 325 is provided adjacent to each data line. Therefore, the data line (D
D1 to DD3) to the display data operation circuit 325 can be shortened. Data lines (DD1-D
If another circuit or wiring is provided between D3) and the display data calculation circuit 325, a width for providing wiring from the data line to those components is required. Therefore, it becomes difficult to provide a necessary configuration within a limited interval between the two drain signal lines (D).

FIG. 15 is a block diagram showing a circuit configuration of the horizontal scanning circuit 120 when the display data is 3 bits. In FIG. 15, the selection circuit 3 is connected to one drain signal line (D) to avoid complicating the drawing.
24 shows the configuration of the second embodiment. The display data operation circuit 325 is provided in the selection circuit 324. The display data operation circuit 325 is provided for each data line, and each display data operation circuit 325 has a time control signal line (161 to 161).
163) is connected. In the figure, reference numeral 328 denotes a display data holding circuit which stores display data of data lines (DD1 to DD3) in accordance with a signal of a timing signal line output from the horizontal shift register 121. Reference numeral 329 denotes an arithmetic circuit, and the display data holding circuit 32
8 and the data of the time control signal line, and the operation results are transmitted to the operation result transmission circuits (330 (1) to 330 (1) to 33
0 (3)). The gradation voltage output circuit 326 selects and outputs a gradation voltage according to the operation result. The operation result transmission circuits (330 (1) to 330 (3)) are connected in series by operation result signal lines 152. Further, the operation result transmission circuits (330 (1) to 330 (1) to
330 (3)) and the gradation voltage output circuit 326 are connected in series. Calculation result transmission circuit (330 (1) to 33 (33)
0 (3)) and the gradation voltage output circuit 326 are connected in series by the operation result signal line 152, so that the operation circuit 32
9 and the gradation voltage output circuit 326 can be omitted.

In the display data calculation circuit 325, the calculation circuit 329 calculates the value of the display data holding circuit 328 and the control signals of the time control signal lines (161 to 163), and outputs the calculation result to the calculation result transmission circuit (330 (1 ) To 330 (3)). By providing the display data holding circuit 328 and the arithmetic circuit 329 for each data line (DD1 to DD3), the wiring between the display data holding circuit 328 and the arithmetic circuit 329 can be shortened. The voltage bus line 151 is connected to the gradation voltage output circuit 326.
The voltage value of the voltage bus line 151 changes with time, and the change in the voltage value is repeated at a constant cycle. The time control signals of the time control signal lines (161 to 163) are used to select the gray scale voltage value of the voltage bus line 151 corresponding to the display data of the data lines (DD1 to DD3). The selection circuit 324 selects and outputs the gradation voltage of the voltage bus line 151 according to the value of the display data output by the display control device 11 shown in FIG. The gray scale voltage of the voltage bus line 151 changes periodically with time. Therefore, in order to select a desired voltage from the voltage bus line 151, the voltage of the voltage bus line 151 is held while the voltage of the voltage bus line 151 has a desired voltage value. If there is regularity in the period in which the voltage of the voltage bus line 151 reaches a desired voltage value, the voltage bus line 15
A desired voltage can be selected by designating a period for holding one voltage. The selection circuit 324 controls the values of the data lines (DD1 to DD3) and the time control signal lines 161 to 161.
A value indicated by the control signal 163 is calculated, and a period during which the voltage of the voltage bus line 151 is held is specified, and a gradation voltage of the voltage bus line 151 is selected. The values represented by the time control signal lines (161 to 163) change with time, and the voltage bus line 15
The voltage of 1 changes with regularity. If the change in the value represented by the time control signal lines (161 to 163) is made to conform to the regularity of the change in the voltage of the voltage bus line 151, the value represented by the time control signal lines (161 to 163)
The voltage of the voltage bus line 151 can be known.

In the selection circuit 324 of FIG. 15, an operation is performed for each data line. That is, in the present embodiment,
Since the display data is shown in the case of three bits, the number of data lines (DD1 to DD3) is three and the number of time control signal lines (161 to 163) is also three. An operation is performed between the data line DD1 and the time control signal line 163, and the operation result is output to the operation result transmission circuit 330 (1). Similarly, the other two data lines DD
The operation result between the time control signal line 2 and the time control signal line 162 is output to the operation result transmission circuit 330 (2), and the data line DD
The operation result between the time control signal line 3 and the time control signal line 161 is output to the operation result transmission circuit 330 (3). Each of the operation result transmission circuits (330 (1) to 330 (3))
It has a function of a logic circuit that performs a logical operation on the output of the output terminal 29 and outputs the operation result to the gradation voltage output circuit 326. When each of the operation result transmission circuits (330 (1) to 330 (3)) is a switching circuit, since the operation result transmission circuits are connected in series by the operation result signal line 152, the operation result transmission circuits (330 (1) ) To 330 (3))
The state in which the operation result transmission circuits (330 (1) to 330 (3)) are all ON and the voltage (VDD) is transmitted to the gradation voltage output circuit 326, and the operation result transmission circuits (330 (1) to (3))
330 (3)) is OFF, and there are only two states in which the voltage (VDD) is not transmitted to the gradation voltage output circuit 326.

In the present embodiment, a configuration is adopted in which an operation result transmission circuit to function as a switching circuit is selected from n operation result transmission circuits (330 (1) to 330 (3)). With this configuration, 2 ⁿ states can be represented even when ⁿ operation result transmission circuits (330 (1) to 330 (3)) are connected in series by the operation result signal line 152. . Table 1 shows the operation result transmission circuit (330
(1) to (3)) shows how to select which operation result transmission circuit is to be the switching circuit, and how to select it. In Table 1, (-) indicates the operation result transmission circuit (330 (1) to
330 (3)) is always ON, and SW is an operation result transmission circuit (330 (1) to 330 (1) to 330 (3)).
(3) indicates that it works as a switching circuit. Operation result transmission circuit (330 (1) to 330 (3))
Is a switching circuit, but an operation result transmission circuit (33
Setting 0 (1) to 330 (3)) to be always ON is considered the same as having no switching circuit.

[0044]

[Table 1]

When the switching circuits are connected in series, all the switching circuits are ON and at least one of the OFF circuits is OFF.
Although only one state can be selected, 2 ⁿ states can be selected by dividing the state according to which switching circuit is selected from the n switching circuits. Therefore, based on the data of the time control signal line, the arithmetic circuit 329 outputs an arithmetic result that turns on the switching circuit at an arbitrary time in accordance with the cycle in which the gradation voltage of the voltage bus line 151 changes. For example, it is possible to select the gradation voltage of the voltage bus line 151 at the time when the switching circuit is ON.

FIG. 16 and FIG. 17 are circuit diagrams showing an example of the circuit configuration of the selection circuit 324 when the display data is 3 bits in the present embodiment. The end of the line indicated by A in FIG. 16 is connected to the end indicated by A in FIG.
The end of the line indicated by B is connected to the end indicated by B in FIG. In the liquid crystal display module of the present embodiment, the number of voltage bus lines in the selection circuit 324 is one, and the voltage level of the voltage bus line 151 changes in eight steps as shown in FIG. Is supplied. Reference numerals 161 to 169 denote time control signal lines. Time control pulses having waveforms shown in FIG. 18 are supplied to the time control signal lines (161 to 169).
In FIG. 16, DD1 is the least significant bit, DD2
Is the second bit, DD3 is the third bit data line, C
M1, CM2, and CM3 are memory capacities.

Hereinafter, the operation of the selection circuit 324 when the 3-bit display data is "1, 0, 1" in the circuits shown in FIGS. 16 and 17 will be described with reference to FIG. FIG. 20 is a timing chart for explaining the operation of the selection circuit 324. First, the display data is stored in the memory capacity (CM) of the display data holding circuit 328.
1 to CM3). In the selection circuit 324 of this embodiment, one gate signal line (G) is provided every scanning period.
To apply a positive bias voltage to write a gray scale voltage to each pixel connected to the selected gate signal line (G). The display data is taken into the selection circuit 324 before the gray scale voltage is written to the pixel. While the grayscale voltage is being written to each pixel connected to the nth gate signal line (G), the display data to be written to the (n + 1) th pixel is taken into the selection circuit 324.

In the circuit shown in FIG. 16, an H-level display data capture shift pulse (SH) is output from the output terminal (HSR3) of the horizontal shift register circuit 121 of the horizontal scanning circuit 120 within one scanning period. When the display data capture shift pulse (SH) is output, the node (N
9) attains the H level, so that each of the data fetch transistors (NMTM1 to NMTM3) is turned on, and each of the memory capacities (CM1 to C1) from each of the data lines (DD1 to DD3).
M3) stores a voltage corresponding to each bit value of the 3-bit display data. As shown in FIG. 19, in the present embodiment, the display data “1” is at the L level and the display data “0” is at the H level. Therefore, when the display data is "1", the voltage level stored in the memory capacity is at the L level. Now, the memory capacity (CM1, CM2, CM
Since 3) considers a case where a voltage corresponding to 3-bit display data of “1, 0, 1” is stored, the voltage level held in the memory capacity CM1 is L level, and the voltage level of the memory capacity CM2 is Is at the H level, and the voltage level of the memory capacity CM3 is at the L level. As described above, in the selection circuit 324 of this embodiment, each memory capacity (C) is set in one scanning period before one scanning period in which the gradation voltage is written to each pixel.
M1 to CM3) hold voltages corresponding to the respective bit values of the 3-bit display data.

In the next one scanning period, the pulse shown in FIG. 20 is at the H level until time t0 shown in FIG. 20, so that the operation result signal line reset transistor (PMTIN1) connected to the operation result signal line 152 Is off. Thereafter, the reset pulse shown in FIG. 20 becomes H level, and the gray scale voltage output circuit reset transistor (NMTR1) is turned on. In this case, since all the operation result transmission transistors (PMTT1 to PMTT3) are on, each node (N1 to N4) is at L level (negative power supply potential Vss). Further, each PMOS (PMT5, PMT5,
PMT6, PMT7) and each NMOS (NMT5, NMT
6, NMT7) constitutes a level shift circuit having the potential of the node (N4) as an input. When the potential of the node (N4) is at the L level, the first output (node (N6)) of the level shift circuit is formed. ) Is at H level, and the second output (node (N7)) of the level shift circuit is at L level. As a result, the gate circuit (GT5) including the PMOS gate transistor (PMTAG) and the NMOS gate transistor (NMTAG) is turned on, and the gate circuit (GT)
From 5), the potential at the voltage level of V0 of the gradation voltage shown in FIG. 18 is output.

Next, the pulse shown in FIG. 20 changes from L level to H level, whereby each memory data transfer transistor (NMTTG1 to NMTTG3) is turned on and stored in each memory capacity (CM1 to CM3). The level potentials of the calculation transistors (PMTG1 to PMTG3, NMTG1 to PMTG1 to PMTG3 to NMTG1 to
NMTG3). Operation transistors (PMTG1 to PMTG3, NMTG1 to NMTG
Since the gate electrode of 3) stores the level potential before one scanning period, it is determined by the capacitance division between the level potential stored in each memory capacitor (CM1 to CM3) and the level potential one scanning period ago. The potential is the potential of the node (N10), the node (N11), and the node (N12). In this state, the potential of each node (N10 to N12) is set to the value of each PMOS operation transistor (PMTG1 to PMTG3).
And each NMOS operation transistor (NMTG1 to NM
TG3) is input to the display data operation circuit 325 having the same circuit configuration as the CMOS inverter circuit. Note that the display data calculation circuit 325 performs the same operation as the switching circuits (SW1 to SW3) illustrated in FIG. However, since the arrangement of the PMOS transistor and the NMOS transistor is opposite, the polarity of the output signal is opposite.
In the display data calculation circuit 325, each memory capacity (CM1
To CM3) to reflect the H level or L level stored in each of the PMOS operation transistors (PMTG1 to PM3).
To PMTG3) and each NMOS operation transistor (N
The gate capacity of MTG1 to NMTG3) and the capacity value of memory capacity (CM1 to CM3) are set. In addition,
The display data holding circuit 328 can be formed of an inverter circuit. For example, a latch circuit is formed using two inverter circuits as shown by the inverter circuits (IV1 and IV2) in FIG. 328
It can be used as In that case, the number of transistors used increases, but it is not necessary to set the capacitance value.

When the pulse shown in FIG. 20 changes from the L level to the H level, each of the PMOS operation transistors (PMTG1 to PMTG1) of each of the display data operation circuits 325 is changed according to the voltage level stored in each of the memory capacitors (CM1 to CM3). P
MTG3) or each NMOS operation transistor (NM
TG1 to NMTG3) is turned on, and each operation result transmission transistor (PMTT1 to PMTT3)
Is applied with a potential Vss or a time control pulse (,,). In the case of this example, each PMOS operation transistor (PM) of each display data operation circuit 325
TG1 to PMTG3) and the ON / OFF state of each NMOS operation transistor (NMTG1 to NMTG3), and each operation result transmission transistor (PMTT1 to PMTT)
Table 2 shows the connection destinations of the gate electrode 3).

[0052]

[Table 2]

Thereafter, the pulse shown in FIG. 20 changes from H level to L level, but the state shown in Table 2 is maintained. Next, at time t0, the pulse shown in FIG. 20 changes from the H level to the L level, the operation result signal line reset transistor (PMTIN1) turns on, and the potential of the node (N1) becomes the potential (VDD) of the potential (VDD). H level). Table 3 shows the ON / OFF state of each operation result transmission transistor (PMTT1 to PMTT3) and the voltage level of each node (N1 to N7) at this time.

[0054]

[Table 3]

In Table 3, the voltage level of the node (N8) indicates the voltage level of the drain signal line (D). Hereinafter, the same applies to Tables 4 to 10. Next, at the timing of time t1, the time control pulse shown in FIG. 20 changes from the H level to the L level and the operation result transmission transistor (PMTT3) is turned on, but the operation result transmission transistor (PMTT1) is off. , The voltage level of each node (N1 to N7) does not change, and the gate circuit (GT5) also maintains the ON state. Table 4 shows ON / OFF states of the operation result transmission transistors (PMTT1 to PMTT3) immediately after the time t1 and voltage levels of the nodes (N1 to N7).

[0056]

[Table 4]

Similarly, at the timings of times t2 and t3, since the operation result transmission transistor (PMTT1) is off, the voltage levels of the nodes (N1 to N7) do not change and the gate circuit (GT5) is on. To maintain. Each operation result transmission transistor ((P
Tables 5 and 6 show ON / OFF states of the MTT1 to PMTT3) and the voltage levels of the nodes (N1 to N7).

[0058]

[Table 5]

[0059]

[Table 6]

At the timing of time t4, the time control pulse shown in FIG. 20 changes from H level to L level, the operation result transmission transistor (PMTT1) turns on, and each node (N1, N2, N3) changes to H level. However, since the time control pulse shown in FIG. 20 is at the H level, the voltage level of each node (N4 to N7) does not change.
The gate circuit (GT5) also maintains the ON state. Time t4
Immediately after each operation result transmission transistor (PMTT1 to PMTT1
TT3) ON / OFF state and each node (N1 to N
Table 7 shows the voltage levels of 7).

[0061]

[Table 7]

At the timing of time t5, the time control pulse shown in FIG. 20 changes to the L level, so that the node (N4) changes to the H level and the node (N5) changes to the L level. Changes to L level and the node (N7) changes to H level. Therefore, the gate circuit (GT5) is turned off, and the potential of the drain signal line (D) becomes the potential of the voltage level immediately before time t5. Immediately after time t5, each operation result transmission transistor ((PMTT1
To PMTT3) on / off state and each node (N
Table 8 shows voltage levels 1 to N7).

[0063]

[Table 8]

Thereafter, the reset pulse becomes H level, and the on / off state of each operation result transmission transistor (PMTT1 to PMTT3) and the voltage level of each node (N1 to N7) until the reset pulse is set to the initial state. Is
Regardless of the voltage level of the time control pulse shown in FIG.
This state is maintained. Therefore, by writing the potential of the drain signal line (D) to the pixel before the reset pulse goes to the H level, the gray scale voltage corresponding to the display data is written to the pixel. Note that time t
6, each operation result transmission transistor (PMTT immediately after t7)
Tables 9 and 10 show the on / off states of the first to third PMTs 3 to 1 and the voltage levels of the nodes (N1 to N7).

[0065]

[Table 9]

[0066]

[Table 10]

During the above operation, scanning of the horizontal shift register circuit 121 is performed, and data of the next scanning line (FIG. 1)
9 (b) is held in the memory capacity (C1, C2, C3) for each video signal line (D). Thereafter, the gray scale voltage shown in FIG. 18 is returned to the voltage of V0, and again at time t0.
The scan from t to t7 is repeated. At this time, the vertical scanning circuit 130 selects the next scanning line.

In the present embodiment, the gate circuit (GT5)
, Except for the nodes (N2, N3, N4) for applying the control voltage to the components (eg, PM
OS operation transistors (PMTG1, PMTT1), N
MOS operation transistors (NMTG1, NMTT1),
Since the memory capacity (CM1), the negative power supply (Vss), and the voltage bus line 151) can be formed independently, wiring or the like extending between each bit is not required. Therefore, the liquid crystal display module of the present embodiment is particularly suitable for a small liquid crystal display device requiring a high-density layout. For example, if a selection circuit or the like is to be built in a 0.7 inch (17.78 mm diagonal) XGA type liquid crystal display panel, the layout (pitch (width)) needs to be about 14 μm. However, for example, when the display data is 8 bits and a 2 μm line-and-space wiring is used, in the circuit configuration shown in FIG. 8, the first selection circuit 223 and the second selection circuit 224 Although only the wiring to the line requires 32 μm, the layout becomes impossible, but it can be easily realized with the circuit configuration of the present embodiment. Further, in the present embodiment, the case where the display data is 3 bits has been described as an example, but a component (for example, P
MOS transistors (PMTG1, PMTT1), NM
Even if the number of bits of display data is increased, it is possible to easily cope with an increase in the number of bits of the display data only by adding the OS transistors (NMTG1 and NMTT1), the memory capacity (CM1), the negative power supply (Vss), and the time control signal line). For example, even if the display data is 8 bits, the total number of transistors is 1
Only 50 drain signal lines (D) are required.

Further, in the present embodiment, by reversing the wiring of the time control signal lines (161 to 169) and the power supply line of the negative power supply potential (Vss), the p-type field effect transistors (PMTT1, PMTT1, PMTT2, PMTT
It is also possible to replace 3) with an n-type field effect transistor. However, as in the present embodiment, P
MOS transistors (PMTT1, PMTT2, PMT
T3), the nodes (N2, N3, N
4) In the floating state, even if charge pumping occurs under the gate electrode of the field-effect transistor due to on / off of the field-effect transistor,
Direction to lower the potential of the nodes (N2, N3, N4),
In other words, only the L level becomes stronger, so that the ON level of the gate circuit (GT5) does not become an unstable element, and malfunction of the gate circuit (GT5) can be prevented. Conversely, when the nodes (N2, N3, N4) become H level, the potential of the nodes (N2, N3, N4) is lowered. In this case, the replenishment from the upper bit side is performed periodically. Therefore, unstable operation can be avoided by setting each node capacitance to an appropriate value. In the case where the control voltage for turning off the gate circuit (GT5) is an H-level voltage, the circuit configuration using the p-type field-effect transistor transmits the voltage to the next node without lowering the threshold voltage. Can be
Since the operation is performed in the discharge mode, there is an advantage that the charging speed of the next node is high. The power supply voltage (VD
D) Input-side field effect transistor (PMOS (PM
For the same reason, TIN1) is a p-type field-effect transistor.

In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, and as a result, an afterimage phenomenon is caused and the life of the liquid crystal layer is shortened. To prevent this, this TFT
In the liquid crystal display module of the system, the voltage applied to the liquid crystal layer is converted into an alternating voltage at a certain time interval, that is, the voltage applied to the pixel electrode is changed based on the voltage applied to the common electrode.
The voltage is changed to the positive voltage side / negative voltage side at regular intervals. Hereinafter, the AC driving method in the TFT liquid crystal display module of each of the above embodiments will be described. As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known. The common inversion method is a method of alternately inverting the voltage applied to the common electrode (ITO2) and the voltage applied to the pixel electrode (ITO1) to positive and negative. The common symmetry method refers to a method in which the voltage applied to the common electrode (ITO2) is kept constant, and the voltage applied to the pixel electrode (ITO1) is alternated with reference to the voltage applied to the common electrode (ITO2). The common symmetric method is excellent in terms of low power consumption and display quality.

In the liquid crystal display module of the present embodiment, both types can be supported by changing the polarity of the gradation voltage supplied from the power supply circuit 12.
For example, as shown in FIG. 21, a positive gradation voltage is applied to odd lines of odd frames, a negative gradation voltage is applied to even lines of odd frames, and a negative gradation voltage is applied to odd lines of even frames. Even in the case where the AC driving method of applying the gray scale voltage and the positive gray scale voltage to the even lines of the even frame is adopted, the power supply circuit 12 supplies the first selection circuit 123 or the selection circuit 324 with the gray scale voltage. , The positive or negative gray scale voltage (VA1 to V
A8) can be easily dealt with by supplying them. One of the common symmetry methods is a dot inversion method shown in FIG. In the dot inversion method, as shown in FIG. 22, for example, in an odd line of an odd frame, a negative gradation voltage (indicated by ● in FIG. 22) is applied to an odd drain signal line (D). , A positive-polarity gray scale voltage (indicated by ○ in FIG. 22) is applied to the even-numbered drain signal lines (D). Further, in the even-numbered lines of the odd-numbered frame, a positive gradation voltage is applied to the odd-numbered drain signal lines (D).
Further, a negative gray scale voltage is applied to the even-numbered drain signal lines (D). The polarity of each line is inverted for each frame. That is, as shown in FIG. 22, in the odd lines of the even frames, the odd drain signal lines (D)
, And a negative gray scale voltage is applied to the even-numbered drain signal line (D). In the even lines of the even frame, a negative gradation voltage is applied to the odd drain signal lines (D), and a positive gradation voltage is applied to the even drain signal lines (D). By using the dot inversion method, the voltages applied to the adjacent drain signal lines (D) have opposite polarities, so that the current flowing through the common electrode (ITO2) or the gate electrode of the thin film transistor (TFT) is not adjacent to each other. It is possible to cancel each other and reduce power consumption. In addition, the common electrode (IT
Since the current flowing through O2) is small and the voltage drop does not increase, the voltage level of the common electrode (ITO2) is stabilized,
Deterioration of display quality can be minimized.

In the liquid crystal display modules of the first to third embodiments, when the dot inversion method is adopted, as shown in FIG. 23, two voltage bus lines (171, 171) are used.
172), and an odd-numbered selection circuit (a gray scale in 123A shown in FIG. 23A) in the selection circuit for each drain signal line (D) in the first selection circuit 123 from one voltage bus line 171. A voltage is supplied, and an even-numbered selection circuit (123B shown in FIG. 23) of the selection circuits for each drain signal line (D) in the first selection circuit 123 is supplied from the other voltage bus line 172. The positive or negative gray scale voltage may be supplied from the power supply circuit 12 to the two voltage bus lines for each scanning line. In the liquid crystal display module according to the fourth embodiment, two voltage bus lines are provided in the same manner as described above. Turn Of the selection circuit for each drain signal line (D) in the selection circuit 324 from the other voltage bus line to the even-numbered selection circuit. In this case, for each scanning line, a positive or negative gradation voltage may be supplied from the power supply circuit 12 to two voltage bus lines. Although the embodiment in which the horizontal scanning circuit 120 and the vertical scanning circuit 130 are incorporated in a liquid crystal display panel has been described, the present invention is not limited to this.
The vertical scanning circuit 130 may be provided outside the liquid crystal display panel. As described above, the invention made by the inventor has been specifically described based on the embodiment of the present invention. However, the present invention is not limited to the embodiment of the invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made in.

[0073]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, it is possible to reduce the number of signal lines and the total number of transistors in the horizontal scanning driving unit, and to reduce the circuit scale of the horizontal scanning driving unit. (2) According to the present invention, it is possible to reduce the area occupied by the horizontal drive unit when the horizontal drive unit path is incorporated in the liquid crystal display element. (3) According to the present invention, the size of the liquid crystal display device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall schematic configuration of a TFT-type liquid crystal display module according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of an example of the liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 3 is a circuit diagram showing a circuit configuration of the digital signal memory array shown in FIGS. 1 and 2;

FIG. 4 is a circuit diagram showing a circuit configuration of a selection circuit per drain signal line (D) of the first selection circuit shown in FIGS. 1 and 2;

FIG. 5 is a waveform diagram showing a change in voltage level within one scanning period in gradation voltages (VA1 to VA8) supplied to each voltage bus line shown in FIG.

FIG. 6 is a circuit diagram showing a circuit configuration of a selection circuit per one drain signal line (D) of the second selection circuit shown in FIGS. 1 and 2;

FIG. 7 is a waveform diagram showing a waveform of a time control pulse (,,) shown in FIG.

FIG. 8 is a circuit diagram showing a circuit configuration of a first selection circuit and a second selection circuit that have been examined by the present inventors before the present invention.

9 is a waveform diagram showing waveforms of time control signals (TP1 to TP8) supplied to each time control signal line shown in FIG.

FIG. 10 is a circuit diagram showing a circuit configuration of a selection circuit per drain signal line (D) of a second selection circuit in a TFT liquid crystal display module according to a second embodiment of the present invention.

11 is a time control pulse (,,,,) shown in FIG.
FIG.

FIG. 12 is a circuit diagram showing a circuit configuration of a selection circuit per drain signal line (D) of a second selection circuit in a TFT liquid crystal display module according to a third embodiment of the present invention.

FIG. 13 is a circuit diagram showing another circuit configuration that can be employed as the second selection circuit in the present invention.

FIG. 14 is a block diagram showing an overall schematic configuration of a TFT type liquid crystal display module according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing a circuit configuration of a horizontal scanning circuit when display data is 3 bits in Embodiment 4 of the present invention.

FIG. 16 is a circuit diagram showing a circuit configuration of a selection circuit when display data is 3 bits in the fourth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a circuit configuration of a selection circuit when display data is 3 bits in the fourth embodiment of the present invention.

18 is a time control pulse (,,,,) shown in FIG.
3A and 3B are waveform diagrams showing the waveforms of FIG.

FIG. 19 is a waveform chart showing voltage levels of display data according to the fourth embodiment of the present invention.

FIG. 20 shows each PMOS in the fourth embodiment of the present invention.
FIG. 3 is a waveform diagram showing ON / OFF states of (PMTT1 to PMTT3) and potentials of respective nodes (N1 to N4).

FIG. 21 is a diagram illustrating an example of an AC driving method according to each of the embodiments of the present invention.

FIG. 22 is a diagram for explaining the polarity of a gray scale voltage output to a drain signal line (D) when a dot inversion method is used as a driving method of a liquid crystal display module.

FIG. 23 is a block diagram showing a circuit configuration for adopting the dot inversion method in each embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10: liquid crystal display panel (liquid crystal display element), 11: display control device, 12: power supply circuit, 110: display unit, 120: vertical pixel line selection circuit (horizontal scanning circuit), 121: memory address selection circuit (horizontal shift register) Circuit), 12
2. Digital signal memory array, 122A: first latch circuit, 122B: second latch circuit, 123, 223
... First selection circuit (upper bit selection circuit), 123A,
123B: selection circuit for one drain signal line (D) in the first selection circuit 123; 124, 224: second selection circuit (lower bit selection circuit); 130: horizontal pixel line selection circuit (vertical scanning circuit) , 131-138, 151,
171,172... Voltage bus lines, 141 to 143, 1
61-169, 241-248 ... time control signal line, 15
2 ... operation result signal line, 324 ... selection circuit, 325 ... display data operation circuit, 326 ... gradation voltage output circuit, 328 ...
Display data holding circuit, 329... Arithmetic circuit, 330 (1)
To 330 (3): calculation result transmission circuit, G: gate signal line (scanning signal line or horizontal signal line), D: drain signal line (video signal line or vertical signal line), TFT: thin film transistor, ITO: pixel electrode, ITO2: common electrode (counter electrode), CLC: liquid crystal capacitance, C0: capacitance element, CN: common signal line, CSTG: storage capacitance, GT: gate circuit, P
T, PMT, PMTIN1, PMTT, PMTG, PM
TAG: p-type MOS transistor, NT, NTM, NM
TM, NMTR1, NMTG, NMTAG, NMTG
... n-type MOS transistor, NAND1 ... NAND circuit,
NOR1: NOR circuit. CM1, CM2, CM3... Memory capacity, DD1 to DD3.

Continued on the front page (72) Inventor Hideo Sato 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Kageyama 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd.

Claims (21)

[Claims] 1. A liquid crystal display device comprising two substrates, one of which is transparent to each other, and a liquid crystal layer sandwiched between the two substrates, wherein a plurality of pixels, and a video signal voltage are applied to the plurality of pixels. A plurality of video signal lines for applying an image signal, a driving unit for supplying a video signal voltage to the plurality of video signal lines, a power supply unit for supplying a plurality of gradation voltages to the driving unit, and controlling the driving unit. A liquid crystal display device comprising: display control means, wherein the display control means supplies at least n-bit display data and p kinds of time control signals to the driving means, To the driving means, 2 ^m gradation voltages whose voltage levels are different and whose voltage level changes with time within one scanning period are supplied to the driving means, and the driving means transmits n gray scale voltages transmitted from the display control means. Bit display data Storage means for storing data, said provided for each video signal line, in accordance with the bit values of the m-bit display data of n bits stored in said storage means, 2 ^m pieces to be supplied from the power supply unit Selecting means for selecting any one of the gray scale voltages of each of the video signal lines, according to each bit value of p bits of the n-bit display data stored in the storage means. And p switching means for selecting a time control signal or a first level voltage supplied from the display control unit, and each output voltage of the p switching means provided for each of the video signal lines. Logic circuit means for changing the output state in the case of the voltage of the first level; and a logic circuit provided for each of the video signal lines and selected by the selection means in accordance with a change in the output state of the logic circuit means. To adjust the voltage And an output circuit for supplying a voltage level when the output state of the logic circuit means changes as a video signal voltage to each of the video signal lines. 2. A 2 ^m-number of gray-scale voltages supplied to the drive means from the power supply unit, that the voltage level in one scanning period is stepped voltage changes to 2 ^p steps The liquid crystal display device according to claim 1, wherein: 3. The p time control signals supplied from the display control means to the drive means are pulse signals in which a first level voltage and a second level voltage are alternately repeated, When the period of the pulse signal selected by the switching means according to the value of the least significant bit of the display data is k, the value of the i-th (i = 2,..., P) bit of the display data is 3. The liquid crystal display device according to claim 1, wherein a period of the pulse signal selected by the switching unit is k × 2 ⁽ⁱ⁻¹⁾ . 4. A plurality of pixels provided in a matrix, a plurality of video signal lines for applying a video signal voltage to pixels in a column or row direction of the plurality of pixels, and a video signal voltage applied to the plurality of video signal lines. A liquid crystal display device comprising: a driving unit that supplies a plurality of gradation voltages to the driving unit; and a display control unit that controls the driving unit. Supplying at least n-bit display data and n time control signals to the driving means, wherein the power supply unit changes the voltage level of the driving means with time within one scanning period. The driving means is a storage means for storing n-bit display data transmitted from the display control means, and is provided for each video signal line, and is stored in the storage means. N switching means for selecting a time control signal or a first-level voltage supplied from the display control unit according to each bit value of the n-bit display data provided for each of the video signal lines An operation result transmitting means for changing an output state when each output voltage of the n switching means is a first level voltage; and an output of the operation result transmitting means provided for each of the video signal lines. Output circuit means for supplying, to each of the video signal lines, a voltage level at the time of an output state change of the operation result transmission means in a gradation voltage supplied from the power supply unit in accordance with a state change, as a video signal voltage; A liquid crystal display device comprising: 5. The storage device according to claim 4, wherein the storage means is n capacitance elements that hold voltages of respective bit values of the n-bit display data transmitted from the display control means. Liquid crystal display device. 6. The gray scale voltage supplied from the power supply unit to the driving unit is a step-like voltage whose voltage level changes in 2 ⁿ steps within one scanning period. 7. The liquid crystal display device according to claim 4 or 6. 7. The n time control signals supplied from the display control means to the driving means are pulse signals in which a first level voltage and a second level voltage are alternately repeated, When the period of the pulse signal selected by the switching means in accordance with the value of the least significant bit of the display data is k, it is determined according to the bit value of the ith (i = 2,..., N) bit of the display data. 7. The liquid crystal display device according to claim 4, wherein a period of the pulse signal selected by the switching means is k × 2 ⁽ⁱ⁻¹⁾ . 8. A liquid crystal display device comprising two transparent substrates opposed to each other and a liquid crystal layer sandwiched between the two substrates, wherein a plurality of pixels and a video signal voltage are applied to the plurality of pixels. A plurality of video signal lines, a driving circuit for supplying a video signal voltage to the plurality of video signal lines, a plurality of display data lines for supplying display data to the driving circuit, and a plurality of grayscale voltages for the driving circuit A driving circuit, wherein the driving circuit is provided for each of the display data lines, and the plurality of displays perform calculations based on display data supplied by the display data lines. Any one of a plurality of gray scale voltages supplied by the gray scale voltage line according to a calculation result of the data calculation circuit and the display data calculation circuit;
A grayscale voltage output circuit that outputs two grayscale voltages to the video signal line as video signal voltages; and a calculation result transmission line that transmits a calculation result of each of the display data calculation circuits to the grayscale voltage output circuit, The plurality of display data operation circuits, the gradation voltage output circuit, and the operation result transmission line are provided for each of the video signal lines, and the plurality of display data operation circuits, the gradation voltage output circuit, The liquid crystal display device, wherein the circuit is connected in series by a calculation result transmission line for each of the video signal lines. 9. The liquid crystal display device according to claim 8, wherein the grayscale voltage line supplies a plurality of grayscale voltages with one grayscale voltage line. 10. The liquid crystal display device according to claim 8, wherein the plurality of display data operation circuits are formed in a line on an extension of the video signal line. 11. A display data operation circuit other than the display data operation circuit at one end of the plurality of display data operation circuits formed in a line is formed between adjacent display data lines. The liquid crystal display device according to claim 10. 12. Two substrates facing each other, and
A liquid crystal display device having a liquid crystal layer sandwiched between two substrates, a plurality of pixels, a plurality of video signal lines for applying a video signal voltage to the plurality of pixels, and a video signal voltage to the plurality of video signal lines. A plurality of display data lines for supplying display data to the drive circuit; a grayscale voltage line for supplying a grayscale voltage that changes periodically with time to the drive circuit; A liquid crystal display device having a plurality of control signal lines for supplying a pulse signal, wherein the drive circuit is provided for each of the display data lines, and the display data supplied by the display data lines; A plurality of arithmetic circuits for performing an arithmetic operation on a pulse signal supplied by a corresponding one of the control signal lines among the control signal lines, and a level supplied by the gradation voltage line according to a value of the plurality of arithmetic circuits. Of regulating voltage Selecting means for selecting any one of the gradation voltages, wherein the plurality of arithmetic circuits and the selecting means are provided for each of the video signal lines, and the display data is provided for each of the display data lines. A liquid crystal display device stored in storage means provided in the liquid crystal display device. 13. The liquid crystal display device according to claim 12, wherein a voltage level of the gray scale voltage changes stepwise with time. 14. The liquid crystal display device according to claim 12, wherein the plurality of storage units are formed in a line on an extension of each of the video signal lines. 15. The storage means according to claim 14, wherein storage means other than the storage means at one end of the plurality of storage means formed in a row are formed between adjacent display data lines. Liquid crystal display device. 16. The liquid crystal display device according to claim 12, wherein the selection unit outputs the selected gradation voltage to the video signal line. 17. Two substrates opposed to each other, and
A liquid crystal display device having a liquid crystal layer sandwiched between two substrates, a plurality of pixels, a plurality of video signal lines for applying a video signal voltage to the plurality of pixels, and a video signal voltage to the plurality of video signal lines. A driving circuit for supplying n-bit display data to the driving circuit; and a gray-scale voltage that periodically changes in 2 ⁿ stages with time to the driving circuit. What is claimed is: 1. A liquid crystal display device comprising: a gray scale voltage line; and n control signal lines for supplying, to the drive circuit, data whose value changes in accordance with a change in the gray scale voltage. N arithmetic circuits provided for each of the display data lines and performing an arithmetic operation on display data supplied by the display data line and data supplied by a corresponding control signal line among the n control signal lines; Operation result of n operation circuits An output circuit that selects any one of the gray scale voltages supplied by the gray scale voltage line and outputs the selected gray scale voltage as a video signal voltage. A liquid crystal display device, wherein the output circuit is provided for each of the video signal lines, and the n arithmetic circuits are provided on an extension of each of the video signal lines. 18. The semiconductor device according to claim 17, further comprising: n switching elements connected to outputs of the n arithmetic circuits, and an operation result transmission line connecting the n switching elements in series. 3. The liquid crystal display device according to 1. 19. The n arithmetic circuits are formed in a row, and arithmetic circuits other than the arithmetic circuit at one end of the n arithmetic circuits formed in the row are formed between adjacent display data lines. The liquid crystal display device according to claim 17, wherein the liquid crystal display device is provided. 20. The output circuit includes a gate circuit that outputs the gray scale voltage to the video signal line, and the gate circuit turns off after outputting the selected gray scale voltage to the video signal line. The liquid crystal display device according to any one of claims 17 to 19, wherein: 21. The output circuit includes a gate circuit that outputs the gray scale voltage to the video signal line, wherein the gate circuit is turned on / off by a signal on the operation result transmission line. The liquid crystal display device according to any one of claims 17 to 20, wherein: