TWI501210B - Device and method for driving display panel - Google Patents

Description

Method and device for driving display panel

Exemplary embodiments of the present invention relate to circuits and methods for driving a flat display panel, and more particularly to an efficient structure of a data driver for applying image data to a display panel in the form of voltage or current. A data drive can be referred to as a row or drive.

The present application claims priority to Korean Patent Application No. 10-2009-0088640 and No. 10-2009-0101398, filed on Sep. 18, 2009, and on The manner is incorporated herein.

The data driver of the flat display panel converts the digital video data into analog video data and transmits the analog video data to the display panel. Digital to analog converters (DACs) occupy a large area of the overall structure of the data drive, and there have been different attempts to reduce the area of the digital to analog converter. One of them is a lamp-type digital to analog converter using time-varying signals (TVS), which is considered as an alternative.

The lamp type digital to analog converter is driven by receiving a time varying signal representing a plurality of gray scale voltages and selecting and outputting a specific gray scale voltage.

1A is a block diagram showing the main portions of a conventional driver using a single time varying signal. A driver using a single time-varying signal is disclosed in U.S. Patent No. 5,440,256, entitled "Dual Mode Track and Hold Drivers for Active LCD's".

Referring to FIG. 1, a driver using a single time varying signal includes a single TVS generator 110, an N-bit switch 120, an N-bit pulse signal generator 130, and a channel buffer 140. The single TVS generator 110 produces a single time varying signal that sequentially represents all gray scale voltages for each cycle of a line time. The N-bit switch 120 receives a single time varying signal and performs switching on the single time varying signal to select a gray scale voltage corresponding to the video material. The N-bit pulse signal generator 130 controls the N-bit switch 120. The channel buffer 140 outputs the output of the N-bit switch 120 via a source line.

The N-bit switch 120, the N-bit pulse signal generator 130, and the channel buffer 140 are some of the constituent elements of the channel block of the driver, and are supplied to each of the channel blocks constituting the driver. The single TVS generator 110 is shared by all channels.

Figure 1B illustrates the operation of a driver using a single time varying signal. The single TVS generator 110 synchronizes with a clock signal and produces a time varying signal 160 that sequentially represents 2 ^N gray scale voltages for one line time. The time varying signal 160 is input to the N-bit switch 120 of each channel. The N-bit pulse signal generator 130 generates an N-bit pulse signal 170. The N-bit switch 120 selects a specific gray-scale voltage of the gray-scale voltage of the time-varying signal 160 by turning on/off according to one of the 2 ^N pulse signals. The gray scale voltage signal 180 selected by the N-bit switch 120 is transmitted to the source line of the display panel via the channel buffer 140.

Because the digital to analog converter uses a single time varying signal to sequentially represent 2 ^N gray scale voltages per line time, the digital to analog converter lacks time to charge the panel load. Therefore, there is an error between the voltages of the pixels. In addition, when the pulse signal generators of all the channels operate in synchronization with a clock signal, a large amount of power is consumed. Also, since the switch and the N-bit pulse signal generator are added to each channel, the channel area is increased. These problems become more serious when the display device has a high gray scale, high definition, and large size.

2A is a block diagram showing the main portions of a conventional driver using a plurality of time varying signals. A driver using a plurality of time-varying signals is disclosed in Korean Patent No. 727,410 entitled "Digital-to-Analog Converting Circuit and Method for Driving a Flat Display Panel Using Multi-Ramp Signals".

A driver using a plurality of time varying signals is proposed to solve the above mentioned problems. The driver includes a multi-TVS generator 210, an M-bit switch 220, an (N-M) bit pulse signal generator 230, and a channel buffer 240.

The multi-TVS generator 210 divides one of the gray scale voltage regions into (1/2 ^M ) gray scale voltage regions for each cycle of one line time and generates a plurality of (2 ^M ) time-varying signals. The M-bit switch 220 receives the plurality of time-varying signals and performs switching on the plurality of time-varying signals to select a gray-scale voltage corresponding to the video data. The channel buffer 240 outputs the output of the M-bit switch 220 to the source line of the display panel. Herein, N and M are positive integers and N is greater than M (N>M).

The M-bit switch 220, the (N-M) bit pulse signal generator 230, and the channel buffer 240 are some of the constituent elements of the channel block of the driver, and are supplied to each of the channels constituting the driver. The multiple TVS generator 210 is shared by all channels.

Figure 2B illustrates the operation of a driver using a plurality of time varying signals.

The multiple TVS generator 210 generates a plurality of time varying signals 260. Since a plurality of ( ^2M ) time varying signals 260 represent all gray scale voltages in regions, each time varying signal 260 sequentially represents 2 ^NM gray scale voltages for one cycle of one line time.

The plurality of (2 ^M ) time varying signals 260 are input to the M-bit switch 220 of each channel. (NM) bit pulse signal generator 230 generates pulse signals 270 2 ^NM. The M-bit switch 220 selects a particular gray-scale voltage of the gray-scale voltage of the time-varying signal by turning on/off according to one of the pulse signals in the 2 ^NM pulse signals 270. One of the gray scale voltage signals 280 selected by the M-bit switch 220 is transmitted to the source line of the display panel via the channel buffer 240.

When using multiple time-varying signals, the display panel charging time is increased by up to 2 ^M. Therefore, it is possible to reduce the error between the pixel voltages. Moreover, since the clock frequency is as slow as 2 ^M times, power consumption can be reduced. In addition, since the circuit of the (NM) bit pulse signal generator 230 is reduced to (NM) bits, the channel area is also reduced.

However, each channel includes a counter formed by a plurality of flip-flops and an (N-M) bit pulse signal generator 230 formed of a plurality of logic circuits, which still occupy a large area. In addition, when all (N-M) bit pulse signal generators operate in synchronization with the clock signal, a large amount of power is still consumed.

One embodiment of the present invention is directed to an apparatus and method for driving a display panel having a significantly reduced size.

Another embodiment of the present invention is directed to an apparatus and method for driving a display panel having low power consumption.

Another embodiment of the present invention is directed to an apparatus and method for easily improving a display panel for driving video quality.

The other objects and advantages of the invention will be apparent from the description and appended claims. It is apparent to those skilled in the art that the objects and advantages of the present invention can be realized by the claimed means and combinations thereof.

According to an embodiment of the invention, an apparatus for driving a display panel includes: a time varying signal (TVS) generator configured to generate a time varying signal group; a common pulse signal generator, grouped State to generate a plurality of pulse signals; a selector configured to receive the time varying signal, the plurality of pulse signals and video data and select a gray scale voltage corresponding to the video data; and a buffer Configured to buffer and transfer one of the selector outputs. Herein, the selector and the buffer are provided to each of the plurality of channels, and the time varying signal and the plurality of pulse signals are commonly input to the selector.

The TVS generator may divide a range of all gray scale voltages into a plurality of gray scale voltage ranges and generate the time varying signal group, the time varying signal groups having a plurality of times each corresponding to each gray scale voltage range Change the signal. The TVS generator can generate the set of time varying signals having a single time varying signal that sequentially represents one of a range of gray scale voltages.

The common pulse signal generator can include a register configured to control an on/off time ratio of one of each pulse signal.

In accordance with another embodiment of the present invention, an apparatus for driving a display panel includes a time varying signal (TVS) generator configured to generate a plurality of time varying signals; a common pulse signal generator Configuring to generate a plurality of pulse signals; a sampler configured to sample and output video data; a pulse selector configured to select the source based on one of the sampled video data Any one of a plurality of pulse signals; and a TVS selector configured to select any one of the plurality of time-varying signals based on a portion of the meta-data in the sampled video material, One of the selected pulse signals enables switching of the selected time varying signal during the duration and transmits the switched time varying signal.

In accordance with yet another embodiment of the present invention, an apparatus for driving a display panel includes: a TVS generator configured to generate a single time varying signal; a common pulse signal generator configured to generate a plurality of a pulse signal; a sampler configured to sample and output video data; a pulse selector configured to select any one of the plurality of pulse signals based on the sampled video data; A switch configured to switch the time varying signal during a duration of one of the selected pulse signals and to transmit the switched time varying signal.

According to still another embodiment of the present invention, a digital to analog conversion method includes: selecting any one of a plurality of pulse signals based on a piece of meta-information in the sampled video data; based on the sampled video data An upper portion metadata for selecting any one of a plurality of time varying signals; and switching the selected time varying signal and transmitting the switched time varying signal during an enabled duration of the selected pulse signal.

According to still another embodiment of the present invention, a digital to analog conversion method includes: selecting any one of a plurality of pulse signals based on the sampled video data; and switching a single one during an enabled duration of the selected pulse signal The time varying signal and the switched time varying signal is transmitted to a channel buffer.

Exemplary embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed to those skilled in the art. Throughout the invention, the same reference numerals refer to the same parts throughout the various figures and embodiments of the invention. The drawings are not necessarily to scale unless the When the first layer is referred to as "on the second layer" or "on the substrate", it refers not only to the condition that the first layer is directly formed on the second layer or the substrate but also refers to the presence of a third layer. The condition between the first layer and the second layer or substrate.

Hereinafter, embodiments of the present invention are described in the present specification, and the technology of the present invention is applied to a liquid crystal display (LCD) to reduce the area and power consumption of the liquid crystal display. However, the technique of the present invention can be applied to all drivers of a flat display device such as a field emission display (FED), an electroluminescence display (ELD), a plasma display panel (PDP), and the like.

First embodiment

3 is a block diagram showing a driver of a display panel using a multi-time varying signal (TVS) generator and a common pulse signal generator in accordance with a first embodiment of the present invention.

Referring to Figure 3, the drive includes a configured to generate a plurality of time varying signal (2 ^M th) becomes much signal (TVS) generator 310 and configured to generate a plurality of different pulse width (2 ^NM two A common pulse signal generator 330 of the pulse signal. Moreover, the driver includes a selector 320 and a channel buffer 340. The selector 320 receives the plurality of (2 ^M ) time-varying signals, the plurality of (2 ^NM ) pulse signals, and the video data D<(N-1): 0> to select a gray-scale voltage corresponding to the video data. . The channel buffer 340 outputs the output of the selector 320 to the source line of the display panel. Herein, N and M are positive integers and N is greater than M (N>M). For each cycle of a line time, all regions of the gray scale voltage are divided into 2 ^M gray scale voltage regions, and each of the plurality of (2 ^M ) time varying signals is generated corresponding to each gray scale voltage range. One.

The selector 320 and the channel buffer 340 are constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. The multiple TVS generator 310 and the common pulse signal generator 330 are shared by all channels. In other words, the plurality of time varying signals and the plurality of pulse signals are commonly input to the selector 320 of each channel.

As illustrated in Fig. 3, a driver manufactured in accordance with an embodiment of the present invention does not include a pulse signal generator in each channel, but has a structure in which the common pulse signal generator 330 is shared by all channels. Therefore, it is possible to significantly reduce the wafer area of the digital to analog converter and the driver.

4 is a detailed block diagram illustrating a unit channel block to which the driver of FIG. 3 is applied.

Referring to FIG. 4, the driver includes a sampler 450, a multi-TVS generator 410, a common pulse signal generator 430, a selector 420, and a channel buffer 440.

The sampler 450 performs sampling on the N-bit video data D<(N-1):0>. The multiple TVS generator 410 generates a plurality of ( ^2M ) time varying signals. The common pulse signal generator 430 generates a plurality of (2 ^NM ) pulse signals having different pulse widths. The selector 420 receives the plurality of (2 ^M ) time-varying signals, the plurality of (2 ^NM ) clock signals, and the sampled video data, and selects any one of the plurality of time-varying signals, and outputs the selected Time-varying signal. The channel buffer 440 outputs the output of the selector 420 to the source line of the display panel.

The sampler 450, the selector 420, and the channel buffer 440 are constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. The multiple TVS generator 410 and the common pulse signal generator 430 are shared by all channels.

The selector 420 includes a pulse selection unit 422, a level shifting unit 424, and a TVS selection unit 426. The pulse selection unit 422 selects one of 2 ^NM pulse signals based on the lower (NM) bits of the sampled video material. The level shifting unit 424 shifts the upper M bits of the sampled video material and the output pulse signal of one of the pulse selecting units 422. The TVS selection unit 426 selects any of the 2 ^M time varying signals based on the output of the level shifting unit 424. Herein, N and M are positive integers and N is greater than M (N>M).

The sampler 450 includes a shift register unit 452 and a sample/hold latch unit 454. Since the circuit configuration of the shift register unit 452 and the sample/hold latch unit 454 is well known, a detailed description thereof will be omitted for the sake of brevity.

FIG. 5 is a detailed block diagram illustrating the selector 420. In this embodiment, the driver uses two time varying signals and the driver is a 6 bit digital to analog converter. That is, it is assumed that the integer N is 6, and the integer M is 1.

The pulse selection unit 422 can be formed as a 5-bit decoder that receives the lower 5-bit data D<4:0> in the sampled video data D<5:0>, and selects 32 pulse signals <31:0. One of > and output the selected pulse signal.

The TVS selection unit 426 includes a 1-bit decoding element 426A and a switch element 426B. The 1-bit decoding element 426A selects one of the two time-varying signals TVS<0> and TVS<1> based on the upper 1-bit data D<5> obtained from the level shifting unit 424. Switcher element 426B performs switching only in the enable of the pulse signal obtained from level shifting unit 424 (which becomes a logic high level) and transmits the output of 1-bit decoding element 426A to channel buffer 440.

In the final analysis, since all gray scale voltages are equally divided into two gray scale voltage regions and one of two time varying signals TVS<0> and TVS<1> respectively representing two gray scale voltage regions is selected, A preferred gray scale voltage region is selected and a target gray scale voltage is selected based on the pulse width of the pulse signal.

As described above, the digital to analog conversion method according to an embodiment of the present invention includes: selecting any one of a plurality of pulse signals based on a lower portion of the sampled video data; based on the sampled video data The upper portion element selects any one of a plurality of time varying signals; and transmits the selected time varying signal to the channel buffer by performing a switch on the selected time varying signal during an enabled duration of the selected pulse signal. Herein, for each cycle of one line time, all gray scale voltages are equally divided into 1/2 ^M gray scale voltage regions, and a plurality of (2 ^M ) time varying signals are generated corresponding to the gray scale voltage range. The plurality of pulse signals are a plurality (2 ^NM ) of pulse signals having different enable durations (which are pulse widths) within one cycle of one line time.

6 is a timing diagram showing the on/off action time ratio of the common pulse signal PULSE<(2 ^NM -1):0> according to an embodiment of the present invention.

One cycle of one line time is divided into a plurality of durations T1 to T (2 ^NM ), and each duration is the time at which the corresponding gray scale voltage arrives. In the embodiment shown in Figure 6, each pulse signal is a signal that is enabled from the initial time to the moment when the corresponding gray scale voltage is reached (which becomes a logic high level).

A digital to analog converter using a time varying signal requires a longer charging time in the initial duration T1 of one line time than in other durations of one line time, since a large width voltage is required in the initial duration T1. Also, after the initial time T1, sufficient charging time for the channel buffer to operate the display panel is required. When the charging time is not long enough, an offset occurs and thus the video quality can be deteriorated. In order to prevent deterioration of video quality, the pulse signal generator of the driver manufactured according to an embodiment of the present invention can independently set the time for each duration T1 to T (2 ^NM ).

Herein, the rate of voltage change according to the time of the time-varying signal is interlocked with the duration T1 to T(2 ^NM ) and varies based on the duration T1 to T(2 ^NM ). By this method, the problem of video quality can be solved.

FIG. 7 is a detailed block diagram illustrating the common pulse signal generator 430.

Referring to FIG. 7, the common pulse signal generator 430 includes a counter 431, a register 432, an adder 433, and a compare and flip-flop unit 434.

The counter 431 outputs the count signal CNT_OUT which is increased in synchronization with the clock CLOCK, and is reset by the reset signal RESET every cycle of one line time. The register 432 stores signals T1 to T (2 ^NM ) having time information of all durations. The adder 433 receives the signals T1 to T(2 ^NM ) from the register 432 and outputs values P1 to P(2 ^NM ) of the on-duration of the decision pulse signal, which is the high level duration. The comparator included in the compare and flip-flop unit 434 generates a flag signal when any of the values P1 to P(2 ^NM ) is the same as the count signal CNT_OUT, and the flag signal is transmitted to the flip-flop F/F. The flip-flop F/F activates a pulse signal when the count signal CNT_OUT becomes "0", and when the flag signal is generated, it deactivates the pulse signal. Therefore, the pulse signal PULSE<(2 ^NM -1): 0> is generated, and the on/off action time ratio of the pulse signal PULSE<(2 ^NM -1): 0> is controlled.

Second embodiment

The first embodiment described above describes the use of a plurality of time varying signals. Hereinafter, a second embodiment using a single time varying signal will be described. As in the first embodiment, the second embodiment to be described hereinafter uses a common pulse signal generator. The common pulse signal generator includes a register for controlling the ratio of the on/off action time of the pulse signal.

Figure 8 is a block diagram showing a driver using a single TVS generator and a common pulse signal generator in accordance with a second embodiment of the present invention.

Referring to FIG. 8, the driver includes a single TVS generator 810, a common pulse signal generator 830, a selector 820, and a channel buffer 840. Single TVS generator 810 produces a single time varying signal. The common pulse signal generator 830 generates a plurality of (2 ^N ) pulse signals having different pulse widths. The selector 820 receives the single time-varying signal, the plurality of pulse signals, and the video data D<(N-1):0>, and selects a grayscale voltage corresponding to the video data. Channel buffer 840 outputs the output of selector 820 to the source line of the display panel. In this paper, N is a positive integer. The single time varying signal is generated corresponding to all gray scale voltages of a period of one line time.

The selector 820 and the channel buffer 840 are internal constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. A single TVS generator 810 and a common pulse signal generator 830 are shared by each channel.

Figure 9 is a detailed block diagram illustrating a unit channel block to which the driver of Figure 8 is applied.

Referring to FIG. 9, the driver includes a sampler 950, a single TVS generator 910, a common pulse signal generator 930, a selector 920, and a channel buffer 940. The sampler 950 performs sampling on the N-bit video data D<(N-1):0>. Single TVS generator 910 produces a single time varying signal. The common pulse signal generator 930 generates a plurality of (2 ^N ) pulse signals having different pulse widths. The selector 920 receives the single time varying signal, the plurality of pulse signals, and the sampled video data, and selects and outputs a gray scale voltage represented by the time varying signal. Channel buffer 940 outputs the output of selector 920 to the source line of the display panel.

The sampler 950, the selector 920, and the channel buffer 940 are internal constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. A single TVS generator 910 and a common pulse signal generator 930 are shared by each channel.

The selector 920 includes a pulse selection unit 922, a level shifting unit 924, and a TVS selection unit 926. Pulse selection unit 922 selects one of a plurality of (2 ^N ) pulse signals based on the sampled video data. The level shifting unit 924 shifts the output signal of the pulse selecting unit 922, which is the selected pulse signal. The TVS selection unit 926 selects a target gray scale voltage from a single time varying signal based on the output of the level shifting unit 924.

The sampler 950 includes a shift register unit 952 and a sample/hold latch unit 954.

FIG. 10 is a detailed block diagram illustrating the selector 920 shown in FIG. In this embodiment, the driver is a 6-bit digital to analog converter. That is, it is assumed that the integer N is 6.

Referring to FIG. 10, the pulse selecting unit 922 receives over 6-bit video data D sampling of <5: 0> and selects and outputs pulse signals ²⁶ <63: 0> in one of those. Therefore, the pulse selection unit 922 can be formed as a 6-bit decoder.

The TVS selection unit 926 can be formed as a switch that performs switching on the time varying signal only during the duration of the activation of the selected pulse signal (which becomes a logic high level) obtained from the level shifting unit 924 and at that time The variable signal is transmitted to the channel buffer 940. In other words, the output of the switch selects a target grayscale value based on the pulse width of the selected pulse signal.

Herein, the common pulse signal generator 830 or 930 described in the second embodiment of the present invention may be formed to be capable of controlling the on/off action time ratio of the pulse signal. Briefly, the common pulse signal generator includes a register for setting the time of each duration of a line time and acquires the charging time during the initial duration and after the initial duration.

As described above, the digital to analog conversion method according to the second embodiment of the present invention includes: selecting any one of a plurality of pulse signals based on the sampled video data; and in an enabled duration of the selected pulse signal A single time varying signal is switched and the single time varying signal is transmitted to the channel buffer. Herein, the plurality of pulse signals are a plurality of (2 ^NM ) pulse signals having different activation durations (which are pulse widths) in one cycle of one line time.

Third embodiment

In the first embodiment and the second embodiment described above, the target gray scale voltage is determined based on the width of the time varying signal having a voltage value and the pulse signal. However, in the third embodiment to be described hereinafter, the target gray scale voltage is determined based on the width of the time varying signal having a current value and the pulse signal, and all other constituent elements and operations are the same.

Figure 11A is a block diagram illustrating a modified example of a selector of the driver shown in Figure 5.

Referring to FIG. 11A, the TVS selecting unit 426_1 includes a 1-bit decoding element 426A_1, a voltage-to-current conversion (VCC) element 426C, and a switcher element 426B_1.

The 1-bit decoding element 426A_1 selects and outputs one of the two voltage time-varying signals TVS_V<0> and TVS_V<1> based on the upper 1-bit data D<5> obtained from the level shifting unit 424. The voltage-to-current conversion element 426C generates a current level time-varying signal TVS_I<0> or TVS_I<1> from the voltage level time-varying signal TVS_V<0> or TVS_V<1> which is the output of the 1-bit decoding element 426A_1. The switcher element 426B_1 switches the output of the voltage to current conversion component 426C only during the duration of the enable of the selected pulse signal (which becomes a logic high level) obtained from the level shifting unit 424 and converts the voltage to the current conversion component 426C. The output is transferred to the channel buffer. The other constituent elements and their operations are substantially the same as the corresponding constituent elements illustrated in FIG.

Herein, the input voltage of the channel buffer is increased by up to a target voltage based on the intensity of the current and the pulse width of the pulse signal.

The digital transom conversion method according to the embodiment of the present invention described in FIG. 11A includes: selecting any one of a plurality of pulse signals based on a lower portion of the sampled video data; based on the sampled video data One of the upper portion elements selects any one of a plurality of voltage time varying signals; converts the selected voltage time varying signal into a current time varying signal; and switches the current time varying during an enable duration of the selected pulse signal The signal is transmitted to the channel buffer.

Figure 11B is a block diagram illustrating a modified example of a selector of the driver shown in Figure 10.

Referring to FIG. 11B, the TVS selection unit 926_1 includes a voltage to current conversion (VCC) element 926A and a switcher element 926B. The voltage-to-current conversion component 926A generates a current level time-varying signal TVS_I from the voltage level single time-varying signal TVS_V. The switch element 926B switches the output of the voltage to current conversion element 926A only during the duration of the enable of the selected pulse signal (which becomes a logic high level) obtained from the level shifting unit 924 and converts the voltage to the current conversion element 926A. The output is transferred to the channel buffer. Other constituent elements and their operation are substantially the same as the corresponding constituent elements shown in FIG.

The digital to analog conversion method according to the embodiment of FIG. 11B includes: selecting any one of a plurality of pulse signals based on the sampled video data; converting a single voltage time varying signal into a current time varying signal; and selecting the pulse The current time varying signal is switched during the enable duration of the signal and the current time varying signal is transmitted to the channel buffer.

Fourth embodiment

Fig. 12 is a waveform of a pulse signal applicable to the first to third embodiments according to the fourth embodiment of the present invention.

Referring to Figure 12, the figure shows that when the common pulse signal generator generates a plurality of pulse signals PULSE < (2 ^NM -1): 0>, the high duration of each pulse signal does not overlap with the high duration of the other pulse signals. . In other words, the pulse signals can be formed to be enabled in respective durations T1 to T(2 ^(NM) ) of one line time. Unlike the pulse signal illustrated in Figure 6, a pulse signal can be formed to be enabled only for a particular duration of time to reach the corresponding gray scale voltage.

According to the technique of the present invention, a pulse signal generator is not provided to each channel and a pulse signal generator is used in common for all channels. Therefore, it is possible to reduce the area and power consumption of the pulse signal generator. In general, in a data drive, the digital to analog converter takes up most of the area and power consumption.

Moreover, according to the technique of the present invention, the on/off action time ratio can be controlled. The charging time for each duration can be appropriately determined based on the on/off action time ratio, and the video quality problem caused by the lack of charging time can be solved.

While the invention has been described with respect to the specific embodiments of the present invention, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention as defined in the following claims.

110. . . Single time varying signal generator

120. . . N-bit switcher

130. . . N-bit pulse signal generator

140. . . Channel buffer

160. . . Time-varying signal

170. . . N-bit pulse signal

180. . . Gray scale voltage signal

210. . . Multiple time varying signal generator

220. . . M bit switcher

230. . . (N-M) bit pulse signal generator

240. . . Channel buffer

260. . . Time-varying signal

270. . . Pulse signal

280. . . Gray scale voltage signal

310. . . Multi-time varying signal (TVS) generator

320. . . Selector

330. . . Common pulse signal generator

340. . . Channel buffer

410. . . Multiple time varying signal generator

420. . . Selector

422. . . Pulse selection unit

424. . . Level shift unit

426. . . Time varying signal selection unit

426_1. . . Time varying signal selection unit

426A. . . 1-bit decoding component

426A_1. . . 1-bit decoding component

426B. . . Switcher component

426B_1. . . Switcher component

426C. . . Voltage to current conversion (VCC) components

430. . . Common pulse signal generator

431. . . counter

432. . . Register

433. . . Adder

434. . . Comparison and flip-flop unit

440. . . Channel buffer

450. . . Sampler

452. . . Shift register unit

454. . . Sample/hold latch unit

810. . . Single time varying signal generator

820. . . Selector

830. . . Common pulse signal generator

840. . . Channel buffer

910. . . Single time varying signal generator

920. . . Selector

922. . . Pulse selection unit

924. . . Level shift unit

926. . . Time varying signal selection unit

926_1. . . Time varying signal selection unit

926A. . . Voltage to current conversion (VCC) components

926B. . . Switcher component

930. . . Common pulse signal generator

940. . . Channel buffer

950. . . Sampler

952. . . Shift register unit

954. . . Sample/hold latch unit

1A is a block diagram showing the main portions of a conventional driver using a single time varying signal.

Figure 1B illustrates the operation of a driver using a single time varying signal;

2A is a block diagram showing the main portions of a conventional driver using a plurality of time varying signals;

Figure 2B illustrates the operation of a driver using a plurality of time varying signals;

3 is a block diagram showing a driver of a display panel using a multi-time varying signal (TVS) generator and a common pulse signal generator in accordance with a first embodiment of the present invention;

4 is a detailed block diagram showing a unit channel block to which the driver of FIG. 3 is applied;

Figure 5 is a detailed block diagram illustrating the selector shown in Figure 3;

6 is a timing diagram showing an on/off action time ratio of a common pulse signal according to an embodiment of the present invention;

Figure 7 is a detailed block diagram illustrating a common pulse signal generator shown in Figure 3;

Figure 8 is a block diagram showing a driver using a single TVS generator and a common pulse signal generator in accordance with a second embodiment of the present invention;

Figure 9 is a detailed block diagram showing a unit channel block to which the driver of Figure 8 is applied;

Figure 10 is a detailed block diagram illustrating the selector shown in Figure 9;

11A and 11B are block diagrams showing modified examples of selectors respectively shown in the drivers of Figs. 5 and 10 according to a third embodiment of the present invention; and

Figure 12 is a waveform diagram of a pulse signal according to a fourth embodiment of the present invention.

410. . . Multiple time varying signal generator

420. . . Selector

422. . . Pulse selection unit

424. . . Level shift unit

426. . . Time varying signal selection unit

430. . . Common pulse signal generator

440. . . Channel buffer

450. . . Sampler

452. . . Shift register unit

454. . . Sample/hold latch unit

Claims (24)

An apparatus for driving a display panel, comprising: a time varying signal (TVS) generator configured to generate at least one time varying signal; a common pulse signal generator configured to generate at least one pulse signal a selector configured to receive the at least one time varying signal, the at least one pulse signal and video data and select a grayscale voltage corresponding to the video data; and a buffer configured to buffer and Transmitting an output of the selector, wherein the selector and the buffer are provided to each of the plurality of channels, and the time varying signal and the plurality of pulse signals are commonly input to the selector of the plurality of channels, And wherein the common pulse signal generator controls an on/off duty ratio of each pulse signal. The device of claim 1, wherein the TVS generator divides one of the grayscale voltage ranges into a plurality of grayscale voltage ranges and generates a time-varying signal group, the time-varying signal groups respectively corresponding to the grayscales A plurality of time varying signals of one of the step voltage ranges. The device of claim 1, wherein the TVS generator generates a single time varying signal that sequentially represents a range of all gray scale voltages. The device of claim 1, wherein the common pulse signal generator comprises one configured to control an on/off time ratio of one of each pulse signal Register. An apparatus for driving a display panel, comprising: a time varying signal (TVS) generator configured to generate a plurality of time varying signals; a common pulse signal generator configured to generate a plurality of pulses a signal; a sampler configured to sample and output video data; and a selector including a pulse selector, a level shifter, and a TVS selector, wherein the pulse selector Configuring to select any one of the plurality of pulse signals based on one of the sampled video data; the level shifter configured to one of the sampled video data The upper part metadata and one of the pulse selector output pulse signals are level-shifted; and the TVS selector is configured to be based on the sampled video from the level shifter Selecting, in the data, the upper part meta-data to select any one of the plurality of time-varying signals, switching the selected time-varying signal based on the selected pulse signal, and transmitting the switched time-varying signal, wherein the common Pulse signal generator Each one of the pulse signal produced on / off duty ratio. The device of claim 5, wherein the sampler, the pulse selector, and the TVS selector are provided to each of a plurality of channels, and the TVS generator and the common pulse signal generator are formed by the plurality of Channel sharing. The device of claim 5, wherein the level shifter is configured to And a voltage level of the upper part metadata in the sampled video data and a voltage level of one of the selected pulse signals, and the shifted voltage level of the upper part metadata and the The shifted voltage level of the selected pulse signal is transmitted to the TVS selector. The device of claim 5, wherein the plurality of pulse signals are voltage level signals, and the TVS selector further comprises a voltage to current conversion (VCC) unit configured to select the selected time varying signal from one The voltage level is converted to a current level. The device of claim 5, wherein the pulse signal is a signal that is enabled from an initial time to a time when a corresponding grayscale voltage is reached, or a one that is enabled in reaching a certain duration of the corresponding grayscale voltage signal. The device of claim 5, wherein the common pulse signal generator comprises a register configured to control an on/off time ratio of one of each pulse signal. An apparatus for driving a display panel, comprising: a time varying signal (TVS) generator configured to generate a single time varying signal; a common pulse signal generator configured to generate a plurality of pulses a signal; a sampler configured to sample and output video data; and a selector including a pulse selector, a level shifter, and a switch, wherein the pulse selector is Configuring to select the plurality of pulse signals based on the sampled video data Either the level shifter is configured to level-shift one of the pulse selector outputs; and the switch is configured to shift based on the level The selected pulse signal switches the time-varying signal and transmits the switched time-varying signal, wherein the common pulse signal generator controls an on/off action time ratio of each pulse signal. The device of claim 11, wherein the sampler, the pulse selector, and the switch are provided to each of a plurality of channels, and the TVS generator and the common pulse signal generator are formed by the plurality of channels Share. The device of claim 11, wherein the level shifter is configured to shift a voltage level of one of the selected pulse signals and to transmit the shifted voltage level of the selected pulse signal To the switcher. The device of claim 11, wherein the single time varying signal is a voltage level signal, and the device further comprises: a voltage to current conversion (VCC) unit for using the selected time varying signal from a voltage level Quasi-converted to a current level. The device of claim 11, wherein the pulse signal is a signal that is enabled from an initial time to a time when a corresponding grayscale voltage is reached, or a one that is enabled in reaching a specific duration of the corresponding grayscale voltage signal. The device of claim 11, wherein the common pulse signal generator comprises a register configured to control a state of each of the pulse signals. A digital-to-analog conversion method, comprising: selecting any one of a plurality of pulse signals based on a piece of meta-information in a sampled video data; Selecting any one of a plurality of time-varying signals based on an upper portion metadata in the sampled video data; switching the selected time-varying signal based on the selected pulse signal and transmitting the switched time-varying signal And control the ratio of the on/off action time of each pulse signal. The method of claim 17, further comprising: shifting a voltage level of one of the selected pulse signals. The method of claim 17, further comprising: converting the selected time-varying signal from a voltage level to a current level. The method of claim 17, wherein the pulse signal is a signal that is enabled from an initial time to a time when a corresponding grayscale voltage is reached, or a one that is enabled in a particular duration of the corresponding grayscale voltage. signal. A digital-to-analog conversion method, comprising: selecting any one of a plurality of pulse signals based on the sampled video data; switching a single time-varying signal during one of the selected durations of the selected pulse signal and The switched time-varying signal is transmitted to a channel buffer; and one of the on/off action time ratios of each pulse signal is controlled. The method of claim 21, further comprising: shifting a voltage level of one of the selected pulse signals. The method of claim 21, further comprising: The single time varying signal is converted from a voltage level to a current level. The method of claim 21, wherein the pulse signal is a signal that is enabled from an initial time to a time when a corresponding grayscale voltage is reached, or a one that is enabled in a particular duration of the corresponding grayscale voltage. signal.