JP2004295103A - Signal line drive circuit in image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein the smooth control of color is hindered by an on-resistance of a switch in a signal line drive circuit in an image display apparatus. <P>SOLUTION: The on-resistance of each switch in an upper selection circuit 312 is adjusted in accordance with a reference gradation voltage of a reference gradation voltage line 202 to which each switch is connected, and a dividing resistance of a ladder resistance 330. Circuit configuration for the upper selection circuit 312 and a lower selection circuit 334 is constituted of a combination of an extrinsic logic type circuit and an intrinsic logic type circuit. Thus, color on the image display apparatus is smoothly controlled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to the design of a signal line driving circuit among image display devices.

  In recent years, semiconductor devices in which a semiconductor thin film is formed on a glass substrate have become widespread. Among them, an active matrix type image display device using a TFT (Thin Film Transistor) has been widely spread. Recently, a polysilicon TFT technology has been developed in which a TFT constituting a pixel and a driving circuit outside a pixel matrix are integrally formed on the same substrate. With this technology, the amount of wiring of the image display device can be greatly reduced, and durability, thinness and light weight, and low power consumption are realized. In addition, not only the drive circuit formed at the same time as the one corresponding to the analog image signal but also the one corresponding to the digital image signal has been realized.

A typical example of an active matrix type image display device is an active matrix type liquid crystal display device. A signal line drive circuit of an active matrix type liquid crystal display device samples an input image signal in synchronization with a timing signal such as a clock signal. Then, the sampled image signal is converted into a corresponding predetermined voltage, and the converted voltage is applied to a liquid crystal serving as a pixel. Since the liquid crystal has a property of changing the light transmittance according to the applied voltage, an image can be displayed.
JP-A-11-167373

  A signal line driver circuit generally has a plurality of switches in the circuit. Therefore, in the process of converting the image signal into a predetermined voltage by the signal line driving circuit, a voltage drop occurs due to the on-resistance of the switches. This voltage drop may cause a difference between the voltage that the signal line driving circuit tries to apply to each pixel and the voltage that is actually applied to each pixel. For this reason, it is particularly difficult to control multi-tone colors.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique for smoothly controlling colors of an image display device.

  One embodiment of the present invention is a signal line driver circuit. This circuit includes a high-side switch and a low-side switch block, a high-side switch selected from the high-side switch block, and a low-side select switch selected from the low-side switch block. The first intermediate voltage is extracted from the ladder resistor to which the low-voltage side voltage is applied, and the first intermediate voltage from the end of the ladder resistor connected to the high-side selection switch. .., A plurality of intermediate voltage output signal lines for extracting the k-1th intermediate voltage and extracting the kth intermediate voltage from the end connected to the low voltage side selection switch of the ladder resistor (where k is an integer of 2 or more) ), The divided resistance value that causes a difference between the first intermediate voltage and the second intermediate voltage among the resistance components of the ladder resistance is larger than the on-resistance value of the high-voltage side selection switch. Characterized in that it is a locked.

  The term “switch” mainly refers to an electronic element such as a transistor, but is not limited to this, and refers to a device that passes or stops current or switches. The “switch block” is a general term for a plurality of switches for selecting a voltage applied to each end of the ladder resistor. By making the ON resistance value of the high voltage side selection switch smaller than the high voltage side divided resistance value of the ladder resistance, the color control of the pixel can be smoothly performed.

  Another embodiment of the present invention also relates to a signal line driver circuit. This circuit includes a high-side switch and a low-side switch block, a high-side switch selected from the high-side switch block, and a low-side select switch selected from the low-side switch block. The first intermediate voltage is extracted from the ladder resistor to which the low-voltage side voltage is applied, and the first intermediate voltage from the end of the ladder resistor connected to the high-side selection switch. .., A plurality of intermediate voltage output signal lines for extracting the k-1th intermediate voltage and extracting the kth intermediate voltage from the end connected to the low voltage side selection switch of the ladder resistor (where k is an integer of 2 or more) ), The divided resistance value of the resistance component of the ladder resistance that causes a difference between the (k-1) th intermediate voltage and the kth intermediate voltage is larger than the on-resistance value of the low-voltage side selection switch. Characterized in that it is a have relationship.

  Similarly, by making the ON resistance value of the low voltage side selection switch smaller than the low voltage side divided resistance value of the ladder resistance, the color control of the pixel can be smoothly performed.

  Another embodiment of the present invention also relates to a signal line driver circuit. This circuit includes a high-side switch and a low-side switch block, a high-side switch selected from the high-side switch block, and a low-side select switch selected from the low-side switch block. A ladder resistor to which a low-voltage is applied, and a plurality of intermediate voltage extraction signal lines for extracting different intermediate voltages from the middle of the ladder resistance, a potential difference between the high-voltage and a predetermined reference voltage; It is characterized in that the magnitude relationship between the potential difference between the side voltage and the reference voltage and the magnitude relationship between the on-resistance values of the high voltage side and low voltage side selection switches are reversed.

  Each switch in the switch block is connected to a different voltage line. The higher the voltage supplied by the voltage line, the longer it takes to write to the signal line. Therefore, when a voltage is supplied from these voltage lines to the signal line, a predetermined reference voltage (hereinafter, referred to as a “precharge voltage”) may be supplied to the signal line in advance. For example, when a high voltage is supplied to the signal line, only a voltage that is different from the precharge voltage is applied, and when a voltage lower than the precharge voltage is supplied to the signal line, according to the difference, Discharge the precharge voltage. However, even in that case, if the potential difference between the voltage supplied to the signal line and the precharge voltage is large, it takes time to write the data. Therefore, the writing time can be shortened by adjusting the on-resistance value of the switch connected to the voltage line that supplies a voltage having a large potential difference from the precharge voltage to a small value.

  Also, the signal line drive circuit receives an x-bit input of the n-bit image signal and selects a high-voltage side and a low-voltage side selection switch from a high-voltage side and a low-voltage side switch block. , N is an integer of 2 or more, and x is an integer of 1 or more and less than n), and a desired number of intermediate voltage extraction signal lines are obtained by using nx bits of the image signal excluding the aforementioned x bits. And a lower selection circuit for selecting one of the two.

  By appropriately distributing the number of bits of the image signal between the upper selection circuit and the lower selection circuit, the signal line driving circuit can be efficiently designed according to the specifications of the image display device.

  The higher-order selection circuit is a circuit of a type in which a logic for selecting a high-voltage side and a low-voltage side selection switch exists outside the path of a line through which a plurality of switches included in the switch block are interposed. The circuit is of a type in which at least a part of the logic for selecting a desired one of the plurality of intermediate voltage output signal lines is interposed on the path of the intermediate voltage output signal line to be selected. You may.

  By dividing the types of the upper selection circuit and the lower selection circuit, the signal line driving circuit can be designed more efficiently in accordance with the specifications of the image display device.

  In addition, any combination or rearrangement of the above-described components, and those expressing the present invention as a method are also effective as embodiments of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the color of an image display apparatus can be controlled smoothly.

  First, the operation principle of the active matrix type liquid crystal display device will be described.

  FIG. 1 shows a configuration of an active matrix type liquid crystal display device. The active matrix type liquid crystal display device includes a signal line driving circuit 100, a scanning line driving circuit 400, and a pixel matrix 500. The signal line driving circuit 100 samples an input image signal in synchronization with a timing signal such as a clock signal. Then, the signal line driving circuit 100 converts the sampled image signal into a predetermined voltage corresponding to the sampled image signal, and applies the voltage to each pixel circuit 530 on each pixel signal line 510. The scanning line driving circuit 400 sequentially selects the scanning lines 520 in synchronization with a timing signal such as a clock signal, and controls on / off of each pixel circuit 530 on each scanning line 520. A desired image is displayed by changing the light transmittance of the liquid crystal of the pixel circuit 530 according to the applied voltage.

  FIG. 2 shows an internal configuration of the signal line driving circuit 100. When the shift register 102 receives a start pulse from the start pulse signal line 104, the shift register 102 generates a sampling pulse in synchronization with a clock signal input from the clock signal line 106. The latch circuit 200 receives a digital image signal (hereinafter, simply referred to as “image signal”) from the image signal line 108 in synchronization with the sampling pulse, and stores the digital image signal.

  The image signal stored in the latch circuit 200 is transmitted to the image signal D / A conversion circuit 300 in synchronization with the latch signal input from the latch signal line 110. The image signal D / A conversion circuit 300 converts the image signal into a predetermined voltage (hereinafter referred to as “pixel applied voltage”) based on a voltage (hereinafter referred to as “reference gray voltage”) supplied from the reference gray voltage line 202. Voltage). The mechanism of the D / A conversion of the image signal D / A conversion circuit 300 will be described later in detail.

  Upon receiving the input of the pixel applied voltage from the image signal D / A conversion circuit 300, the pixel signal line selection circuit 350 synchronizes with the signal line selection signal input from the pixel signal line selection signal line 352 to generate a predetermined pixel signal. A pixel applied voltage is applied to line 510. The pixel signal line selection circuit 350 drives all the pixel signal lines 510 by performing writing while dividing one horizontal scanning period into a plurality. That is, since a plurality of pixel signal lines are driven by one DAC circuit by the pixel signal line selection circuit 350, the circuit area can be reduced.

  Next, the operation principle of the image signal D / A converter 150 in FIG. 2 will be described.

  FIG. 3 shows an internal configuration of the image signal D / A converter 150 of FIG. Here, a 4-bit image signal D / A converter 150 is taken as an example. Further, the internal resistance of the wiring itself and the ON resistance of the switch are not considered.

  The image signal D / A converter 150 can be divided into an upper selection circuit 312 and a lower selection circuit 334. The high-order selection circuit 312 includes a high-voltage switch block 310 and a low-voltage switch block 320 each including four switches (A1 to A4, B1 to B4), and a reference grayscale voltage line 202. The lower selection circuit 334 includes a ladder switch block 340 including four switches (C1 to C4) and a ladder resistor 330. Each reference gradation voltage line 202 supplies five types of voltages (V0 to V4) from a low voltage to a high voltage.

  In the figure, the high-side switch block 310 and the low-side switch block 320 are each controlled by a two-bit signal (hereinafter, referred to as an “upper signal”) of the four-bit image signal transmitted from the latch circuit 200. . In each of the high-side switch block 310 and the low-side switch block 320, only one switch is designed to be closed, and two switches are not closed at the same time. Further, the following relationship is established between the switches inside the high voltage side switch block 310 and the switches inside the low voltage side switch block 320.

  That is, when the B4 switch of the high voltage side switch block 310 is closed, the A4 switch of the low voltage side switch block 320 is also closed in conjunction with this. Similarly, when the switch B3 of the high voltage side switch block 310 is closed, the A3 switch of the low voltage side switch block 320 is also closed in conjunction with this. This is the same for the other switches. Therefore, the adjacent reference gradation voltage line 202 is always selected, and a predetermined reference gradation voltage is applied to both ends of the ladder resistor 330.

  The ladder switch block 340 uses the remaining two-bit signals (hereinafter, referred to as “lower signals”) of the 4-bit image signal transmitted from the latch circuit 200, excluding the two bits used in the higher-order selection circuit 312. Controlled. The ladder switch block is designed so that only one switch is closed, and two switches are not closed at the same time.

  The voltage selected by the higher-order selection circuit 312 and applied to both ends of the ladder resistor 330 (hereinafter, referred to as “ladder applied voltage”) is divided by the divided resistors R0 to R3 of the ladder resistor 330. Then, four types of intermediate voltages are input to the ladder switch block 340 by the four intermediate voltage extraction signal lines 332. Therefore, by closing one of the switches in the ladder switch block 340 in response to the lower signal, one of these intermediate voltages is output to the pixel signal line selection circuit 350 in FIG. 2 as a pixel applied voltage. You.

  FIG. 4 shows the level of the pixel applied voltage output by the lower selection circuit 334. The image signal D / A converter 150 outputs 16 types of pixel applied voltages from Vref0 to Vref15 based on the 4-bit image signal. For example, when the switch A1 of the low voltage side switch block 320 and the switch B1 of the high voltage side switch block 310 are closed, the ladder applied voltage becomes V1−V0.

  Here, when the switch C1 of the ladder switch block 340 is selected, the lower-order selection circuit 334 outputs V0, that is, Vref0 shown in FIG. When the switch C2 is selected instead of the switch C1 of the ladder switch block 340, the lower selection circuit 334 outputs Vref1, which is a voltage higher than V0 by the division resistance R3, as a pixel applied voltage. When the switch A4 of the low-voltage switch block 320, the switch B4 of the high-voltage switch block 310, and the switch C4 of the ladder switch block 340 are closed, the lower-order selection circuit 334 sets the divided resistance of the ladder resistor 330 from V4. The pixel application voltage of Vref15, which is obtained by subtracting the voltage drop of R0, is output.

  The reason why the division resistance R0 is provided in the ladder resistor 330 is that the lower selection circuit 334 results even if the combination of selection of each switch of the high-voltage switch block 310, the low-voltage switch block 320 and the ladder switch block 340 is different. In order to prevent the same pixel applied voltage from being output.

  For example, if there is no division resistor R0, when the switch A3 of the low voltage side switch block 320, the switch B3 of the high voltage side switch block 310, and the switch C4 of the ladder switch block 340 are selected, the lower selection circuit 334 sets V3 to the pixel applied voltage. Is output as Similarly, even when the switch A4 of the low voltage side switch block 320, the switch B4 of the high voltage side switch block 310, and the switch C1 of the ladder switch block 340 are selected, the lower selection circuit 334 outputs V3 as the pixel applied voltage. That is, there is a case where the same pixel applied voltage is output while the selection of the switch in each switch block is different.

  However, if the division resistance R0 exists, in the former case, the lower selection circuit 334 outputs a pixel applied voltage reduced by the voltage drop due to the division resistance R0 from the reference gradation voltage V3, so that such a state can be avoided. . That is, the image signal D / A converter 150 can output 16 types of pixel applied voltages according to the 4-bit image signal due to the presence of the division resistor R0.

  FIG. 5 shows a general relationship between the light transmittance of the liquid crystal and the applied voltage in a white display mode without applying a voltage (hereinafter, referred to as a “normally white mode”). The horizontal axis represents the applied voltage, and the vertical axis represents the light transmittance. As shown in the figure, as the applied voltage is increased, the liquid crystal does not transmit light. Therefore, a desired image display is realized by controlling the pixel applied voltage output from the image signal D / A converter 150.

  Next, the circuit configuration of the high-voltage switch block 310, the low-voltage switch block 320, and the ladder switch block 340 in FIG. 3 will be described. With respect to the configuration of these circuits, there are two systems shown in FIGS. Here, a 2-bit circuit is taken as an example. Here, all the switches will be described as TFTs.

  FIG. 6 shows an example of a D / A conversion circuit controlled by 2-bit signals (D0, D1). Hereinafter, a circuit such as this circuit in which a logic for selecting a switch exists outside the path of a line in which a plurality of switches are interposed is referred to as a “logic external circuit”.

  The voltage supply lines 204 supply four types of voltages from V0 to V3, respectively. In the logic external type circuit shown in the figure, one of the switching TFTs S1 to S4 is selected by four NOR gates and two inverters according to a 2-bit signal (D0, D1). Thereby, one of the four voltages from V0 to V3 is supplied, so that D / A conversion is realized. For example, if D0 is HIGH and D1 is LOW, only S3 is turned on, and this circuit outputs the voltage V2.

  FIG. 7 shows another example of a D / A conversion circuit controlled by 2-bit signals (D0, D1). Hereinafter, a circuit in which at least a part of a logic for selecting a desired one of a plurality of lines is interpolated on a path of a line to be selected, such as this circuit, is referred to as a “logical intrinsic type”. Circuit ".

  The voltage supply lines 204 supply four types of voltages V0 to V3, respectively. In the logic intrinsic type circuit of FIG. 6, six switching TFTs (S1 to S6) interposed on the voltage supply line 204 are appropriately selected according to the 2-bit signals (D0, D1). As a result, one of the four voltages V0 to V3 is output, so that D / A conversion is realized. For example, if D0 is HIGH and D1 is LOW, S1, S3 and S6 of the switching TFT are turned on, so that a voltage of V1 is output from this circuit.

  The external logic circuit of FIG. 6 passes only one of the switching TFTs S1 to S4 in the process of extracting a voltage from the voltage supply line 204. Therefore, the external logic circuit is a circuit having a small voltage drop because only one stage passes through the switching TFT in the voltage extracting process, and has excellent circuit drivability.

  On the other hand, the logic intrinsic type circuit shown in FIG. 7 is a circuit of a type useful for reducing the circuit scale because a logical configuration can be made with only six TFTs for a 2-bit signal.

  Next, the harmful effects of not taking measures against the voltage drop due to the on-resistance of these switches will be specifically described.

  FIG. 8 is a schematic diagram of extracting a pixel applied voltage from a ladder applied voltage. Here, it is assumed that there is no on-resistance of the switches in the high-voltage switch block 310, the low-voltage switch block 320, and the ladder switch block 340 in FIG.

  In the figure, reference gradation voltages selected in the low-voltage switch block 320 and the high-voltage switch block 310 are applied to the low-voltage ladder resistance end point 336 and the high-voltage ladder resistance end point 338, respectively. Here, it is assumed that the reference gradation voltage V1 is applied to the high voltage side ladder resistance end point 338, and the reference gradation voltage V0 is applied to the low voltage side ladder resistance end point 336.

  As described above, the ladder application voltage is divided by the division resistors R0 to R3, and the intermediate voltage is extracted by the intermediate voltage extraction signal line 332. In the figure, four intermediate voltage extraction signal lines 332 extract voltages from Vref0 to Vref3. Therefore, by adjusting the values of the division resistors R0 to R3, an arbitrary pixel applied voltage between V0 and V1 can be finally obtained.

  FIG. 9 is also a schematic diagram of extracting a pixel applied voltage from a ladder applied voltage. 3 does not consider the on-resistance of the switches in the ladder switch block 340 of FIG. 3, but considers the on-resistance of the switches in the high-voltage switch block 310 and the low-voltage switch block 320.

  In the figure, reference gradation voltages selected in the low-voltage switch block 320 and the high-voltage switch block 310 are applied to the low-voltage ladder resistance end point 336 and the high-voltage ladder resistance end point 338, respectively. Here, it is also assumed that the reference gradation voltage V1 is applied to the high voltage side ladder resistance end point 338, and the reference gradation voltage V0 is applied to the low voltage side ladder resistance end point 336.

  Here, the resistances r1 and r2 are the ON resistances of the switches selected in the high-side switch block 310 and the low-side switch block 320, respectively. Therefore, the voltage is actually supplied to both ends of the ladder resistor 330 in a narrower range than V1 to V0 due to the voltage drop due to the on-resistance. That is, even if the resistance values of the divided resistors R0 to R3 are adjusted, a voltage within a predetermined range cannot be supplied as a pixel applied voltage. This range is a portion shown by oblique lines in FIG. Hereinafter, a voltage range that cannot be supplied due to the voltage drop of the on-resistance is referred to as a “supply-unavailable voltage range”.

  The unsuppliable voltage range is a voltage range that cannot be applied to the liquid crystal. Therefore, this hinders smooth control of the color of the image display device. In particular, when the switches are connected in multiple stages when supplying the voltage, this adverse effect becomes remarkable.

  Hereinafter, embodiments of the present invention that solve these problems will be described.

  FIG. 10 shows an embodiment of the reference gradation voltage line 202 driven by a 6-bit image signal, the image signal D / A conversion circuit 300, and the pixel signal line selection signal line 352. In the figure, of the 6-bit image signal, 3 bits are an upper signal and the remaining 3 bits are a lower signal.

  In the figure, the upper selection circuit 312 is formed by a logic external circuit, and the lower selection circuit 334 is formed by a logical internal circuit. The reference gradation voltage line 202 supplies nine kinds of reference gradation voltages from V0 to V8. Correspondingly, the high-side switch block and the low-side switch block of the upper-level selection circuit 312 each include eight switches (B1 to B8, A1 to A8). The ladder resistor 330 is divided into seven by the dividing resistors R1 to R7, and the lower selection circuit 334 receives eight kinds of intermediate voltages as inputs.

  In the figure, the on-resistance value of each switch in the upper selection circuit 312 is properly adjusted. The adjustment method will be described later in detail. Note that, in the figure, a resistor corresponding to the divided resistor R0 in FIG. 3 is not provided. This is because even if there is no division resistor R0, the image signal D / A conversion circuit 300 can select different switches while appropriately adjusting the on-resistance of each switch in the higher-order selection circuit 312 as described later. As a result, a state in which the same pixel applied voltage is output does not occur.

  Adjustment of the on-resistance value of the switch is performed from two viewpoints. One is the relationship between the divided resistance value of the ladder resistor and the on-resistance value of the switch (hereinafter, referred to as a “first relationship”), and the other is the relationship of the reference gradation voltage line 202 connected to each switch. This is the relationship between the reference gradation voltage and the on-resistance value (hereinafter, referred to as “second relationship”). When the switch is a TFT, the on-resistance of the switch can be adjusted by adjusting the gate width and gate length of the TFT.

About the first relationship:
In this circuit, the on-resistance values of the switches B1 to B8 of the high-voltage side switch block 310 are set smaller than the resistance value of the divisional resistor R1. As a numerical example, the TFT gate width is set to 300 μm, the gate length is set to 4 μm, the ON resistance value is set to 1.5 kΩ, and the resistance value of the divisional resistor R1 is set to 3 kΩ. Further, the on-resistance values of the switches A1 to A8 of the low-voltage side switch block 320 are similarly set smaller than the resistance value of the divisional resistor R7.

  FIG. 11 shows the level of the pixel applied voltage after the ON resistance value of the switch is adjusted based on the first relationship. However, for the sake of explanation of the principle, in this figure, only the on-resistance of the switches (A1 to A8, B1 to B8) in the upper selection circuit 312 is focused, and the on-resistance of the switches in the lower selection circuit 334 is not considered. .

  In the figure, among the pixel applied voltages output from the lower selection circuit 334, the voltage levels near the reference gradation voltage V7 of the reference gradation voltage line 202 are shown. The voltage drop 356 in the figure represents a voltage drop due to the on-resistance of the switch B7 when the higher-order selection circuit 312 selects the switch B7 and the switch A7. Then, the potential difference between Vref55 and Vref54 is generated by the voltage applied to the dividing resistor R1 at this time. Therefore, for example, if the ON resistance value of the switch B7 is half of the resistance value of the divisional resistor R1, Vref55−Vref54 becomes twice V7−Vref55.

  Similarly, the voltage drop 358 in the figure represents the voltage drop due to the switch A8 when the higher-order selection circuit 312 selects the switch B8 and the switch A8. Then, a potential difference between Vref57 and Vref56 is generated by a voltage applied to both ends of the dividing resistor R7 at this time. Therefore, if the ON resistance value of the switch A8 is half of the resistance value of the divisional resistor R7, Vref57−Vref56 is twice Vref56−V7.

  By the adjustment based on the first relationship, the non-supplyable voltage range existing between Vref54 and Vref57 is adjusted, and a smooth transition of the voltage level is realized. Although the case where the ON resistance value of the predetermined switch is half of the predetermined divided resistance value has been described here, it is needless to say that the present invention is not limited to this.

On the second relationship:
Generally, the higher the voltage, the longer it takes to write. In order to shorten the writing time, the ON resistance value of the switch that conducts the high voltage may be set small. This is because when the on-resistance value of the switch is reduced, the drivability of the switch increases. For example, a case where V8 and V7 are applied as reference gradation voltages to both ends of the ladder resistor 330 will be described as an example.

  In this case, the reference gradation voltage V8 requires more time to write the voltage than the reference gradation voltage V7. Therefore, the on-resistance value of the switch B8 connected to the reference gradation voltage V8 is set smaller than the on-resistance value of the switch A8 connected to the reference gradation voltage V7. As a numerical specific example, if the resistance values of the divided resistors R1 to R7 of the ladder resistor 330 are the same, the ON resistance value of the switch B8 is 0.33 times the divided resistance value, and the ON resistance value of the switch A8 is It is set to 0.67 times the division resistance value.

  FIG. 12 shows the level of the voltage applied to the pixel after the on-resistance value of the switch is adjusted based on the second relationship. However, for the sake of explanation of the principle, in this figure, only the on-resistance of the switches (A1 to A8, B1 to B8) in the upper selection circuit 312 is focused, and the on-resistance of the switches in the lower selection circuit 334 is not considered. .

  In the drawing, among the pixel applied voltages output by the lower selection circuit 334, the voltage levels near the reference gradation voltages V7 to V8 of the reference gradation voltage line 202 are shown. A voltage drop 360 in the figure indicates a voltage drop due to the on-resistance of the switch B8 when the higher-order selection circuit 312 selects the switch B8 and the switch A8. The voltage drop 362 indicates a voltage drop caused by the switch A8. In order to supply a high voltage, the ON resistance value of the switch B8 is set smaller than the ON resistance value of the switch A8.

  By the adjustment based on the second relationship, the time required for the signal line driving circuit 100 to write a predetermined voltage to the pixel signal line 510 can be reduced. Further, in the case where the above-described precharge voltage is applied to the signal line in advance, if the voltage actually supplied to the signal line is lower than the precharge voltage, it is necessary to perform discharging. Therefore, even if the switch conducts a low voltage, if the potential difference between the voltage at which the switch conducts and the precharge voltage is large, it takes time to drive the switch. Therefore, also in this case, the writing time can be reduced by setting the ON resistance value of the switch that conducts the low voltage small. Also, by setting the on-resistance values of the switches A1 and B8 smaller than the on-resistance values of the other switches, the dynamic range (the potential difference from Vref63 to Vref0) can be increased.

  As described above, the logic intrinsic circuit can reduce the number of TFT elements, which is advantageous in reducing the circuit area. In addition, the external logic circuit has a small voltage drop because only one stage passes through the switching TFT in the voltage extraction process, and is excellent in circuit responsiveness.

  In the present embodiment shown in FIG. 11, the upper selection circuit 312 is formed by an external logic circuit, and the lower selection circuit 334 is formed by an internal logic circuit. Therefore, when distributing the number of bits of the image signal to the upper signal and the lower signal, a trade-off between a reduction in circuit area and a reduction in writing time can be achieved. That is, if priority is given to the response speed of the image display device, the number of bits of the logic external circuit is increased, and the number of switches from the reference gradation voltage line 202 to the pixel signal line selection signal line 352 is reduced. Design the circuit. Conversely, if priority is given to reducing the circuit area, a larger number of bits of the logical intrinsic circuit may be allocated.

  The present invention has been described based on the embodiments. It should be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications can be made to combinations of the components, and that such modifications are also within the scope of the present invention.

  As such a modification, a case where an electroluminescence (hereinafter, simply referred to as “EL”) material is used for a display element will be described. The EL element is of a current driving type and has a different circuit configuration from the pixel circuit 530 in the case of a liquid crystal material.

  FIG. 13 illustrates an example of a pixel circuit 530 using an EL material. The pixel circuit 530 includes two TFTs, a switching transistor Tr1 for designating write timing and a drive transistor Tr2 for passing a current to the EL element. The pixel circuit 530 includes a capacitor C1 for holding a write voltage, a scanning line 520, a pixel signal line 510, and a power supply line 512 for supplying a current.

  In the pixel circuit 530 of FIG. 10, when the scanning line 520 is selected, the switching transistor Tr1 is turned on, and the voltage of the pixel signal line 510 is stored in the capacitor C1. At the same time, the drive transistor Tr2 is also turned on, a current corresponding to the write voltage flows through the EL element, and the EL element emits light. Even after the selection period of the scanning line 520 ends, a predetermined current flows through the EL element by the voltage held in the capacitor C1 until the next image signal is received.

FIG. 2 is a diagram illustrating a configuration of an image display device. FIG. 3 is a diagram illustrating an internal configuration of a signal line driving circuit according to the embodiment; FIG. 3 is a diagram illustrating an internal configuration of an image signal D / A conversion unit in the signal line driving circuit according to the embodiment. FIG. 4 is a diagram illustrating a voltage level applied to a pixel in the signal line driving circuit in FIG. 3. FIG. 7 is a diagram showing a general correspondence between an applied voltage of a liquid crystal and a light transmittance in a normally white mode. FIG. 2 is a diagram illustrating a D / A conversion circuit of a logic external type. FIG. 3 is a diagram illustrating a D / A conversion circuit of a logical intrinsic type. FIG. 9 is a schematic diagram of extracting a pixel applied voltage from a ladder applied voltage when the on-resistance of a switch of the signal line driving circuit is not considered. FIG. 9 is a schematic diagram illustrating extraction of a pixel applied voltage from a ladder applied voltage when the on-resistance of a switch of a signal line driving circuit is considered. FIG. 3 is a diagram illustrating a circuit from a reference grayscale voltage line to a pixel signal line according to the embodiment; FIG. 6 is a diagram illustrating a pixel applied voltage level after the on-resistance value of the switch is adjusted based on the first relationship according to the embodiment. FIG. 14 is a diagram illustrating a pixel applied voltage level after the on-resistance value of the switch is adjusted based on the second relationship according to the embodiment. FIG. 2 is a diagram illustrating a pixel circuit using an organic EL element.

Explanation of reference numerals

100 signal line drive circuit, 202 reference gradation voltage line, 300 image signal D / A conversion circuit, 310 high voltage side switch block, 312 high order selection circuit, 320 low voltage side switch block, 330 ladder resistance, 332 intermediate voltage extraction signal line, 334 Lower selection circuit, 340 ladder switch block, 510 pixel signal line, 530 pixel circuit.

Claims (5)

High and low pressure switch blocks,
A ladder resistor to which high-side and low-side voltages are respectively applied to both ends via a high-side selection switch selected from the high-side switch block and a low-side selection switch selected from the low-side switch block,
The first intermediate voltage is extracted from the end of the ladder resistor connected to the high-voltage side selection switch, and the second, third,... A plurality of intermediate voltage extraction signal lines for extracting a k-th intermediate voltage from an end of the ladder resistor connected to the low-voltage side selection switch (where k is an integer of 2 or more);
Including
A signal, wherein a resistance value of a divided resistance value that causes a difference between the first intermediate voltage and the second intermediate voltage among the resistance components of the ladder resistance is larger than an ON resistance value of the high-voltage side selection switch. Line drive circuit. High and low pressure switch blocks,
A ladder resistor to which high-side and low-side voltages are respectively applied to both ends via a high-side selection switch selected from the high-side switch block and a low-side selection switch selected from the low-side switch block,
The first intermediate voltage is extracted from the end of the ladder resistor connected to the high-voltage side selection switch, and the second, third,... A plurality of intermediate voltage extraction signal lines for extracting a k-th intermediate voltage from an end of the ladder resistor connected to the low-voltage side selection switch (where k is an integer of 2 or more);
Including
A divisional resistance value that produces a difference between the (k−1) th intermediate voltage and the kth intermediate voltage among the resistance components of the ladder resistance is larger than the on-resistance value of the low-voltage side selection switch. Signal line drive circuit. High and low pressure switch blocks,
A ladder resistor to which high-side and low-side voltages are respectively applied to both ends via a high-side selection switch selected from the high-side switch block and a low-side selection switch selected from the low-side switch block,
A plurality of intermediate voltage extraction signal lines for extracting different intermediate voltages from the middle of the ladder resistance,
Including
The potential difference between the voltage on the high voltage side and a predetermined reference voltage, the magnitude relationship between the potential difference between the low voltage voltage and the reference voltage, and the magnitude relationship between the on-resistance values of the high voltage side and the low voltage side selection switch are reversed. A signal line drive circuit, wherein the signal line drive circuit is configured to be: an upper-level selection circuit that receives x-bit input of the n-bit image signal and selects the high-side and low-side selection switches from the high-side and low-side switch blocks, respectively, where n is an integer of 2 or more; Where x is an integer of 1 or more and less than n),
A lower selection circuit that selects a desired one of the plurality of intermediate voltage extraction signal lines by a signal of nx bits excluding the x bit in the image signal;
The signal line driving circuit according to claim 1, further comprising: The upper-level selection circuit is a circuit of a type in which a logic for selecting the high-voltage side and the low-voltage side selection switch exists outside a path of a line in which a plurality of switches included in the switch block are interposed,
The lower-order selection circuit is configured such that at least a part of a logic for selecting a desired one of the plurality of intermediate voltage extraction signal lines is inserted on a path of the intermediate voltage extraction signal line to be selected. 5. The signal line driving circuit according to claim 4, wherein:

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