JP4721763B2 - D / A conversion circuit, display driver, and display device - Google Patents

Description

  The present invention relates to a D / A conversion circuit that converts a digital signal into an analog signal.

  As a D / A conversion circuit for converting a digital signal into an analog signal, various methods such as a resistance string method and a switched capacitor method are known. According to the resistor string method, a plurality of gradation voltages generated from a plurality of reference voltages by resistance voltage division are supplied to a plurality of switches, and a desired gradation voltage corresponding to a digital signal from the plurality of gradation voltages. Is selected. According to the switched capacitor method, a switch and a capacitor are used.

  Such a D / A conversion circuit is also used for a liquid crystal driver for driving a liquid crystal display device. In the liquid crystal display, gamma correction is performed in order to realize a natural gradation display. Therefore, the relationship between the input signal and the output signal to the D / A conversion circuit is not linear but nonlinear. Therefore, particularly in a liquid crystal display device, a resistor string type D / A conversion circuit having excellent monotonic increase characteristics is often used.

  For example, FIG. 3 of Patent Document 1 discloses a resistor string type D / A conversion circuit. This D / A conversion circuit selects a gradation voltage corresponding to an input 6-bit digital signal (D0 to D5) from 64 kinds of gradation voltages. Specifically, 64 switches are controlled by the least significant bit D0 of the digital signal, and 32 types of gradation voltages are selected from the 64 types of gradation voltages. The 32 switches are controlled by the digital signal D1, and 16 kinds of gradation voltages are selected from the 32 kinds of gradation voltages. Sixteen switches are controlled by the digital signal D2, and eight kinds of gradation voltages are selected from the 16 kinds of gradation voltages. Eight switches are controlled by the digital signal D3, and four kinds of gradation voltages are selected from the eight kinds of gradation voltages. Four switches are controlled by the digital signal D4, and two kinds of gradation voltages are selected from the above four kinds of gradation voltages. Two switches are controlled by the most significant bit D5 of the digital signal, and one kind of gradation voltage is selected from the two kinds of gradation voltages. In this way, a desired gradation voltage is selected by the tournament method, and the liquid crystal display device is driven.

JP 2002-175060 A

  In a liquid crystal display device, the driving voltage of liquid crystal is higher than the operating voltage of a logic unit such as a latch circuit that stores a digital signal. Therefore, the withstand voltage of the elements constituting the D / A conversion circuit for driving the liquid crystal is designed to be higher than the withstand voltage of the elements constituting the logic unit. In order to further increase the breakdown voltage of the MOS transistor, it is necessary to make the gate length L longer and the gate oxide film Tox thicker. However, this causes a reduction in the driving capability of the transistor. In order to maintain the driving capability of the transistor, it is necessary to increase the gate width W. In other words, the circuit area increases exponentially as the withstand voltage of the elements constituting the D / A conversion circuit increases.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The D / A conversion circuit (1) according to the present invention converts a digital signal (D0 to D5) composed of an upper bit group (D5) and lower bit groups (D0 to D4) into a plurality of analog voltage signals (V1 to V64). Are converted into one analog voltage signal corresponding to the digital signal (D0 to D5). Specifically, the D / A conversion circuit (1) according to the present invention includes a first D / A converter (11), a second D / A converter (12), and a selection circuit (19). With.

  The first D / A converter (11) includes a first voltage range (VDD to GND) between the first voltage (VDD) and a second voltage (GND) lower than the first voltage (VDD). ). The first D / A converter (11) includes a first voltage signal group (V33 to V64) corresponding to a first voltage range (VDD to GND) among the plurality of analog voltage signals (V1 to V64). And outputs a first analog voltage signal corresponding to the lower bit group (D0 to D4) of the first voltage signal group (V33 to V64) to the selection circuit (19).

  On the other hand, the second D / A converter (12) has a second voltage between the third voltage (GND) and a fourth voltage (VEE) lower than the second and third voltages (GND). Operates in the range (GND to VEE). The second D / A converter (12) includes a second voltage signal group (V1 to V32) corresponding to a second voltage range (GND to VEE) among the plurality of analog voltage signals (V1 to V64). And outputs a second analog voltage signal corresponding to the lower bit group (D0 to D4) of the second voltage signal group (V1 to V32) to the selection circuit (19).

  The selection circuit (19) selects either the first analog voltage signal or the second analog voltage signal as the one analog voltage signal in accordance with the upper bit group (D5). The selection circuit (19) has a third voltage range (VDD to VEE) between a voltage (VDD) higher than the first voltage (VDD) and a voltage (VEE) lower than the fourth voltage (VEE). Operate.

  The selection circuit (19) or the like that operates in the third voltage range (VDD to VEE) is manufactured with a high-voltage element. However, the first D / A converter (11) operating in the first voltage range (VDD to GND) and the second D / A converter operating in the second voltage range (GND to VEE) ( With regard to 12), it is possible to manufacture with a medium voltage element having a lower withstand voltage than a high voltage element. That is, according to the present invention, the withstand voltage of the elements constituting the D / A conversion circuit (1) may be lower than that of the prior art, so that the gate length L and gate width W of the elements can be designed to be small. Become. Therefore, the circuit area of the D / A conversion circuit (1) can be reduced. In addition, since the operating voltage of the first D / A converter (11) and the second D / A converter (12) is reduced, the power consumption of the D / A converter circuit (1) can be reduced. It becomes possible.

  In particular, the D / A conversion circuit (1) according to the present invention is preferably applied to a display driver (61) for driving a display device (60) such as a liquid crystal display. In this case, the digital signals (D0 to D5) are pixel data displayed on the pixels of the display device (60). Each of the plurality of analog voltage signals (V1 to V64) is a plurality of gradation signals indicating pixel voltages generated by the gradation voltage generation circuit (4). The display device (60) includes a display panel (63) having a plurality of pixels (66), and the display driver (61) converts the gradation signal selected as the one analog voltage signal into the plurality of pixels (66). ) Thereby, an image is displayed on the display panel (63).

  In general, the driving voltage of the liquid crystal is higher than the operating voltage of the logic unit (2) such as the latch circuit (31) that stores the digital signals (D0 to D5). The D / A conversion circuit (1) for supplying the drive voltage has conventionally been constituted by a high voltage element. However, according to the configuration according to the present invention, the D / A conversion circuit (1) is replaced with the conventional D / A conversion circuit (1). It is possible to configure the device with a lower breakdown voltage. Since the circuit area of the D / A conversion circuit (1) is reduced, the circuit areas of the display driver (61) and the display device (60) are also reduced. Further, the power consumption of the display driver (61) and the display device (60) is reduced.

  According to the present invention, the circuit area of the D / A conversion circuit can be reduced. In addition, the power consumption of the D / A conversion circuit can be reduced. Furthermore, it becomes possible to reduce the power consumption of the display device using the D / A conversion circuit.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The following description is intended to describe embodiments of the present invention and does not mean that the present invention is limited to the following embodiments. For example, in the following description, a 6-bit digital signal is handled, but the number of bits of the digital signal handled in the present invention may be 5 or more and 7 or less.

  First, terms used in this specification are defined. The D / A conversion circuit converts a digital signal into an analog voltage signal corresponding to the digital signal. The digital signal is, for example, a 6-bit digital signal (D5, D4, D3, D2, D1, D0) as shown in FIG. The most significant bit (MSB: Most Significant Bit) of this digital signal is D5, and the least significant bit (LSB: Least Significant Bit) is D0. In this specification, the “upper bit group” means a bit group including at least one upper bit including the most significant bit. Further, the “lower bit group” means a bit group including at least one lower bit including the least significant bit. For example, as shown in FIG. 1, the upper bit group includes only the most significant bit D5, and the lower bit group includes bits D4 to D0 other than the most significant bit.

  This 6-bit digital signal can express 64 types of data. The 64 types of data are associated with 64 types of analog voltage signals, respectively. The respective voltages of the 64 types of analog voltage signals are sequentially expressed as V1 to V64 based on the values, and as shown in FIG. 2, it is assumed that the voltage V1 is the lowest and the voltage V64 is the highest. Of the 64 types of voltages, the relatively high voltage groups V33 to V64 are included in at least the “first voltage range”, and the relatively low voltage groups V1 to V32 are included in at least the “second voltage range”. Let's say. As shown in FIG. 2, the “first voltage range” is between a first voltage VDD (eg, 3V) and a second voltage (eg, 0V) lower than the first voltage VDD. Defined as a range. The “second voltage range” is defined as a range between the third voltage (for example, 0 V) and the fourth voltage VEE (for example, −3 V) lower than the second and third voltages. The That is, the first voltage range covers a region higher than the second voltage range. Furthermore, the voltage range including all the voltages V1 to V64 is referred to as a “third voltage range”. The “third voltage range” is defined as a range between a voltage (for example, 5 V) equal to or higher than the first voltage VDD and a voltage (−5 V) equal to or lower than the fourth voltage VEE.

  Of the 64 types of analog voltage signals, a group having the voltages V33 to V64 included in the first voltage range is referred to as a “first voltage signal group”. A group having the voltages V1 to V32 included in the second voltage range is referred to as a “second voltage signal group”. Hereinafter, each of the symbols V1 to V64 may indicate an analog voltage signal having the voltage together with the voltage value. For example, the first voltage signal group corresponding to the first voltage range is referred to as “first voltage signal group V33 to V64”, and the second voltage signal group corresponding to the second voltage range is “ It may be referred to as “second voltage signal group V1 to V32”.

  The 6-bit digital signals D0 to D5 shown above are associated with 64 types of analog voltage signals V1 to V64. For example, the digital signal “000000” corresponds to the analog voltage signal V1, and the digital signal “011111” corresponds to the analog voltage signal V32. That is, the digital signal whose most significant bit D5 is “0” corresponds to the second voltage signal group V1 to V32. The digital signal “100000” corresponds to the analog voltage signal V33, and the digital signal “111111” corresponds to the analog voltage signal V64. That is, a digital signal whose most significant bit D5 is “1” corresponds to the first voltage signal group V33 to V64. In other words, the most significant bit D5 (upper bit group) is related to the selection of either the first voltage signal group V33 to V64 or the second voltage signal group V1 to V32. On the other hand, the lower bit group (D0 to D4) relates to one analog voltage signal in the first voltage signal group V33 to V64 or the second voltage signal group V1 to V32.

  The D / A converter circuit according to the embodiment of the present invention receives the digital signals D0 to D5 and outputs one analog voltage signal corresponding to the digital signals D0 to D5 among the plurality of analog voltage signals V1 to V64. Output. Hereinafter, the configuration, operation and effect of the D / A conversion circuit will be described in detail.

(Circuit configuration)
FIG. 3 is a circuit block diagram showing a configuration of the D / A conversion circuit 1 according to the embodiment of the present invention. As shown in FIG. 3, the D / A conversion circuit 1 receives a digital signal (upper bit group D5, lower bit group D0 to D4) and a plurality of analog voltage signals V1 to V64. The D / A conversion circuit 1 includes a first D / A converter 11, a second D / A converter 12, a precharge circuit 15, a buffer 17, an output terminal 18, and a selection circuit 19. .

  The first D / A converter 11 receives the lower bit groups D0 to D4 of the digital signal and the first voltage signal groups V33 to V64. Then, the first D / A converter 11 selects an analog voltage signal corresponding to the lower bit groups D0 to D4 among the first voltage signal groups V33 to V64. An analog voltage signal selected from the first voltage signal group V33 to V64 is referred to as a “first analog voltage signal”. The first analog voltage signal is output from the first D / A converter 11 to the selection circuit 19.

  The second D / A converter 12 receives the lower bit groups D0 to D4 and the second voltage signal groups V1 to V32 of the digital signal. Then, the second D / A converter 12 selects an analog voltage signal corresponding to the lower bit groups D0 to D4 among the second voltage signal groups V1 to V32. An analog voltage signal selected from the second voltage signal group V1 to V32 is referred to as a “second analog voltage signal”. The second analog voltage signal is output from the second D / A converter 12 to the selection circuit 19.

  The circuit configurations of the first D / A converter 11 and the second D / A converter 12 are illustrated in FIGS. 4A and 4B. For simplicity, the case of a 2-bit digital signal (D0, D1) will be described. The D / A converter shown in FIG. 4A includes inverters a1 and a2, AND circuits a3 to a6, and transistors (switches) a7 to a10. The digital signal is decoded by logic circuits such as inverters a1 and a2 and AND circuits a3 to a6. As a result, one of the four switches a7 to a10 is turned on, and one voltage corresponding to the digital signal is output from the four types of voltages V1 to V4. The D / A converter shown in FIG. 4B includes a plurality of transistors b1 to b16 and inverters b17 and b18. However, the transistors b1, b3, b5, b8, b10, b11, b14, and b16 are enhancement type transistors, and the other transistors are always on depletion type transistors. Either a digital signal (D0, D1) or its inverted signal is input to the gate of each transistor. Thereby, one voltage according to a digital signal is output among four types of voltages V1-V4. Even when the number of bits of the digital signal is different, the D / A converter is realized by the same principle. Although not shown, the first and second D / A converters 11 and 12 may be R-2R type or switched capacitor type D / A converters. In these systems, since the D / A converter includes a buffer therein, a buffer 17 described later may be deleted.

  According to the present embodiment, the first D / A converter 11 is configured to operate at least in the first voltage range (first voltage to second voltage: see FIG. 2). A positive voltage VDD is exemplified as the first voltage, and a system ground GND is exemplified as the second voltage. In this case, the first D / A converter 11 is configured to operate in the positive voltage range VDD to GND. The first D / A converter 11 receives the first voltage signal group V33 to V64 corresponding to the positive voltage range VDD to GND, and receives the first analog voltage signal from the first voltage signal group V33 to V64. Select. The lower bit groups D0 to D4 input to the first D / A converter 11 may be adjusted by the level shift circuit or the like so as to conform to the first voltage range VDD to GND.

  Further, the second D / A converter 12 is configured to operate at least in the second voltage range (third voltage to fourth voltage: see FIG. 2). The system ground GND is exemplified as the third voltage, and the negative voltage VEE is exemplified as the fourth voltage. In this case, the second D / A converter 12 is configured to operate in the negative voltage range GND to VEE. The second D / A converter 12 receives the second voltage signal group V1 to V32 corresponding to the negative voltage range GND to VEE and receives the second analog voltage signal from the second voltage signal group V1 to V32. Select. The lower bit groups D0 to D4 input to the second D / A converter 12 may be adjusted by the level shift circuit or the like so as to conform to the second voltage range GND to VEE.

  In the above example, the second voltage and the third voltage are the same and are the system ground GND. However, the second voltage and the third voltage are different as long as the relationship of “first voltage> second voltage> fourth voltage, first voltage> third voltage> fourth voltage” is satisfied. The voltage may be

  Next, the selection circuit 19 will be described. The selection circuit 19 according to the present embodiment is interposed between the first and second D / A converters 11 and 12 and the output terminal 18. The selection circuit 19 receives the first analog voltage signal described above from the first D / A converter 11 and the second analog voltage signal described above from the second D / A converter 12. Further, the selection circuit 19 receives the upper bit group (most significant bit D5) of the digital signal. As described above, the most significant bit D5 indicates one of the first voltage signal group V33 to V64 and the second voltage signal group V1 to V32 depending on the value thereof. The first analog voltage signal is an analog voltage signal selected from the first voltage signal group V33 to V64, and the second analog voltage signal is selected from the second voltage signal group V1 to V32. Analog voltage signal. Therefore, the selection circuit 19 can select either the first analog voltage signal or the second analog voltage signal according to the most significant bit D5.

  More specifically, as shown in FIG. 3, the selection circuit 19 according to the present embodiment includes a switch 13 and a switch 14. The switch 13 is connected to the output of the first D / A converter 11 and the node 16. The switch 14 is connected to the output of the second D / A converter 12 and the node 16. When the most significant bit D5 is “1”, the switch 13 is closed and the switch 14 is opened. As a result, the first analog voltage signal selected by the first D / A converter 11 is output to the node 16. On the other hand, when the most significant bit D5 is “0”, the switch 13 is opened and the switch 14 is closed. As a result, the second analog voltage signal selected by the second D / A converter 12 is output to the node 16. As described above, the selection circuit 19 outputs either the first analog voltage signal or the second analog voltage signal to the node 16 based on the most significant bit D5.

  The selection circuit 19 handles all analog voltage signals V1 to V64. Therefore, the selection circuit 19 according to the present embodiment is configured to operate in the third voltage range (see FIG. 2). In the case of the above example, the selection circuit 19 is configured to operate at least in the voltage range VDD to VEE. Further, the upper bit D5 input to the selection circuit 19 may be adjusted by the level shift circuit or the like so as to be adapted to the third voltage range VDD to VEE.

  Next, the buffer 17 will be described. The buffer 17 is disposed between the selection circuit 19 and an output terminal 18 for outputting one analog voltage signal determined by the selection circuit 19 to the outside. Specifically, as shown in FIG. 3, the buffer 17 is interposed between the node 16 and the output terminal 18. Similar to the selection circuit 19, the buffer 17 is also configured to operate in the third voltage range (see FIG. 2). In the case of the above example, the buffer 17 is configured to operate at least in the voltage range VDD to VEE. The buffer 17 can drive the analog voltage signal at high speed. The buffer 17 is preferably a voltage follower, but may be an amplifier having an output / input characteristic larger than 1.

  Next, the precharge circuit 15 will be described. The precharge circuit 15 according to the present embodiment is connected to the node 16, that is, the outputs of the switch 13 and the switch 14 of the selection circuit 19. The precharge circuit 15 receives the upper bit group (most significant bit D5) of the digital signal and precharges the node 16 to a predetermined voltage according to the upper bit group. In other words, the precharge circuit 15 precharges the wiring connecting the selection circuit 19 and the output terminal 18 (buffer 17) to a predetermined voltage based on the upper bit group.

  The reason why the node 16 is precharged to a predetermined voltage is to prevent a voltage exceeding the withstand voltage from being applied to the first D / A converter 11 and the second D / A converter 12 via the selection circuit 19. It is. Therefore, the precharge operation is executed in a state where both the switch 13 and the switch 14 of the selection circuit 19 are open. In other words, after the selection circuit 19 disconnects the electrical connection between the precharge circuit 15 (node 16) and the first and second D / A converters 11 and 12, the precharge circuit sets the node 16 to a predetermined voltage. To precharge. The predetermined voltage is preferably either the second voltage or the third voltage. For example, when the most significant bit D5 is “1”, the precharge circuit 15 applies the second voltage to the node 16, and when the most significant bit D5 is “0”, the precharge circuit 15 A voltage is applied to node 16.

  In the case of the above example, the predetermined voltage precharged at the node 16 is the system ground GND. In this case, as shown in FIG. 3, the precharge circuit 15 has a precharge switch interposed between the ground and the node 16. This precharge switch is controlled by the upper bit group. For example, when the value of the upper bit group (most significant bit D5) changes, the node 16 is precharged to the system ground GND.

  In order to specifically explain the operation and effect of the precharge circuit 15, consider the following example. It is assumed that the operating voltage of the first D / A converter 11 is +3 to 0 V (first voltage range VDD to GND). Further, it is assumed that the operating voltage of the second D / A converter 12 is 0 to −3 V (second voltage range GND to VEE) and the withstand voltage thereof is 4 V. In this case, a voltage can be applied to the second D / A converter 12 only up to + 1V. When the precharge circuit 15 is not provided, a voltage of +1 V or more may be applied to the second D / A converter 12 by the analog voltage signals V33 to V64 selected by the first D / A converter 11. is there. This leads to a significant decrease in device life. According to the present embodiment, when the value of the upper bit group changes, the switch 13 and the switch 14 of the selection circuit 19 are turned off, and the precharge circuit 15 precharges the node 16 to the system ground GND. As a result, it is possible to prevent the first D / A converter 11 and the second D / A converter 12 from being applied with a voltage higher than the withstand voltage. Therefore, a reduction in device life is prevented. As with the selection circuit 19, the precharge circuit 15 may be configured to operate in the third voltage range (see FIG. 2).

(Operation example)
Next, the overall operation of the D / A conversion circuit 1 according to the present embodiment will be described with reference to FIG. As an example, consider a case where 6-bit digital signals “000000”, “100000”, and “111111” are input. First, a digital signal “000000” is input. At this time, the upper bit group is “0” and the lower bit group is “00000”. The first D / A converter 11 and the second D / A converter 12 send the first analog voltage signal V33 and the second analog voltage signal V1 to the selection circuit 19 according to the lower bit group, respectively. Output. In the selection circuit 19, the switch 13 is turned off and the switch 14 is turned on in accordance with the upper bit group. As a result, the second analog voltage signal V <b> 1 is output from the output terminal 18 through the buffer 17.

  Subsequently, the digital signal “100000” is input. At this time, the upper bit group is “1” and the lower bit group is “00000”. Since the upper bit group (most significant bit D5) is changed from “0” to “1”, the switch 13 and the switch 14 of the selection circuit 19 are turned off, and the precharge circuit 15 causes the node 16 to be set to the system ground GND. Precharge. Thereafter, the first D / A converter 11 and the second D / A converter 12 select the first analog voltage signal V33 and the second analog voltage signal V1, respectively, according to the lower-order bit group. Output to. In the selection circuit 19, the switch 13 is turned on and the switch 14 is turned off according to the upper bit group. As a result, the first analog voltage signal V <b> 33 is output from the output terminal 18 through the buffer 17.

  Subsequently, the digital signal “111111” is input. At this time, the upper bit group is “1” and the lower bit group is “11111”. Since the upper bit group (most significant bit D5) remains “1”, only the switch 13 is kept on and no precharge operation is performed. That is, when the upper bit group does not change, there is no possibility that a voltage higher than the withstand voltage is applied to the D / A converters 11 and 12, so the precharge operation is not performed. As a result, it is possible to reduce useless charging / discharging power due to precharging. The first D / A converter 11 and the second D / A converter 12 output the first analog voltage signal V64 and the second analog voltage signal V32 to the selection circuit 19 according to the lower bit group, respectively. To do. In the selection circuit 19, the switch 13 is turned on and the switch 14 is turned off. As a result, the first analog voltage signal V64 is output from the output terminal 18 through the buffer 17.

  Thus, the analog voltage signals V1, V33, and V64 corresponding to the digital signals “000000”, “100000”, and “111111” are output from the output terminal 18, respectively. That is, the D / A conversion circuit 1 according to the present embodiment realizes a desired operation as a “D / A conversion circuit”.

(Element structure)
In the present embodiment, the selection circuit 19, the precharge circuit 15, and the buffer 17 are configured to operate in the third voltage range VDD to VEE, and they are manufactured by “high voltage elements”. As described above, the first D / A converter 11 is configured to operate in the first voltage range VDD to GND. Therefore, the first D / A converter 11 can be manufactured with an “intermediate voltage element” having a lower withstand voltage than the high voltage element. As described above, the second D / A converter 12 is configured to operate in the second voltage range GND to VEE. Therefore, the second D / A converter 12 can be manufactured with an “intermediate voltage element” having a lower withstand voltage than the high voltage element. Features that appear due to such differences in operating voltage and withstand voltage will be described below.

FIG. 5 is a top view schematically showing a layout of the D / A conversion circuit 1 according to the present embodiment. Since the operation voltage (use voltage) of each circuit is different, circuits having different use voltages are arranged in different regions on the substrate. For example, the first D / A converter 11 operating in the first voltage range VDD to GND is formed in the first continuous region R1 on the substrate 100. The second D / A converter 12 that operates in the second voltage range GND to VEE is formed in the second continuous region R <b> 2 on the substrate 100. The selection circuit 19, the precharge circuit 15, and the buffer 17 that operate in the third voltage range VDD to VEE are formed in the third continuous region R3 on the substrate 100. Each continuous region is separated by using a deep well layer, and a different range of voltage is applied to each continuous region R1-R3. When a plurality of D / A conversion circuits 1 are formed, the plurality of first D / A converters 11 are continuously arranged in the continuous region R1, and the plurality of second D / A converters 12 are continuous regions. It is sufficient that the plurality of selection circuits 19 are continuously arranged in the continuous region R3.

  FIG. 6 is a cross-sectional view schematically showing a structure taken along line B-B ′ in FIG. 5. A first N well 110, a second N well 120, and a third N well 130 are formed in the P-type substrate 100. The first to third continuous regions R1 to R3 described above correspond to the first to third N wells 110, 120, and 130, respectively.

A P well 112 is formed in the first N well 110. The first voltage VDD and the system ground GND are applied to the first N well 110 and the P well 112, respectively . A P channel MOS transistor Q1p is formed on the first N well 110, and an N channel MOS transistor Q1n is formed on the P well 112. A gate electrode of each MOS transistor is formed on the substrate 100 via a gate oxide film 114. The MOS transistors Q1p and Q1n constitute a first D / A converter 11 that operates in the first voltage range VDD to GND. That is, the MOS transistors Q1p and Q1n are medium voltage elements.

A P well 122 is formed in the second N well 120. The system ground GND and the fourth voltage VEE are applied to the second N well 120 and the P well 122, respectively . A P channel MOS transistor Q2p is formed on the second N well 120, and an N channel MOS transistor Q2n is formed on the P well 122. A gate electrode of each MOS transistor is formed on the substrate 100 via a gate oxide film 124. The MOS transistors Q2p and Q2n constitute a second D / A converter 12 that operates in the second voltage range GND to VEE. That is, the MOS transistors Q2p and Q2n are medium voltage elements.

  The first voltage VDD and the fourth voltage VEE are applied to the third N well 130 and the P-type substrate 100. However, a voltage equal to or higher than the first voltage VDD may be applied to the third N well 130, and a voltage equal to or higher than the fourth voltage VEE may be applied to the P-type substrate 100. A P-channel MOS transistor Q3p is formed on the third N well 130, and an N-channel MOS transistor Q3n is formed on the P-type substrate 100. A gate electrode of each MOS transistor is formed on the substrate 100 via a gate oxide film 134. These MOS transistors Q3p and Q3n constitute a selection circuit 19, a precharge circuit 15, and a buffer 17 that operate in the third voltage range VDD to VEE. That is, the MOS transistors Q3p and Q3n are high voltage elements.

  Here, the withstand voltages of the MOS transistors Q1p, Q1n, Q2p, and Q2n that are medium voltage elements may be smaller than the withstand voltages of the MOS transistors Q3p and Q3n that are high voltage elements. Accordingly, the gate oxide films 114 and 124 of the MOS transistor formed in the first and second continuous regions R1 and R2 are made thinner than the gate oxide film 134 of the MOS transistor formed in the third continuous region R3. It is possible to design. Also, the gate length L of the MOS transistor formed in the first and second continuous regions R1 and R2 is designed to be shorter than the gate length L of the MOS transistor formed in the third continuous region R3. Is possible. Furthermore, the gate width W of the MOS transistor formed in the first and second continuous regions R1 and R2 is designed to be smaller than the gate width W of the MOS transistor formed in the third continuous region R3. Is possible. That is, according to the present embodiment, the circuit areas of the first D / A converter 11 and the second D / A converter 12 can be reduced. As a result, the circuit area of the D / A conversion circuit 1 is reduced as compared with the prior art.

(effect)
As described above, according to the present embodiment, the first D / A converter 11 and the second D / A converter 12 are manufactured with medium voltage elements. Thereby, the circuit area of the D / A conversion circuit 1 is reduced. In general, the area of the D / A conversion circuit increases as the number of bits of the digital signal increases. Therefore, the D / A conversion circuit 1 according to the present invention is particularly suitable when the number of bits is large.

  In addition, since the operating voltages of the first D / A converter 11 and the second D / A converter 12 are reduced, the power consumption of the D / A converter circuit 1 can be reduced. In addition, the precharge circuit 15 prevents the first D / A converter 11 and the second D / A converter 12 from being applied with a voltage higher than the withstand voltage, and prevents a decrease in the element lifetime. The precharge circuit 15 preferably performs a precharge operation only when the value of the upper bit group changes. As a result, it is possible to reduce useless charging / discharging power due to precharging.

(Application example)
Hereinafter, an example of a semiconductor device to which the D / A conversion circuit 1 according to the present invention is applied will be described in detail. For example, the D / A conversion circuit 1 according to the present invention is applied to a display device that displays image data supplied as digital data, and is used in a display driver that drives the display device. In this case, the digital signals D0 to D5 are pixel data displayed on the pixels of the display panel. The analog voltage signals V1 to V64 are gradation signals indicating pixel voltages (gradation voltages) applied to the pixels. The D / A conversion circuit 1 converts the pixel data into a gradation signal corresponding to the pixel data. Examples of the display device include a liquid crystal display device, a plasma display device, and an organic EL display device. In the following description, a liquid crystal display device is given as an example.

  FIG. 7 is a block diagram showing a configuration of the liquid crystal display device 60 according to the present embodiment. The liquid crystal display device 60 includes a data line driving circuit 61, a scanning line driving circuit 62, a display panel 63, a control circuit 67, and a power supply circuit 68.

  In the display panel 63, a plurality of data lines 64 connected to the data line driving circuit 61 and a plurality of scanning lines 65 connected to the scanning line driving circuit 62 are formed. The plurality of data lines 64 and the plurality of scanning lines 65 are formed so as to intersect with each other, and a plurality of pixels 66 are formed at each of the plurality of intersections. That is, the display panel 63 includes a plurality of pixels 66 (for example, 1080 × 1920 pixels 66) arranged in a matrix. Each pixel 6 includes a TFT (Thin Film Transistor), a liquid crystal, and a common electrode. The gate terminal of the TFT is connected to the scanning line 65, and the source terminal or drain terminal of the TFT is connected to the data line 64. One end of the liquid crystal is connected to the source terminal or drain terminal of the TFT, and the other end is connected to a common electrode to which a constant common voltage is applied.

  The control circuit 67 outputs a scanning line driving signal group for controlling the scanning line driving circuit 62 to the scanning line driving circuit 62. The scanning line driving circuit (gate driver) 62 sequentially drives the plurality of scanning lines 65 in accordance with the scanning line driving signal group. The control circuit 67 outputs a data line driving signal group for controlling the data line driving circuit 61 and a video signal which is digital data to the data line driving circuit 61. The data line driving circuit (source driver) 61 drives a plurality of data lines 64 in accordance with a data line driving signal group. Specifically, the data line driving circuit 61 outputs a gradation signal (analog voltage signal) corresponding to the video signal to each of the plurality of data lines 64. As a result, a gradation voltage (pixel voltage) corresponding to the video signal is applied to each of the plurality of pixels 66 connected to the selected one scanning line 65. By driving the plurality of scanning lines 65 in order, an image is displayed on the display panel 63.

  The power supply circuit 68 generates operating voltages for the data line driving circuit 61 and the scanning line driving circuit 62 from the power supply voltage VDC supplied to the liquid crystal display device 60. Further, the power supply circuit 68 has a common voltage generation circuit 69. The common voltage generation circuit 69 supplies a common voltage to the common electrode.

  The D / A conversion circuit 1 according to the present invention is applied to a data line driving circuit 61 for outputting a gradation signal (analog voltage signal) to the data line 64. Since the data line driving circuit 61 drives each of the plurality of data lines 64, a plurality of D / A conversion circuits 1 are provided in each of the plurality of data lines 64. Thus, since the data line driving circuit 61 requires a large number of D / A conversion circuits, the D / A conversion circuit 1 according to the present invention having a reduced circuit area is particularly suitable.

(First embodiment)
(Circuit configuration)
FIG. 8 is a circuit block diagram showing a configuration of the data line driving circuit 61 according to the first embodiment of the present invention. The data line driving circuit 61 according to the present embodiment includes the D / A conversion circuit 1, the level shift circuit group 2, the logic circuit 3, and the gradation voltage generation circuit 4 shown in FIG. The output terminal 18 of the D / A conversion circuit 1 is connected to a certain data line 64 among the plurality of data lines 64. Then, one gradation signal (analog voltage signal) selected by the D / A conversion circuit 1 is supplied to the data line 64 and a certain pixel 66 via the output terminal 18. In FIG. 8, only one D / A conversion circuit 1 is shown, but actually, a plurality of D / A conversion circuits 1 are provided for each of the plurality of data lines 64.

  First, the gradation voltage generation circuit 4 will be described. The gradation voltage generation circuit 4 is configured to supply a plurality of gradation signals (analog voltage signals) V <b> 1 to V <b> 64 to the D / A conversion circuit 1. That is, the gradation voltage generation circuit 4 is connected to the D / A conversion circuit 1 and the gradation signals V33 to V64 corresponding to the first voltage range VDD to GND are supplied to the first D / A converter 11. The gradation signals V1 to V32 corresponding to the second voltage ranges GND to VEE are supplied to the second D / A converter 12. In order to prevent variation in each D / A conversion circuit 1, it is preferable that the gradation voltage generation circuit 4 is provided in common for a plurality of D / A conversion circuits 1.

  In the present embodiment, the gradation voltage generation circuit 4 is configured by a resistor string circuit that is excellent in monotonic increase. For example, FIG. 9A shows a resistor string circuit in which a plurality of resistors R1 to R64 are connected in series. Reference voltages Vref1, Vref2, and GND are supplied to the resistor string circuit, and a plurality of gradation voltages V1 to V64 are generated from respective connection points. In this case, the gradation voltages V32 and V33, which are halftones, are voltages near the system ground GND. FIG. 9B shows a resistor string circuit in which a plurality of resistors R1 to R63 are connected in series. Reference voltages Vref1, Vref2, and GND are supplied to the resistor string circuit, and a plurality of gradation voltages V1 to V64 are generated from respective connection points. In this case, the gradation voltage V32 which is a halftone is the system ground GND. The gradation voltages V64 to V33 are gradation voltages in the first voltage range VDD to GND, and are output to the first D / A converter 11. The gradation voltages V32 to V1 are gradation voltages in the second voltage range GND to VEE and are output to the second D / A converter 12.

  FIG. 10 shows a correspondence relationship between the gradation voltage and the gradation in the pixel 66. When the gradation voltage and the gradation have a linear relationship as shown by a solid line in FIG. 10, the plurality of resistors (R1 to R64) are designed to have the same resistance value. In addition, in order to adjust the difference between the light transmission characteristics of the liquid crystal material and the human visual characteristics and perform natural gradation display, the correspondence between the gradation voltage and the gradation may be corrected. This correction is called gamma correction. In this case, the correspondence between the gradation voltage and the gradation is set so as to be non-linear as shown by the dotted line in FIG. In order to perform gamma correction, the resistance values of the plurality of resistors (R1 to R64) may be adjusted so that the function indicated by the dotted line in FIG. 10 is obtained. Although not shown, a buffer such as a voltage follower may be provided between the gradation voltage generation circuit 4 and the first and second D / A converters 11 and 12. In that case, the above-described buffer 17 may be deleted.

  Next, the logic circuit 3 will be described. The logic circuit 3 receives digital signals D0 to D5 indicating pixel data, and supplies the upper bit group D5 and the lower bit groups D0 to D4 to the D / A conversion circuit 1. Specifically, the logic circuit 3 includes a latch circuit 31 that latches the 6-bit digital signals D0 to D5 in response to the latch signal LAT. The latch circuit 31 outputs the lower bit groups D0 to D4 of the digital signal to the first D / A converter 11 and the second D / A converter 12. The latch circuit 31 outputs the upper bit group D5 of the digital signal to the selection circuit 19 and the precharge circuit 15. The D / A conversion circuit 1 performs the above-described operation in response to the upper bit group D5 and the lower bit groups D0 to D4.

  Further, the logic circuit 3 according to the present embodiment may include a change detection circuit 33 as shown in FIG. The change detection circuit 33 is a circuit for controlling the precharge operation, and detects a change in the value of the upper bit group D5 of the digital signal. In order to detect a change in the upper bit group D5, the change detection circuit 33 is configured by a logic circuit such as an EXOR circuit or a latch circuit. When a change in the value of the upper bit group D5 is detected, the change detection circuit 33 outputs the switch control signal SWCNT to the selection circuit 19 and the precharge circuit 15 while the latch signal LAT is Hi. In response to the switch control signal SWCNT, the selection circuit 19 temporarily turns off the switch 13 and the switch 14. Meanwhile, the precharge circuit 15 precharges the node 16 to the system ground GND in response to the switch control signal SWCNT. The change detection circuit 33 may be provided in each of the selection circuit 19 and the precharge circuit 15 instead of being provided in the logic circuit 3.

  In the present embodiment, the latch circuit 31 is configured to operate in a voltage range between the voltage VCC and the ground voltage GND. This voltage VCC is, for example, 2V, unlike the voltage VDD (example: + 3V) and the voltage VEE (example: -3V). In this case, the voltages of the digital signals D0 to D5 input to the latch circuit 31 are the voltage VCC and the ground voltage GND. In order to adapt the voltage of the digital signals D0 to D5 output from the latch circuit 31 to the operating voltage of the D / A conversion circuit 1, according to the present embodiment, the logic circuit 3 and the D / A conversion circuit 1 A level shift circuit group 2 is interposed therebetween. As shown in FIG. 8, the level shift circuit group 2 includes a first level shift circuit 21, a second level shift circuit 22, and a third level shift circuit 23.

  The first level shift circuit 21 is provided between the latch circuit 31 and the first D / A converter 11. The first level shift circuit 21 receives the lower bit groups D0 to D4 from the latch circuit 31, and converts the lower bit groups so as to conform to the first voltage range VDD (3V) to GND. Then, the first level shift circuit 21 outputs the lower bit groups D0 to D5 after the level shift to the first D / A converter 11.

  The second level shift circuit 22 is provided between the latch circuit 31 and the second D / A converter 12. The second level shift circuit 22 receives the lower bit groups D0 to D4 from the latch circuit 31, and converts the lower bit groups so as to conform to the second voltage range GND to VEE (-3V). Then, the second level shift circuit 22 outputs the lower bit groups D0 to D5 after the level shift to the second D / A converter 12.

  FIG. 11 shows an example of the configuration of the first level shift circuit 21 and the second level shift circuit 22. The first level shift circuit 21 is a well-known level shifter composed of P-channel transistors P1 and P2 and N-channel transistors N1 and N2. The first level shift circuit 21 is configured to operate in a voltage range from the first voltage VDD (3 V) to the second voltage GND. That is, the first level shift circuit 21 is a medium voltage system, and the transistors P1, P2, N1, and N2 are medium voltage elements. The second level shift circuit 22 includes a well-known level shifter including P-channel transistors P3 and P4 and N-channel transistors N3 and N4, and P-channel transistors P5 and P6, and N-channel transistors N5 and N6. And a well-known level shifter. The second level shift circuit 22 is configured to operate in a voltage range from the voltage VCC (2 V) to the fourth voltage VEE (−3 V). That is, the second level shift circuit 22 is a high voltage system, and the transistors P3 to P6 and N3 to N6 are high voltage elements.

  The third level shift circuit 23 is provided between the logic circuit 3 (change detection circuit 33), the selection circuit 19, and the precharge circuit 15. The third level shift circuit 23 receives the upper bit group D5 from the logic circuit 3, or receives the switch control signal SWCNT from the change detection circuit 33. Then, the third level shift circuit 23 converts the upper bit group D5 or the switch control signal SWCNT so as to conform to the third voltage range VDD (3V) to VEE (-3V). Thereafter, the third level shift circuit 23 outputs the upper bit group D5 or the switch control signal SWCNT after the level shift to the selection circuit 19 and the precharge circuit 15.

  FIG. 12 shows an example of the configuration of the third level shift circuit 23. The third level shift circuit 23 includes a well-known level shifter including P-channel transistors P7 and P8 and N-channel transistors N7 and N8, and P-channel transistors P9 and P10 and N-channel transistors N9 and N10. And a known level shifter. The third level shift circuit 23 is configured to operate in the voltage range from the first voltage VDD (3 V) to the fourth voltage VEE (−3 V). That is, the third level shift circuit 23 is a high voltage system, and the transistors P7 to P10 and N7 to N10 are high voltage elements.

(Operation example)
Next, the overall operation of the data line driving circuit 61 according to the present embodiment will be described. FIG. 13 is a timing chart showing an example of the operation of the data line driving circuit 61. First, the digital signal “000000” is input to the D / A conversion circuit 1, and the gradation voltage V 1 is output from the output terminal 18 (OUT) of the D / A conversion circuit 1.

  Next, the latch signal LAT changes from Low to Hi, and the latch circuit 31 latches the digital signal “111111”. At this time, since the upper bit group D5 has changed from “0” to “1”, the change detection circuit 33 outputs the switch control signal SWCNT to the selection circuit 19 and the precharge circuit 15. During the period when the latch signal LAT is Hi, the selection circuit 19 turns off the switch 13 and the switch 14, and the precharge circuit 15 precharges the node 16 to the system ground GND. At this time, the system ground GND is output from the output terminal 18. When the latch signal LAT changes from Hi to Low, the change detection circuit 33 stops outputting the switch control signal SWCNT. The selection circuit 19 turns on the switch 13 in accordance with the upper bit group D5. As a result, the gradation voltage V64 is output from the output terminal 18. By this precharge operation, the possibility that the gradation voltage V64 is applied to the second D / A converter 12 is eliminated.

  Next, the latch signal LAT changes from Low to Hi, and the latch circuit 31 latches the digital signal “110000”. At this time, since the upper bit group D5 remains “1”, the precharge operation is not performed, and the state in which the switch 13 is turned on is maintained. From the output terminal 18, a gradation voltage V49 corresponding to the digital signal is output. Thus, since the precharge operation is not performed when the upper bit group does not change, useless charge / discharge power is reduced.

  Next, the latch signal LAT changes from Low to Hi, and the latch circuit 31 latches the digital signal “010000”. At this time, since the upper bit group D5 is changed from “1” to “0”, the precharge operation is executed. During the period when the latch signal LAT is Hi, the system ground GND is output from the output terminal 18. When the latch signal LAT changes from Hi to Low, the selection circuit 19 turns on the switch 14 according to the upper bit group D5. As a result, the gradation voltage V17 is output from the output terminal 18. Next, the latch circuit 31 latches the digital signal “000000”, and the gradation voltage V 1 is output from the output terminal 18.

(Element structure)
In the present embodiment, the logic circuits 3 such as the latch circuit 31 and the change detection circuit 33 are configured to operate in the voltage range VCC to GND, and are manufactured with a low voltage element (for example, 2V). The first D / A converter 11 is configured to operate in the first voltage range VDD to GND, and is manufactured with an intermediate voltage element (for example, 3 V). The second D / A converter 12 is configured to operate in the second voltage range GND to VEE and is manufactured with a medium voltage element. The first level shift circuit 21 is configured to operate in the first voltage range VDD to GND, and is manufactured with an intermediate voltage element. The second level shift circuit 22 is configured to operate at least in the voltage range VCC to VEE, and is manufactured with a high voltage element (for example, 6 V). The third level shift circuit 23, the selection circuit 19, the precharge circuit 15, and the buffer 17 are configured to operate in the third voltage range VDD to VEE, and they are manufactured with high voltage elements. When the gradation voltage generation circuit 4 is provided with a buffer, it is preferable that the buffer is manufactured with a medium voltage element.

  Referring to FIG. 5, the first D / A converter 11 and the first level shift circuit 21 that operate in the first voltage range VDD to GND are formed in the first continuous region R1. The second D / A converter 12 operating in the second voltage range GND to VEE is formed in the second continuous region R2. The second level shift circuit 22, the third level shift circuit 23, the selection circuit 19, the precharge circuit 15, and the buffer 17 that operate in the third voltage range VDD to VEE are the third continuous region on the substrate 100. Formed in R3. The logic circuit 3 operating in the voltage range VCC to GND is formed in a fourth continuous region R4 (not shown). When a plurality of D / A conversion circuits 1 are formed, the plurality of first D / A converters 11 are continuously arranged in the continuous region R1, and the plurality of second D / A converters 12 are continuous regions. It is sufficient that the plurality of selection circuits 19 are continuously arranged in the continuous region R3.

  Further, as shown in FIG. 6, the continuous regions R1 to R3 are separated by using the deep well layers 110, 120, and 130, and different ranges of voltages are applied to the continuous regions R1 to R3. Is done. In FIG. 6, the first voltage VDD (3 V) and the fourth voltage VEE (−3 V) are applied to the third continuous region R3, but the first continuous region R3 includes the first voltage VDD (3 V). A voltage equal to or higher than the voltage VDD and a voltage equal to or lower than the fourth voltage VEE may be applied. For example, the data line driving circuit 61 and the scanning line driving circuit 62 are formed on the same substrate 100, and a voltage (for example, −5 V to 5 V) used for the operation of the scanning line driving circuit 62 is applied to the third continuous region R3. May be.

  According to the present embodiment, it is possible to design the medium voltage element formed in the first and second continuous regions R1 and R2 to be smaller than the high voltage element. That is, the gate oxide films 114 and 124 of the MOS transistor formed in the first and second continuous regions R1 and R2 are thinner than the gate oxide film 134 of the MOS transistor formed in the third continuous region R3. Designed to. In addition, the gate length L of the MOS transistor formed in the first and second continuous regions R1 and R2 is designed to be shorter than the gate length L of the MOS transistor formed in the third continuous region R3. . Further, the gate width W of the MOS transistor formed in the first and second continuous regions R1 and R2 is designed to be smaller than the gate width W of the MOS transistor formed in the third continuous region R3. . Thereby, the circuit area of the D / A conversion circuit 1 is reduced, and the circuit area of the data line driving circuit 61 is also reduced. Note that the low-voltage element formed in the fourth continuous region (not shown) can be designed to be smaller than the medium-voltage element.

(effect)
As described above, according to the present embodiment, the first D / A converter 11 and the second D / A converter 12 are manufactured with medium voltage elements. Thereby, the circuit area of the D / A conversion circuit 1 is reduced, and the circuit area of the data line driving circuit 61 is also reduced. In particular, since the data line driving circuit 61 requires a large number of D / A conversion circuits 1, the configuration according to the present invention is suitable. In general, as the number of bits of a digital signal increases, the area of the D / A conversion circuit increases and the area of the data line driving circuit also increases. Therefore, the data line driving circuit 61 according to the present invention is particularly suitable when the number of bits is large.

  In addition, since the operating voltages of the first D / A converter 11 and the second D / A converter 12 are reduced, the power consumption of the D / A converter circuit 1 is reduced and the consumption of the data line driving circuit 61 is reduced. Power is also reduced. In addition, the precharge circuit 15 prevents the first D / A converter 11 and the second D / A converter 12 from being applied with a voltage higher than the withstand voltage, and prevents a decrease in the element lifetime. The precharge circuit 15 preferably performs a precharge operation only when the value of the upper bit group changes. As a result, it is possible to reduce useless charging / discharging power due to precharging.

  Further, as shown in the above description, the second voltage and the third voltage are preferably the system ground GND. The reason is as follows. It is assumed that the power supply voltage VDC (see FIG. 7) of the liquid crystal display device 60 is 3V, and the data line driving circuit 61 operates in the voltage range of 6V to 0V as the third voltage range VDD to VEE. In this case, in order to generate the voltage of 6V, the power supply circuit 68 needs to boost the power supply voltage VDC. At this time, the efficiency in the booster circuit is about 80%. However, when the data line driving circuit 61 operates in the voltage range of 3V to −3V as the third voltage range VDD to VEE, the power supply circuit 68 does not need to boost the power supply voltage VDC. The power supply circuit 68 generates the power supply voltage of the data line driving circuit 61 from the power supply voltage VDC using the system ground GND as a reference. In this case, loss in the booster circuit is eliminated, and power consumption is reduced. As described above, the power consumption of the liquid crystal display device 60 can be reduced by setting the second voltage and the third voltage to the system ground GND.

(Second Embodiment)
When the voltage range in which the logic unit 3 operates matches the voltage range in which the first D / A converter 11 or the second D / A converter 12 operates, the first level shift circuit 21 or the second level shift circuit 21 The level shift circuit 22 can be deleted. FIG. 14 shows a configuration of the data line driving circuit 61a when the logic unit 3 operates in the same first voltage range VDD to GND as the first D / A converter 11. In FIG. 14, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The level shift circuit group 2a of the data line driving circuit 61a according to the present embodiment includes a second level shift circuit 22 and a third level shift circuit 23. The first level shift circuit 21 is omitted, and the lower bit groups D0 to D4 are directly supplied from the latch circuit 31 to the first D / A converter 11. Thereby, the circuit area of the data line driving circuit 61a is further reduced.

(Third embodiment)
The data line driving circuit 61 can execute a precharge operation with the following configuration instead of the precharge circuit 15. FIG. 15 shows the configuration of the data line driving circuit 61b according to the second embodiment of the present invention. 15, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The data line driving circuit 61b according to the present embodiment includes a D / A conversion circuit 1b, a level shift circuit group 2, and a logic circuit 3b. The D / A conversion circuit 1b is the same as the D / A conversion circuit 1 according to the first embodiment except that the D / A conversion circuit 1b does not have the precharge circuit 15.

  The logic circuit 3b according to the present embodiment includes a latch circuit 31, logic circuits 34 and 35, and a change detection circuit 36. The logic circuit 34 supplies the lower bit groups D0 to D4 received from the latch circuit 31 to the first D / A converter 11 via the first level shift circuit 21. The logic circuit 35 supplies the lower bit groups D0 to D4 received from the latch circuit 31 to the second D / A converter 12 via the second level shift circuit 22.

  The change detection circuit 36 receives the upper bit group D5 of the digital signal from the latch circuit 31, and supplies the upper bit group D5 to the selection circuit 19 via the third level shift circuit 23. The change detection circuit 36 detects a change in the value of the upper bit group D5. In order to detect a change in the upper bit group D5, the change detection circuit 36 is composed of a logic circuit such as an EXOR circuit or a latch circuit. When a change in the value of the upper bit group D5 is detected, the change detection circuit 36 outputs a control signal CNT to the logic circuits 34 and 35 of the logic circuit 3b.

  When the value of the upper bit group D5 changes, at least one of the logic circuits 34 and 35 performs the following operation, whereby the node 16 is precharged to a voltage near the system ground GND. That is, in response to the control signal CNT, the logic circuit 34 temporarily supplies data (00000) whose bit values are all 0 as the lower bit groups D0 to D4 to the first D / A converter 11. . Accordingly, the first D / A converter 11 selects the gradation voltage V33 and precharges the node 16 to the gradation voltage V33. Alternatively, in response to the control signal CNT, the logic circuit 35 temporarily supplies data (11111) whose bit values are all 1 to the second D / A converter 12 as the lower bit groups D0 to D4. . Accordingly, the second D / A converter 12 selects the gradation voltage V32 and precharges the node 16 to the gradation voltage V32.

  Thus, according to the present embodiment, when the upper bit group D5 changes, the node 16 is precharged to the gradation voltage V32 or V33 near the system ground GND. As a result, it is possible to prevent the first D / A converter 11 and the second D / A converter 12 from being applied with a voltage higher than the withstand voltage.

(Fourth embodiment)
In the above embodiment, the upper bit group is composed of the most significant bit D5, and the lower bit group is composed of bits D0 to D4. Even when the higher-order bit group includes a plurality of bits, the D / A conversion circuit according to the present invention can be realized based on the same idea as the above-described embodiment. As an example, a case where the upper bit group is composed of bits D5 and D4 and the lower bit group is composed of bits D0 to D3 will be described below.

  FIG. 16 shows a D / A conversion circuit 1 ′ and a gradation voltage generation circuit 4 according to the fourth embodiment of the present invention. In FIG. 16, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The D / A conversion circuit 1 ′ according to the present embodiment includes a first D / A converter 54, a second D / A converter 55, a third D / A converter 56, and a fourth D / A. An A converter 57, a selection circuit 19 ′, a precharge circuit 15 ′, a buffer 17, and an output terminal 18 are provided.

  The first D / A converter 54 is configured to operate in a voltage range between the fifth voltage VFF and the first voltage VDD. The first voltage VDD is lower than the fifth voltage VFF. The gradation voltage generation circuit 4 supplies a plurality of gradation signals V49 to V64 corresponding to the voltage range VFF to VDD to the first D / A converter 54. The first D / A converter 54 outputs one gradation signal corresponding to the lower bit groups D0 to D3 among the plurality of gradation signals V49 to V64 to the selection circuit 19 ′ as the first gradation signal. To do.

  The second D / A converter 55 is configured to operate in a voltage range between the first voltage VDD and the second voltage GND. The second voltage GND is lower than the first voltage VDD. The gradation voltage generation circuit 4 supplies a plurality of gradation signals V33 to V48 corresponding to the voltage range VDD to GND to the second D / A converter 55. The second D / A converter 55 outputs one gradation signal corresponding to the lower bit groups D0 to D3 among the plurality of gradation signals V33 to V48 to the selection circuit 19 ′ as the second gradation signal. To do.

  The third D / A converter 56 is configured to operate in a voltage range between the third voltage GND and the fourth voltage VEE. The fourth voltage VEE is lower than the third voltage GND. The gradation voltage generation circuit 4 supplies a plurality of gradation signals V <b> 17 to V <b> 32 corresponding to the voltage ranges GND to VEE to the third D / A converter 56. The third D / A converter 56 outputs one gradation signal corresponding to the lower bit groups D0 to D3 among the plurality of gradation signals V17 to V32 to the selection circuit 19 ′ as the third gradation signal. To do.

  The fourth D / A converter 57 is configured to operate in a voltage range between the fourth voltage VEE and the sixth voltage VGG. The sixth voltage VGG is lower than the fourth voltage VEE. The gradation voltage generation circuit 4 supplies a plurality of gradation signals V1 to V16 corresponding to the voltage ranges VEE to VGG to the fourth D / A converter 57. The fourth D / A converter 57 outputs one gradation signal corresponding to the lower bit groups D0 to D3 among the plurality of gradation signals V1 to V16 to the selection circuit 19 ′ as the fourth gradation signal. To do.

  FIG. 17 shows the correspondence between the gradation voltage and the gradation in the pixel 66. Here, + 5V is exemplified as the fifth voltage VFF. An example of the first voltage VDD is + 2V. The system ground GND is exemplified as the second voltage and the third voltage. As the fourth voltage VEE, -2V is exemplified. As the sixth voltage VGG, −4 V is exemplified. In this case, the first to fourth D / A converters 54 to 57 can be manufactured by “low voltage elements”. That is, according to the present embodiment, the circuit area of the D / A conversion circuit 1 ′ can be further reduced than the circuit area of the D / A conversion circuit 1.

  Further, as shown in FIG. 16, the selection circuit 19 ′ according to the present embodiment includes switches 13 and 14 controlled by the most significant bit D5 in the upper bit group and the upper bit D4 in the upper bit group. It has switches 50 to 53 to be controlled. Each switch of the selection circuit 19 'operates in a voltage range between a voltage equal to or higher than the fifth voltage VFF and a voltage equal to or lower than the sixth voltage VGG.

  The switch 50 is interposed between the first D / A converter 54 and the node 71 and receives the first gradation signal from the first D / A converter 54. The switch 51 is interposed between the second D / A converter 55 and the node 71 and receives the second gradation signal from the second D / A converter 55. The switches 50 and 51 output either the first gradation signal or the second gradation signal to the node 71 as an “upper gradation signal” based on the value of the upper bit D4.

  The switch 52 is interposed between the third D / A converter 56 and the node 72 and receives the third gradation signal from the third D / A converter 56. The switch 53 is interposed between the fourth D / A converter 57 and the node 72 and receives the fourth gradation signal from the fourth D / A converter 57. The switches 52 and 53 output either the third gradation signal or the fourth gradation signal to the node 72 as a “lower gradation signal” based on the value of the upper bit D4.

  The switch 13 is interposed between the node 71 and the node 16 and receives the upper gradation signal. The switch 14 is interposed between the node 72 and the node 16 and receives the lower gradation signal. Based on the value of the most significant bit D5, the switches 13 and 14 output either the upper gradation signal or the lower gradation signal to the node 16 as one gradation signal corresponding to the digital signals D0 to D5.

  Further, the precharge circuit 15 'according to the present embodiment precharges the node 16 to a predetermined voltage when the upper bit groups D4 and D5 of the digital signal change. As shown in FIG. 16, the precharge circuit 15 ′ has a switch 58 and a switch 59. The switch 58 temporarily precharges the node 16 to the first voltage VDD when the upper bit groups D4 and D5 change. The switch 59 temporarily precharges the node 16 to the fourth voltage VEE when the upper bit groups D4 and D5 change.

  When the most significant bit D5 changes from “0” to “1”, that is, when the upper bit group (D5, D4) changes from “00” or “01” to “10” or “11”, Such an operation is performed. First, the switches 14, 50 to 53, and 59 are temporarily turned off, and the switches 13 and 58 are temporarily turned on. As a result, the nodes 16 and 71 are precharged to the first voltage VDD. Thereafter, the switch 58 is turned off, and the precharge operation ends. Next, the switch 50 or the switch 51 is turned on according to the upper bit D4, and a desired gradation signal is selected.

  When the most significant bit D5 changes from “1” to “0”, that is, when the upper bit group (D5, D4) changes from “10” or “11” to “00” or “01”, Such an operation is performed. First, the switches 13, 50 to 53, and 58 are temporarily turned off, and the switches 14 and 59 are temporarily turned on. As a result, the nodes 16 and 72 are precharged to the fourth voltage VEE. Thereafter, the switch 59 is turned off, and the precharge operation ends. Next, according to the upper bit D4, the switch 52 or the switch 53 is turned on, and a desired gradation signal is selected.

  When the most significant bit D5 remains “0” and the upper bit D4 changes, that is, the upper bit group (D5, D4) changes from “00” to “01” or from “01” to “00” When doing so, the following operations are performed. First, the switches 13, 50 to 53, and 58 are temporarily turned off, and the switches 14 and 59 are temporarily turned on. As a result, the nodes 16 and 72 are precharged to the fourth voltage VEE. Thereafter, the switch 59 is turned off, and the precharge operation ends. Next, according to the upper bit D4, the switch 52 or the switch 53 is turned on, and a desired gradation signal is selected.

  When the most significant bit D5 remains “1” and the upper bit D4 changes, that is, the upper bit group (D5, D4) changes from “10” to “11”, or from “11” to “10”. When doing so, the following operations are performed. First, the switches 14, 50 to 53, and 59 are temporarily turned off, and the switches 13 and 58 are temporarily turned on. As a result, the nodes 16 and 71 are precharged to the first voltage VDD. Thereafter, the switch 58 is turned off, and the precharge operation ends. Next, the switch 50 or the switch 51 is turned on according to the upper bit D4, and a desired gradation signal is selected.

  Such a precharge operation prevents the D / A converters 54 to 57 from being applied with a voltage exceeding the withstand voltage. In addition, since the precharge operation is performed only when the value of the upper bit group changes, it is possible to reduce unnecessary charge / discharge power due to precharge.

  The level shift circuit group 2 is configured in the same manner as in the above embodiment.

  According to the present embodiment, the selection circuit 19 ′, the precharge circuit 15 ′, and the buffer 17 are manufactured with high voltage elements. On the other hand, the D / A converters 54 to 57 are manufactured with low voltage elements. Accordingly, the circuit areas of the D / A conversion circuit 1 'and the data line driving circuit are further reduced. Further, since the operating voltages of the D / A converters 54 to 57 are low, the power consumption of the D / A conversion circuit 1 ′ can be reduced.

  As described above, according to the present invention, the circuit area of the D / A conversion circuit can be reduced. In addition, the power consumption of the D / A conversion circuit can be reduced. Furthermore, it becomes possible to reduce the power consumption of the display device using the D / A conversion circuit. The D / A conversion circuit according to the present invention can be applied not only to a display device but also to a sound source of a mobile phone, a printer head, and the like. The substrate on which the D / A conversion circuit is integrated may be a semiconductor substrate other than silicon, a glass substrate, a plastic substrate, or the like. The transistor is not limited to a MOS transistor but may be a bipolar transistor, an organic transistor, or the like.

FIG. 1 is a conceptual diagram showing a digital signal in the embodiment of the present invention. FIG. 2 is a conceptual diagram showing an analog voltage signal in the embodiment of the present invention. FIG. 3 is a circuit block diagram showing a configuration of the D / A conversion circuit according to the embodiment of the present invention. FIG. 4A is a circuit diagram showing an example of the configuration of the D / A converter according to the embodiment of the present invention. FIG. 4B is a circuit diagram showing another example of the configuration of the D / A converter according to the embodiment of the present invention. FIG. 5 is a top view schematically showing a layout of the D / A conversion circuit according to the embodiment of the present invention. FIG. 6 is a cross-sectional view schematically showing a structure taken along line B-B ′ in FIG. 5. FIG. 7 is a block diagram showing the configuration of the liquid crystal display device according to the embodiment of the present invention. FIG. 8 is a circuit block diagram showing the configuration of the display driver according to the first embodiment of the present invention. FIG. 9A is a circuit block diagram showing an example of the configuration of the grayscale voltage generation circuit according to this embodiment. FIG. 9B is a circuit block diagram illustrating another example of the configuration of the grayscale voltage generation circuit according to this embodiment. FIG. 10 is a diagram showing the relationship between the gradation voltage and the gradation in this embodiment. FIG. 11 is a circuit diagram showing a configuration of the level shift circuit in the present embodiment. FIG. 12 is a circuit diagram showing the configuration of the level shift circuit in the present embodiment. FIG. 13 is a timing chart showing the operation of the display driver according to the present embodiment. FIG. 14 is a circuit block diagram showing a configuration of a display driver according to the second embodiment of the present invention. FIG. 15 is a circuit block diagram showing a configuration of a display driver according to the third embodiment of the present invention. FIG. 16 is a circuit block diagram showing a configuration of a D / A conversion circuit according to the fourth embodiment of the present invention. FIG. 17 is a diagram showing the relationship between the gradation voltage and the gradation in this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 D / A converter circuit 2 Level shift circuit group 3 Logic circuit 4 Gradation voltage generation circuit 11 1st D / A converter 12 2nd D / A converter 13 Switch 14 Switch 15 Precharge circuit 16 Node 17 Buffer 18 output terminal 19 selection circuit 21 first level shift circuit 22 second level shift circuit 23 third level shift circuit 31 latch circuit 33 change detection circuit 34 logic circuit 35 logic circuit 36 change detection circuit 50 to 53 switch 54 first 1 D / A converter 55 Second D / A converter 56 Third D / A converter 57 Fourth D / A converter 58, 59 Switch 60 Liquid crystal display device 61 Data line drive circuit 62 Scan line Drive circuit 63 Display panel 64 Data line 65 Scan line 66 Pixel 67 Control circuit 68 Power supply circuit 69 Common voltage generation circuit 71, 72 Node 100 Substrate 110 First N well 112 P well 114 Gate oxide film 120 Second N well 122 P well 124 Gate oxide film 130 Third N well 134 Gate oxide film

Claims (19)

A D / A conversion circuit for converting a digital signal composed of an upper bit group and a lower bit group into one analog voltage signal corresponding to the digital signal among a plurality of analog voltage signals,
A first analog voltage signal that operates in a first voltage range between a first voltage and a second voltage lower than the first voltage, and that corresponds to the lower bit group among the plurality of analog voltage signals A first D / A converter that outputs
It operates in a second voltage range between a third voltage and a fourth voltage lower than the second and third voltages, and a second voltage corresponding to the lower bit group among the plurality of analog voltage signals A second D / A converter for outputting an analog voltage signal;
Operates in a third voltage range between a voltage greater than or equal to the first voltage and a voltage less than or equal to the fourth voltage, and depending on the upper bit group, the first analog voltage signal or the second voltage A selection circuit that selects any one of the analog voltage signals and outputs the selected analog voltage signal to the first node as the one analog voltage signal ;
The first D / A converter includes a plurality of first MOS transistors,
The second D / A converter includes a plurality of second MOS transistors,
The selection circuit includes a plurality of third MOS transistors,
The gate oxide film thickness of the first and second MOS transistors is smaller than the gate oxide film thickness of the third MOS transistor, or the gate length of the first and second MOS transistors is shorter than the gate length of the third MOS transistor. Conversion circuit. A D / A conversion circuit according to claim 1,
The first D / A converter receives a first voltage signal group corresponding to the first voltage range among the plurality of analog voltage signals, and the lower bit group of the first voltage signal group And outputting the first analog voltage signal according to the selection circuit,
The second D / A converter receives a second voltage signal group corresponding to the second voltage range among the plurality of analog voltage signals, and the lower bit group of the second voltage signal group A D / A conversion circuit that outputs the second analog voltage signal corresponding to the signal to the selection circuit. A D / A converter circuit according to claim 1 or 2 ,
The second voltage and the third voltage are the same D / A conversion circuit. A D / A conversion circuit according to claim 3 ,
The second voltage and the third voltage are a system ground D / A conversion circuit. A D / A conversion circuit according to any one of claims 1 to 4 , wherein
The first D / A converter is formed in a first continuous region on the substrate;
The second D / A converter is formed in a second continuous region different from the first continuous region on the substrate;
The selection circuit is a D / A conversion circuit formed in a third continuous region different from the first and second continuous regions on the substrate. A D / A conversion circuit according to any one of claims 1 to 5 ,
Further, a D / A conversion circuit including a buffer disposed between the first node and the output terminal and operating in the third voltage range . A D / A conversion circuit according to any one of claims 1 to 6 ,
Further, a D / A conversion circuit including a precharge circuit that precharges the first node to a predetermined voltage and operates in the third voltage range . A D / A conversion circuit according to claim 7 ,
The precharge by the precharge circuit is performed when the value of the upper bit group changes. D / A conversion circuit. A D / A converter circuit according to claim 8 ,
Wherein when the value of the higher bit group is changed, after the selection circuit off the electrical connection with the previous SL first and second D / A converter, the precharge D / A conversion circuit to be performed. A D / A converter circuit according to any one of claims 7 to 9 ,
The predetermined voltage is either the second voltage or the third voltage. A D / A conversion circuit. A D / A converter circuit according to any one of claims 7 to 9 ,
The second voltage, the third voltage, and the predetermined voltage are a system ground D / A conversion circuit. A D / A converter circuit according to any one of claims 1 to 11 ,
The digital signal is pixel data displayed on a pixel of a display device,
Each of the plurality of analog voltage signals is a plurality of gradation signals indicating a pixel voltage. D / A conversion circuit. A D / A conversion circuit according to any one of claims 1 to 12 ,
A gradation voltage generation circuit for supplying a plurality of gradation signals to the D / A conversion circuit as the plurality of analog voltage signals;
And a logic circuit that receives the digital signal indicating pixel data and supplies the upper bit group and the lower bit group to the D / A conversion circuit. A D / A conversion circuit according to any one of claims 7 to 11 ,
A gradation voltage generation circuit for supplying a plurality of gradation signals to the D / A conversion circuit as the plurality of analog voltage signals;
A logic circuit that receives the digital signal indicating pixel data and supplies the upper bit group and the lower bit group to the D / A conversion circuit;
A change detection circuit that outputs a control signal to the precharge circuit when a change in the value of the upper bit group is detected;
The precharge circuit precharges the first node to the predetermined voltage in response to the control signal. A D / A conversion circuit according to any one of claims 1 to 6 ,
A gradation voltage generation circuit for supplying a plurality of gradation signals to the D / A conversion circuit as the plurality of analog voltage signals;
A logic circuit that receives the digital signal indicating pixel data and supplies the upper bit group and the lower bit group to the D / A conversion circuit;
A change detection circuit that outputs a control signal to the logic circuit when a change in the value of the upper bit group is detected;
When the control circuit receives the control signal, the logic circuit supplies data whose bit values are all 0 to the first D / A converter as the lower bit group. Display driver. A D / A conversion circuit according to any one of claims 1 to 6 ,
A gradation voltage generation circuit for supplying a plurality of gradation signals to the D / A conversion circuit as the plurality of analog voltage signals;
A logic circuit that receives the digital signal indicating pixel data and supplies the upper bit group and the lower bit group to the D / A conversion circuit;
A change detection circuit that outputs a control signal to the logic circuit when a change in the value of the upper bit group is detected;
When the logic circuit receives the control signal, the logic circuit supplies data whose bit values are all 1 to the second D / A converter as the lower bit group. Display driver. A display driver according to any one of claims 13 to 16 , comprising:
A first level shift circuit;
A second level shift circuit;
The first level shift circuit receives the lower bit group from the logic circuit, converts the lower bit group so as to conform to the first voltage range, and then converts the lower bit group to the first D Output to the / A converter,
The second level shift circuit receives the lower bit group from the logic circuit, converts the lower bit group to fit the second voltage range, and then converts the lower bit group to the second D Display driver that outputs to the / A converter. A display driver according to claim 17 ,
A third level shift circuit;
The third level shift circuit receives the upper bit group from said logic circuit, after converting the upper bit group to conform to the third voltage range, outputting the upper bit group to said selection circuit Yes Display driver. A display driver according to any one of claims 13 to 18 ,
A display panel having a plurality of pixels,
The display driver supplies a gradation signal selected as the one analog voltage signal to any of the plurality of pixels.

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