JP2007003563A - Driver circuit of liquid crystal display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption and prevent degradation of image quality by reducing the area of a driver circuit of a liquid crystal display apparatus. <P>SOLUTION: The driver circuit 5 of the liquid crystal display apparatus includes: positive D/A converters PH and PL; negative D/A converters NH and NL; a positive selector 11; and a negative selector 21. The first positive D/A converter PL operates within a first positive voltage range GND-VDD1, and outputs first positive analog voltage signals V32P-V63P by D/A converting lower bit groups D0-D4 of digital signals. The second positive D/A converter PH operates within a second positive voltage range VDD1-VDD2, and outputs second positive analog voltage signals V0P-V31P by D/A converting lower bit groups D0-D4 of digital signals. The positive selector 11 selects, in accordance with the highest bit D5 of the digital signals, either the first or the second positive analog voltage signal as the positive analog voltage signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driving circuit for a liquid crystal display device. In particular, the present invention relates to a data line driving circuit for driving a liquid crystal display device by a dot inversion driving method.

  In a known liquid crystal display device, the polarity of a voltage (hereinafter referred to as a pixel voltage) applied to a pixel from a data line via a TFT (Thin Film Transistor) is inverted every predetermined period. That is, the pixels are driven in an alternating manner. Here, the polarity indicates the positive or negative of the pixel voltage when the common electrode voltage (com voltage) is used as a reference. Such a driving method is applied to suppress deterioration of the liquid crystal material. Further, a “dot inversion driving method” is known in which the data line and the scanning line are driven so that the polarity of the pixel voltage is inverted for each adjacent pixel in one frame. According to the dot inversion driving method, flicker is reduced and image quality is improved.

  Regarding the driving circuit for driving such a liquid crystal display device, the area is preferably as small as possible. As a conventional technique for reducing the area of the liquid crystal driving circuit, a technique disclosed in Patent Document 1 is known.

A data line driving circuit described in Patent Document 1 amplifies a D / A converter that converts a digital signal into an analog signal and a voltage level of an output signal of the D / A converter to a level for driving a liquid crystal display device. And an amplifier. The amplification factor α by the amplifier is larger than 1. Specifically, in this amplifier, a resistor R1 is provided between the reference voltage terminal and the inverting input terminal, and a resistor Rf is provided between the output terminal and the inverting input terminal. In this case, the relationship between the input voltage Vin and the output voltage Vout is expressed by the following equation:
Vout = Vin (1 + Rf / R1)
As a result of providing an amplifier having an amplification factor α greater than 1, the voltage level of the signal sent from the D / A converter to the amplifier can be set to 1 / α of the pixel voltage. Accordingly, the withstand voltage of elements such as transistors constituting the D / A converter can be reduced, and the area of the D / A converter can be reduced.

JP-A-11-184444

  The inventor of the present application paid attention to the following points. In Patent Document 1 described above, a D / A converter and an amplifier are provided for each data line. However, the amplification factor α (> 1) in each amplifier varies due to manufacturing variations of the resistors R1 and Rf. This leads to deterioration of the accuracy of the pixel voltage supplied to the data line, and causes deterioration of image quality such as vertical unevenness. In particular, in the case of the dot inversion driving method, “unevenness” occurs between adjacent data lines, and an adverse effect due to variation in the amplification factor α appears remarkably.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The drive circuit (5) of the liquid crystal display device according to the present invention converts a digital signal (D0 to D5) composed of the most significant bit (D5) and the lower bit group (D0 to D4) into the digital signal (D0 to D5). The analog voltage signals (V0P to V63P, V0N to V63N) are converted accordingly. More specifically, the drive circuit (5) has a “positive analog voltage signal (V0P to V63P)” having a positive polarity with respect to the reference voltage (GND) and a negative polarity with respect to the reference voltage (GND). “Negative polarity analog voltage signals (V0N to V63N)” are output to the data line (Y) of the liquid crystal display device (1). The drive circuit (5) of the liquid crystal display device according to the present invention includes a first positive electrode D / A converter (PL), a second positive electrode D / A converter (PH), and a positive electrode selector (11). The drive circuit (5) further includes a first negative D / A converter (NH), a second negative D / A converter (NL), and a negative selector (21).

  The first positive electrode D / A converter (PL) operates in a first voltage range (GND to VDD1) defined by a reference voltage (GND) and a first voltage (VDD1) higher than the reference voltage. . The first positive D / A converter (PL) performs D / A conversion on the lower bit group (D0 to D4) of the first digital signal to be input, whereby the first positive analog voltage signal ( V32P to V63P) are generated. The first positive D / A converter (PL) outputs the first positive analog voltage signal (V32P to V63P) to the positive selector (11).

  The second positive electrode D / A converter (PH) has a second voltage range (VDD1) defined by the first voltage (VDD1) and a second voltage (VDD2) higher than the first voltage. ~ VDD2). Then, the second positive D / A converter (PH) performs D / A conversion on the lower bit group (D0 to D4) of the input first digital signal, thereby generating a second positive analog voltage signal ( V0P to V31P) are generated. The second positive D / A converter (PH) outputs the second positive analog voltage signal (V0P to V31P) to the positive selector (11).

  The positive selector (11) operates in a fifth voltage range (GND to VDD2) defined by the reference voltage (GND) and the second voltage (VDD2). The positive selector (11) selects either the first positive analog voltage signal (V32P to V63P) or the second positive analog voltage signal (V0P to V31P) according to the most significant bit (D5) of the first digital signal. Are selected as positive analog voltage signals (V0P to V63P).

  On the other hand, the first negative D / A converter (NH) has a third voltage range (VDD3 to GND) defined by a reference voltage (GND) and a third voltage (VDD3) lower than the reference voltage. Operate. Then, the first negative D / A converter (NH) performs D / A conversion on the lower bit group (D0 to D4) of the second digital signal to be input, so that the first negative analog voltage signal ( V32N to V63N). The first negative D / A converter (NH) outputs the first negative analog voltage signal (V32N to V63N) to the negative selector (21).

  The second negative D / A converter (NL) has a fourth voltage range (VDD4) defined by a third voltage (VDD3) and a fourth voltage (VDD4) lower than the third voltage. ~ VDD3). The second negative D / A converter (NL) performs D / A conversion on the lower bit group (D0 to D4) of the second digital signal to be input, so that the second negative analog voltage signal ( V0N to V31N) are generated. The second negative D / A converter (NL) outputs the second negative analog voltage signal (V0N to V31N) to the negative selector (21).

  The negative selector (21) operates in a sixth voltage range (VDD4 to GND) defined by the reference voltage (GND) and the fourth voltage (VDD4). The negative selector (21) selects one of the first negative analog voltage signal (V32N to V63N) and the second negative analog voltage signal (V0N to V31N) according to the most significant bit (D5) of the second digital signal. Is selected as the negative analog voltage signal (V0N to V63N).

  Thus, the first and second positive D / A converters (PL, PH), the first and second negative D / A converters (NH, NL), the positive selector (11), and the negative selector ( 21) operate in different voltage ranges, and are formed in different regions (71-76) on the substrate (70). Here, the positive selector (11) operating in the fifth voltage range (GND to VDD2) and the negative selector (21) operating in the sixth voltage range (VDD4 to GND) are the medium voltage element and the high voltage element. Can be manufactured. On the other hand, the positive electrode D / A converter (PL, PH) and the negative electrode D / A converter (NL, NH) operating in a narrower voltage range can be manufactured with a low voltage element having a lower withstand voltage than the medium voltage element. Is possible. That is, according to the present invention, the withstand voltage of the elements constituting the positive electrode D / A converter (PL, PH) and the negative electrode D / A converter (NL, NH) may be lower than the conventional one. It becomes possible to design the gate length L and the gate width W small. Therefore, the circuit area of the positive electrode D / A converter (PL, PH) and the negative electrode D / A converter (NL, NH) can be reduced.

  As described above, according to the present invention, the area of the circuit (PH, PL, NH, NL) responsible for D / A conversion can be reduced without using an amplifier having an amplification factor α greater than 1. Is possible. The positive analog voltage signals (V0P to V63P) and the negative analog voltage signals (V0N to V63N) described above may be output to the data line (Y) through the voltage followers (17, 27). Since there is no variation in the amplification factor α due to manufacturing variation of the amplifier, the accuracy of the pixel voltage supplied to the data line (Y) is improved. As described above, according to the present invention, not only the area of the drive circuit (5) of the liquid crystal display device is reduced, but also image quality deterioration such as “unevenness” is prevented. In particular, in the case of the dot inversion driving method, the configuration according to the present invention is effective. Furthermore, according to the present invention, since the operating voltage of the D / A converter (PH, PL, NH, NL) is reduced, the power consumption of the driving circuit (5) of the liquid crystal display device is also reduced.

  According to the present invention, the area of the driving circuit of the liquid crystal display device can be reduced. In addition, the power consumption of the drive circuit can be reduced. Furthermore, it is possible to prevent image quality deterioration in the liquid crystal display device.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The following description is intended to describe embodiments of the present invention and does not mean that the present invention is limited to the following embodiments. For clarity of explanation, the following description is omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention.

1. First embodiment (Overall configuration)
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 1 according to the present invention. The liquid crystal display device 1 includes a display panel 2 on which an image is displayed. The display panel 2 includes a plurality of pixels 3 arranged in a matrix. The plurality of scanning lines X1 to Xm and the plurality of data lines Y1 to Yn are formed so as to intersect each other, and a plurality of pixels 3 are arranged at each of the plurality of intersections. Each pixel 3 includes a TFT (Thin Film Transistor), a liquid crystal, and a common electrode. The gate terminal of the TFT is connected to the scanning line, and the source terminal or drain terminal of the TFT is connected to the data line. One end of the liquid crystal is connected to the source terminal or drain terminal of the TFT, and the other end is connected to a common electrode to which a constant common voltage is applied.

  The plurality of scanning lines X <b> 1 to Xm are connected to the scanning line driving circuit 4. The control circuit 6 outputs a scanning line driving signal group for controlling the scanning line driving circuit 4 to the scanning line driving circuit 4. The scanning line driving circuit 4 sequentially drives the plurality of scanning lines X1 to Xm according to the scanning line driving signal group. The plurality of data lines Y <b> 1 to Yn are connected to the data line driving circuit 5. The control circuit 6 outputs a data line drive signal group for controlling the data line drive circuit 5 and pixel data which is digital data to the data line drive circuit 5. The data line driving circuit 5 drives the plurality of data lines Y1 to Yn according to the data line driving signal group. Specifically, the data line driving circuit 5 outputs a pixel voltage corresponding to the pixel data to each of the plurality of data lines Y1 to Yn. As a result, a pixel voltage corresponding to the pixel data is applied to each of the plurality of pixels 3 connected to the selected single scanning line X. An image is displayed on the display panel 2 by sequentially driving the plurality of scanning lines X1 to Xm.

  In the present embodiment, the liquid crystal display device 1 is driven by the “dot inversion driving method”. That is, the polarities of the pixel voltages applied to the adjacent pixels 3 are opposite. Here, the polarity means positive / negative of the pixel voltage when the common voltage applied to the common electrode is used as a reference. For example, in FIG. 1, the polarity of the pixel voltage applied to the pixel 3a is opposite to the polarity of the pixel voltage applied to the pixel 3b or the pixel 3c. Therefore, the data line driving circuit 5 generates positive and negative pixel voltages, and applies pixel voltages having different polarities to the data lines Y1 and Y2. Further, the data line driving circuit 5 inverts the polarity of the pixel voltage applied to each data line Y every horizontal period. Further, the data line driving circuit 5 inverts the polarity of the pixel voltage applied to each data line Y for each frame. Such a dot inversion driving method reduces flicker and improves image quality.

  FIG. 2 is a block diagram showing the configuration of the data line driving circuit 5 according to the present invention. The data line driving circuit 5 includes a D / A conversion circuit 10, a gradation voltage generation circuit 40, a level shift circuit group 50, and a logic circuit 60. The outline of each circuit will be described below.

  First, the D / A conversion circuit 10 is a circuit that converts a digital signal indicating pixel data into an analog voltage signal (gradation signal) corresponding to the digital signal. The output of the D / A conversion circuit 10 is connected to a plurality of data lines Y1 to Yn. In the present embodiment, the description will be made using 6-bit digital signals “D5, D4, D3, D2, D1”. The most significant bit (MSB: Most Significant Bit) of this digital signal is D5, and the least significant bit (LSB: Least Significant Bit) is D0. The lower bit group means bits D0 to D4 other than the most significant bit.

  The 6-bit digital signals D0 to D5 can express 64 types of gradations. For example, the digital signal “000000” represents the 0th gradation, the digital signal “011111” represents the 31st gradation, the digital signal “100000” represents the 32nd gradation, and the digital signal “111111” represents the 63rd floor. Represents the key. In the case of the dot inversion driving method, one gradation is associated with one positive pixel voltage and one negative pixel voltage. Therefore, in the following description, the pixel voltage is referred to as “grayscale voltage”, the positive grayscale voltage is referred to as “positive grayscale voltage”, and the negative grayscale voltage is referred to as “negative grayscale voltage”. Referred to. The 64 kinds of gradations are associated with 64 kinds of positive gradation voltages V0P to V63P and 64 kinds of negative gradation voltages V0N to V63N.

  An example of the correspondence between each gradation and gradation voltage is shown in FIG. On the positive polarity side, positive gradation voltages V0P to V63P are sequentially associated with the 0th to 63rd gradations. On the negative polarity side, negative gradation voltages V63N to V0N are sequentially associated with the 0th to 63rd gradations. Here, in the positive gradation voltages V0P to V63P, it is assumed that the voltage is higher as it is closer to V0P and closer to the ground (system ground) GND as it is closer to V63P. On the other hand, in the negative gradation voltages V0N to V63N, it is assumed that the voltage is lower as it is closer to V0N and closer to the ground GND as it is closer to V63N. Since the voltage applied to the pixel generates an offset voltage by the feedthrough of the TFT when the TFT is turned off, the common voltage is about −2 to 0 V for the n-type TFT and about 0 to 2 V for the p-type TFT. Supplied.

  As shown in FIG. 3, the voltage range including the positive gradation voltages V63P to V32P is referred to as the first voltage range (GND to VDD1). The first voltage range is defined as a range between a reference voltage (GND) and a first voltage VDD1 (eg, 2.7 V) higher than the reference voltage. The voltage range including the positive gradation voltages V31P to V0P is referred to as a second voltage range (VDD1 to VDD2). The second voltage range is defined as a range between the first voltage VDD1 and a second voltage VDD2 (eg, 5V) higher than the first voltage VDD1. The voltage range including the negative gradation voltages V32N to V63N is referred to as a third voltage range (VDD3 to GND). The third voltage range is defined as a range between the reference voltage and a third voltage VDD3 (eg, -2.8V) lower than the reference voltage. The voltage range including the negative gradation voltages V0N to V31N is referred to as a fourth voltage range (VDD4 to VDD3). The fourth voltage range is defined as a range between the third voltage VDD3 and a fourth voltage VDD4 (eg, −5 V) lower than the third voltage VDD3. The fifth voltage range is defined as a range between the reference voltage and the second voltage VDD2. The sixth voltage range is defined as a range between the reference voltage and the fourth voltage VDD4. The seventh voltage range including all gradation voltages is defined as a range between a voltage equal to or higher than the second voltage and a voltage equal to or lower than the fourth voltage. The second voltage VDD2 and the fourth voltage VDD4 may be generated by a power supply circuit (not described) such as a DC-DC converter. The first voltage VDD1 and the third voltage VDD3 are generated by a gradation voltage generation circuit 40 described later.

  Next, the gradation voltage generation circuit 40 is a circuit that outputs the positive gradation voltages V0P to V63P and the negative gradation voltages V0N to V63N described above to the D / A conversion circuit 10. Specifically, the gradation voltage generation circuit 40 outputs a gradation signal (analog voltage signal) having each gradation voltage to the D / A conversion circuit 10. In this specification, each of the symbols V0P to V63P and V0N to V63N may represent not only each gradation voltage but also a gradation signal having each gradation voltage. That is, the voltages of the positive gradation signals (positive analog voltage signals) V0P to V63P are the gradation voltages V0P to V63P, and the respective voltages of the negative gradation signals (negative polarity analog voltage signals) V0N to V63N are levels. The regulated voltages are V0N to V63N.

  Next, the logic circuit 60 is a circuit that receives from the control circuit 6 digital signals D0 to D5 indicating pixel data, a horizontal synchronization signal STB, a latch signal LAT, and a polarity signal POL. The logic circuit 60 outputs a control signal for controlling image display based on the horizontal synchronization signal STB, the latch signal LAT, the polarity signal POL, and the like. The digital signals D0 to D5 and the control signal are sent to the D / A conversion circuit 10 through the level shift circuit group 50. The level shift circuit group 50 includes a plurality of level shift circuits for converting voltage levels of digital signals and control signals so as to be compatible with the D / A conversion circuit 10.

  Hereinafter, the configuration and operation of the data line driving circuit 5 according to the present invention will be described in more detail.

(Detailed configuration and operation)
FIG. 4 is a circuit block diagram showing a configuration of the D / A conversion circuit 10 according to the first embodiment of the present invention. FIG. 4 shows a configuration for driving two adjacent data lines Y1 and Y2. The output terminal T1 of the D / A conversion circuit 10 is connected to the data line Y1, and the output terminal T2 is connected to the data line Y2. One of the positive gray scale signals V0P to V63P is applied to one data line, and one of the negative gray scale signals V0N to V63N is applied to the other data line.

  As shown in FIG. 4, the D / A conversion circuit 10 according to the present embodiment includes a first positive D / A converter PL, a second positive D / A converter PH, a positive selector 11, a precharge. Switches 14 to 16 and a voltage follower 17 are provided. These circuits handle the positive gradation signals V0P to V63P and determine one positive gradation signal according to a positive-side digital signal (hereinafter referred to as “first digital signal”). The D / A conversion circuit 10 according to the present embodiment includes a first negative D / A converter NH, a second negative D / A converter NL, a negative selector 21, precharge switches 24 to 26, and A voltage follower 27 is provided. These circuits handle negative gradation signals V0N to V63N, and determine one negative gradation signal corresponding to a negative-side digital signal (hereinafter referred to as “second digital signal”). Further, the D / A conversion circuit 10 according to the present embodiment includes a polarity selection circuit 30. The polarity selection circuit 30 outputs the above-described one positive gradation signal to one of the data lines Y1 and Y2, and outputs one negative gradation signal to the other of the data lines Y1 and Y2.

  First, description will be made from the configuration on the positive electrode side.

  The first positive D / A converter PL is configured to operate in the first voltage range GND to VDD1. Therefore, the positive polarity gradation signals V32P to V63P corresponding to the first voltage range GND to VDD1 are supplied to the first positive polarity D / A converter PL (see FIG. 3). The positive polarity gradation signals V32P to V63P are supplied by the positive polarity gradation voltage generation circuit 41 of the gradation voltage generation circuit 40. Then, the first positive D / A converter PL includes one positive gray scale signal (hereinafter referred to as “first positive gray scale signal”) corresponding to the lower bit groups D0 to D4 of the first digital signal among the positive gray scale signals V32P to V63P. 1 positive gradation signal ”). That is, the first positive electrode D / A converter PL generates a first positive gradation signal by performing D / A conversion on the lower bit groups D0 to D4 of the input first digital signal. For example, when the lower bit groups D0 to D4 are “00000”, the gradation signal V32P is selected as the first positive gradation signal. The first positive polarity D / A converter PL outputs the first positive polarity gradation signal to the positive polarity selector 11.

  5A and 5B illustrate the circuit configuration of one D / A converter. For simplicity, the case of a 2-bit digital signal (D0, D1) will be described. The D / A converter shown in FIG. 5A includes inverters a1 and a2, AND circuits a3 to a6, and transistors (switches) a7 to a10. The digital signal is decoded by logic circuits such as inverters a1 and a2 and AND circuits a3 to a6. As a result, one of the four switches a7 to a10 is turned on, and one voltage corresponding to the digital signal is output from the four types of voltages V0 to V3. The D / A converter shown in FIG. 5B includes a plurality of transistors b1 to b16 and inverters b17 and b18. However, the transistors b1, b3, b5, b8, b10, b11, b14, and b16 are enhancement type transistors, and the other transistors are always on depletion type transistors. Either a digital signal (D0, D1) or its inverted signal is input to the gate of each transistor. Thereby, one voltage according to a digital signal is output among the four types of voltages V0 to V3. Even when the number of bits of the digital signal is different, the D / A converter is realized by the same principle.

  The second positive electrode D / A converter PH is configured to operate in the second voltage range VDD1 to VDD2. Therefore, the positive polarity gradation signals V0P to V31P corresponding to the second voltage range VDD1 to VDD2 are supplied to the second positive polarity D / A converter PH (see FIG. 3). The positive polarity gradation signals V0P to V31P are supplied by the positive polarity gradation voltage generation circuit 41 of the gradation voltage generation circuit 40. Then, the second positive D / A converter PH includes one positive gray scale signal (hereinafter referred to as “first positive gray scale signal”) corresponding to the lower bit groups D0 to D4 of the first digital signal among the positive gray scale signals V0P to V31P. 2 positive polarity gradation signal). That is, the second positive polarity D / A converter PH generates a second positive polarity gradation signal by D / A converting the lower bit groups D0 to D4 of the first digital signal inputted. For example, when the lower bit groups D0 to D4 are “11111”, the gradation signal V31P is selected as the second positive gradation signal. The second positive polarity D / A converter PH outputs the second positive polarity gradation signal to the positive polarity selector 11. The circuit configuration of the second positive electrode D / A converter PH is the same as the configuration shown in FIGS. 5A and 5B.

  6A and 6B illustrate the circuit configuration of the positive gradation voltage generation circuit 41. The positive gradation voltage generation circuit 41 includes a resistor string circuit that is excellent in monotonic increase. For example, FIG. 6A shows a resistor string circuit in which a plurality of resistors R1 to R64 are connected in series. Reference voltages Vref2, Vref3, and Vref1 are supplied to the resistor string circuit through the voltage followers 43, 44, and 45, respectively. In addition, a plurality of positive gradation voltages V0 to V63 are generated from the respective connection points. The reference voltage Vref3 is supplied to a connection point between the resistor R31 and the resistor R32, and a capacitor 46 is connected to the connection point and used as the VDD1 power source. In this case, the positive gradation voltages V31P and V32P which are halftones are voltages in the vicinity of the first voltage VDD1. FIG. 6B shows a resistor string circuit in which a plurality of resistors R1 to R63 are connected in series. In this case, the positive gradation voltage V31P, which is a halftone, becomes the first voltage VDD1.

  Next, the positive selector 11 receives the first positive gradation signal from the first positive D / A converter PL, and receives the second positive gradation signal from the second positive D / A converter PH. Therefore, the positive selector 11 is configured to operate in the fifth voltage range GND to VDD2. Then, the positive selector 11 selects either the first positive gradation signal or the second positive gradation signal as one positive gradation signal according to the most significant bit D5 of the first digital signal.

  Specifically, the positive selector 11 has switches 12 and 13, and ON / OFF of the switches 12 and 13 is controlled by a control signal SWCNT1 indicating the state of the most significant bit D5. When the most significant bit D5 is “1”, the positive tone signals V32P to V63P are selected, so the control signal SWCNT1 controls the positive selector 11 so that the switch 12 is turned off and the switch 13 is turned on. In this case, the positive selector 11 selects the first positive gradation signal from the first positive D / A converter PL. On the other hand, when the most significant bit D5 is “0”, the positive tone signals V0P to V31P are selected, so the control signal SWCNT1 controls the positive selector 11 so that the switch 12 is turned on and the switch 13 is turned off. . In this case, the positive selector 11 selects the second positive gradation signal from the second positive D / A converter PL. One selected positive tone signal is output to the node N1.

  The node N1 is connected to the input of the voltage follower 17 whose amplification factor is 1. The output of the voltage follower 17 is connected to the node N2. The node N2 is connected to the polarity selection circuit 30. One positive gradation signal described above is supplied to the polarity selection circuit 30 through the voltage follower 17. The precharge switches 14 to 16 are configured to precharge the node N1 and the node N2 to a predetermined voltage. The precharge operation will be described later. The voltage follower 17 and the precharge switches 14 to 16 are configured to operate in the fifth voltage range GND to VDD2, similarly to the positive selector 11.

  Next, the configuration on the negative electrode side will be described.

  The first negative D / A converter NH is configured to operate in the third voltage range VDD3 to GND. Therefore, the negative polarity gradation signals V32N to V63N corresponding to the third voltage range VDD3 to GND are supplied to the first negative polarity D / A converter NH (see FIG. 3). The negative gradation signals V32N to V63N are supplied by the negative gradation voltage generation circuit 42 of the gradation voltage generation circuit 40. The first negative D / A converter NH includes one negative gradation signal (hereinafter referred to as “first gradation signal”) corresponding to the lower bit groups D0 to D4 of the second digital signal among the negative gradation signals V32N to V63N. 1 negative gradation signal ”). In other words, the first negative D / A converter NH generates a first negative gradation signal by performing D / A conversion on the lower bit groups D0 to D4 of the input second digital signal. For example, when the lower bit groups D0 to D4 are “00000”, the gradation signal V32N is selected as the first negative gradation signal. The first negative D / A converter NH outputs the first negative gradation signal to the negative selector 21.

  The second negative D / A converter NL is configured to operate in the fourth voltage range VDD4 to VDD3. Therefore, the negative polarity gradation signals V0N to V31N corresponding to the fourth voltage range VDD4 to VDD3 are supplied to the second negative polarity D / A converter NL (see FIG. 3). The negative gradation signals V0N to V31N are supplied by the negative gradation voltage generation circuit 42 of the gradation voltage generation circuit 40. Then, the second negative D / A converter NL includes one negative gradation signal (hereinafter referred to as “first negative gradation signal”) corresponding to the lower bit groups D0 to D4 of the second digital signal among the negative gradation signals V0N to V31N. 2 negative gradation signal ”). In other words, the second negative D / A converter NL generates a second negative gradation signal by performing D / A conversion on the lower bit groups D0 to D4 of the input second digital signal. For example, when the lower bit groups D0 to D4 are “11111”, the gradation signal V31N is selected as the second negative gradation signal. The second negative D / A converter NL outputs the second negative gradation signal to the negative selector 21.

  The circuit configurations of the first negative electrode D / A converter NH and the second negative electrode D / A converter NL are the same as those shown in FIGS. 5A and 5B. The circuit configuration of the negative gradation voltage generation circuit 42 is the same as that shown in FIGS. 6A and 6B. A capacitor 46 is connected to a connection point between the resistor R31 and the resistor R32, and is used as a VDD3 power source.

  The negative selector 21 receives a first negative gradation signal from the first negative D / A converter NH and receives a second negative gradation signal from the second negative D / A converter NL. Therefore, the negative selector 21 is configured to operate in the sixth voltage range VDD4 to GND. Then, the negative selector 21 selects one of the first negative gradation signal and the second negative gradation signal as one negative gradation signal according to the most significant bit D5 of the second digital signal.

  Specifically, the negative selector 21 has switches 22 and 23, and ON / OFF of the switches 22 and 23 is controlled by a control signal SWCNT1 indicating the state of the most significant bit D5. When the most significant bit D5 is “1”, the negative gradation signals V32N to V63N are selected, so the control signal SWCNT1 controls the negative selector 21 so that the switch 22 is turned on and the switch 23 is turned off. In this case, the negative selector 21 selects the first negative gradation signal from the first negative D / A converter NH. On the other hand, when the most significant bit D5 is “0”, since the negative gradation signals V0N to V31N are selected, the control signal SWCNT1 controls the negative selector 21 so that the switch 22 is turned off and the switch 23 is turned on. . In this case, the negative selector 21 selects the second negative gradation signal from the second negative D / A converter NH. One selected negative gradation signal is output to the node N3.

  The node N3 is connected to the input of the voltage follower 27 having an amplification factor of 1. The output of the voltage follower 27 is connected to the node N4. The node N4 is connected to the polarity selection circuit 30. One negative gradation signal described above is supplied to the polarity selection circuit 30 through the voltage follower 27. The precharge switches 24 to 26 are configured to precharge the node N3 and the node N4 to a predetermined voltage. The precharge operation will be described later. Similarly to the negative selector 21, the voltage follower 27 and the precharge switches 24 to 26 are configured to operate in the sixth voltage range VDD4 to GND.

  Next, the configuration of the polarity selection circuit 30 will be described.

  The polarity selection circuit 30 receives one positive gradation signal from the positive selector 11 and one negative gradation signal from the negative selector 21. Therefore, the polarity selection circuit 30 is configured to operate in the seventh voltage range VDD4 to VDD2. The polarity selection circuit 30 outputs one positive gradation signal to one of the data lines Y1 and Y2, and outputs one negative gradation signal to the other of the data lines Y1 and Y2.

  Specifically, the polarity selection circuit 30 has switches 31 to 34. The switch 31 is provided between the node N2 and the output terminal T1, and the switch 33 is provided between the node N2 and the output terminal T2. The switch 32 is provided between the node N4 and the output terminal T1, and the switch 34 is provided between the node N4 and the output terminal T2. ON / OFF of these switches 31 to 34 is controlled by a control signal SWCNT2 indicating the state of the polarity signal POL. For example, when the polarity signal POL is “1”, the control signal SWCNT2 controls the polarity selection circuit 30 so that the switches 31 and 34 are turned on and the switches 32 and 33 are turned off. In this case, the polarity selection circuit 30 outputs the positive gradation signal to the data line Y1, and outputs the negative gradation signal to the data line Y2. On the other hand, when the polarity signal POL is “0”, the control signal SWCNT2 controls the polarity selection circuit 30 so that the switches 31 and 34 are turned off and the switches 32 and 33 are turned on. In this case, the polarity selection circuit 30 outputs the positive gradation signal to the data line Y2, and outputs the negative gradation signal to the data line Y1.

  Thus, gradation signals having different polarities are output to the adjacent data lines Y1 and Y2. As a result, the polarities of the pixel voltages applied to the adjacent pixels 3 (3a-3b; 3c-3d) are reversed. Therefore, dot inversion driving is realized. Further, it is possible to invert the positive electrode and the negative electrode by the polarity signal POL (control signal SWCNT2). Here, the value of the polarity signal POL is preferably switched between “0” and “1” for each horizontal period. As a result, the polarity of the gradation voltage applied to the data lines Y1 and Y2 is inverted every horizontal period. As a result, the polarities of the pixel voltages applied to the adjacent pixels 3 (3a-3c; 3b-3d) are reversed. Therefore, dot inversion driving (line inversion driving) is realized.

  As described above, the positive electrode D / A converters PL and PH, the negative electrode D / A converters NH and NL, the positive electrode selector 11, the negative electrode selector 21, and the polarity selection circuit 30 operate in different voltage ranges. Here, the positive selector 11 that operates in the fifth voltage range GND to VDD2 and the negative selector 21 that operates in the sixth voltage range VDD4 to GND are manufactured by “medium voltage elements”, and the seventh voltage range VDD4. The polarity selection circuit 30 operating at ~ VDD2 is manufactured with a "high voltage element".

  On the other hand, the positive electrode D / A converters PL and PH and the negative electrode D / A converters NL and NH that operate in a narrower voltage range can be manufactured with “low voltage elements” having a lower withstand voltage than the medium voltage elements. is there. In other words, according to the present embodiment, the withstand voltages of the elements constituting the positive electrode D / A converters PL and PH and the negative electrode D / A converters NL and NH may be lower than those in the past. As a result, the gate length L and the gate width W of the elements constituting the positive electrode D / A converters PL and PH and the negative electrode D / A converters NL and NH can be designed to be small. Therefore, the circuit area of the positive electrode D / A converter (PL, PH) and the negative electrode D / A converter (NL, NH) can be reduced.

  As described above, according to the present embodiment, it is possible to reduce the area of a circuit responsible for D / A conversion without using an amplifier having an amplification factor α greater than 1. The positive polarity gradation signal and the negative polarity gradation signal described above may be output to the data line Y through the voltage followers 17 and 27. Since there is no variation in the amplification factor α due to manufacturing variation of the amplifier, the accuracy of the pixel voltage supplied to the data line Y is improved. That is, not only the area of the data line driving circuit 5 is reduced, but also image quality deterioration such as “unevenness” is prevented. In particular, in the case of the dot inversion driving method, the configuration according to the present invention is effective. Furthermore, since the operating voltages of the D / A converters PH, PL, NH, and NL are reduced, the power consumption of the data line driving circuit 5 is also reduced.

  Note that the voltage level of the signal from the logic circuit 60 to each circuit having a different operating voltage may be appropriately changed by the level shift circuit group 50 shown in FIG. For example, FIG. 7 shows an example of the configuration of the level shift circuit group 50. The level shift circuit group 50 includes level shift circuits 51 to 57. The level shift circuit 51 changes the voltage levels of the lower bit groups D0 to D4 so as to conform to the operating voltage (VDD1 to VDD2) of the second positive electrode D / A converter PH. The level shift circuit 52 changes the voltage levels of the lower bit groups D0 to D4 so as to conform to the operating voltage (GND to VDD1) of the first positive D / A converter PL. The level shift circuit 53 changes the voltage levels of the lower bit groups D0 to D4 so as to match the operating voltage (VDD3 to GND) of the first negative D / A converter NH. The level shift circuit 54 changes the voltage level of the lower bit groups D0 to D4 so as to match the operating voltage (VDD4 to VDD3) of the second negative D / A converter NL.

  The logic circuit 60 also outputs a control signal SWCNT1 based on the state of the most significant bit D5 and a control signal SWCNT2 based on the state of the polarity signal POL. The level shift circuit 55 changes the voltage levels of the control signals SWCNT1 and SWCNT2 so as to match the operating voltages (GND to VDD2) of the switch groups 12 to 16 on the positive side. The level shift circuit 56 changes the voltage levels of the control signals SWCNT1 and SWCNT2 so as to match the operating voltages (VDD4 to GND) of the switch groups 22 to 26 on the negative electrode side. The level shift circuit 57 changes the voltage level of the control signal SWCNT2 so as to match the operating voltage (VDD4 to VDD2) of the polarity selection circuit 30.

(Precharge operation)
First, the precharge operation for the nodes N2 and N4 will be described. Referring to FIG. 4, according to control signal SWCNT2, nodes N2 and N4 are precharged to ground GND. Specifically, during the precharge operation, the switch 15 is turned off and the precharge switch 16 is turned on by the control signal SWCNT2. Further, during the precharge operation, the switch 25 is turned off and the precharge switch 26 is turned on by the control signal SWCNT2. The precharge switches 16 and 26 are connected to the ground line. When these switches are turned on, the node N2 and the node N4 are precharged to the ground GND.

  The reason for precharging the node N2 and the node N4 is to prevent a voltage other than the operating voltage from being applied to the voltage followers 17 and 27. For example, the voltage follower 17 is connected to the node N2 via the switch 15, and the node N2 is connected to the output terminals T1 and T2 via the switches 31 and 33. As described above, the polarity of the gradation voltage applied to the output terminal T1 (data line Y1) and the output terminal T2 (data line Y2) is inverted according to the control signal SWCNT2. Therefore, it is necessary to prevent the negative gradation voltages V0N to V63N from being applied to the voltage follower 17 that operates at the fifth operating voltages GND to VDD2 in order to prevent a decrease in the element lifetime. Therefore, the switch 15 is turned off, the precharge switch 16 is turned on, and the node N2 is precharged to the ground GND. From this point of view, it is preferable that the precharge operation is executed when the switches 31 to 34 in the polarity selection circuit 30 are switched. In other words, the precharge operation is performed when the polarity signal POL changes, and is preferably controlled by the control signal SWCNT2 based on the state of the polarity signal POL. The same applies to the node N4.

  Next, the precharge operation for the nodes N1 and N3 will be described. Referring to FIG. 4, node N1 is precharged to first voltage VDD1 in response to control signal SWCNT1. Specifically, during the precharge operation, the switches 12 and 13 are turned off and the precharge switch 14 is turned on by the control signal SWNCT1. The precharge switch 14 is connected to the node N1 and the VDD1 power source (see FIGS. 6A and 6B). When the precharge switch 14 is turned on, the node N1 is precharged to the first voltage VDD1. Further, the node N3 is precharged to the third voltage VDD3 according to the control signal SWCNT1. Specifically, during the precharge operation, the switches 22 and 23 are turned off and the precharge switch 24 is turned on by the control signal SWNCT1. The precharge switch 24 is connected to the node N3 and the VDD3 power source (see FIGS. 6A and 6B). When the precharge switch 24 is turned on, the node N3 is precharged to the third voltage VDD3.

  The reason for precharging the node N1 and the node N3 is to prevent a voltage other than the operating voltage from being applied to the D / A converters PH, PL, NH, and NL. For example, the first positive electrode D / A converter PL that operates in the first voltage range GND to VDD1 is connected to the node N1 via the switch 13. Here, the positive gradation voltages V0P to V31P output from the second positive D / A converter PH are also applied to the node N1. Therefore, in order to prevent a decrease in element lifetime, it is necessary to prevent a voltage other than the first voltage range GND to VDD1 from being applied to the first positive electrode D / A converter PL. Therefore, the switches 12 and 13 are turned off, the precharge switch 14 is turned on, and the node N1 is precharged to the first voltage VDD1 which is an intermediate gradation voltage. From this point of view, the precharge operation is preferably executed when the switches 12 and 13 in the positive selector 11 are switched. In other words, the precharge operation is preferably performed before the most significant bit D5 of the first digital signal is changed, and is preferably controlled by the control signal SWCNT1 based on the state of the most significant bit D5. The same applies to the node N3, and the precharge operation for the node N3 is performed before the most significant bit D5 of the second digital signal changes.

  FIG. 8 shows a configuration for detecting the change of the most significant bit D5 of the digital signal and precharging the node N1. In FIG. 8, only the circuit relating to the positive electrode side is shown. The circuit and operation relating to the negative electrode side are the same as those of the positive electrode side, and the description thereof is omitted as appropriate. FIG. 8 shows that a latch circuit and a precharge circuit are separately provided for each of the plurality of data lines Y1 to Y (n−1) serving as positive electrodes.

  As shown in FIG. 8, the logic circuit 60 includes a first latch circuit 61, a second latch circuit 62, and a change detection circuit 63. The first latch circuit 61 and the second latch circuit 62 are circuits for latching the 6-bit digital signals D0 to D5. Here, the first latch circuit 61 performs latching according to a sampling signal SMP output from a shift register register (not shown) synchronized with the clock signal. On the other hand, the second latch circuit 62 simultaneously latches the digital signals D0 to D5 latched by the first latch circuit 61 in response to the latch signal LAT. The second latch circuit 62 holds the digital signals D0 to D5 only for a predetermined period such as one horizontal period.

  The digital signal held in the second latch circuit 62 is the current digital signal. On the other hand, the digital signal held in the first latch circuit 61 is a digital signal in the next step. Therefore, by comparing the digital signals held in the first latch circuit 61 and the second latch circuit 62, it is possible to detect a change in the most significant bit D5. The change detection circuit 63 is provided for detecting the change.

  The change detection circuit 63 is controlled by the control signal C1. For example, when the control signal C1 is “1”, the change detection circuit 63 compares the most significant bit D5 held by the first latch circuit 61 with the most significant bit D5 held by the second latch circuit 62. . When the two most significant bits D5 do not match, that is, when the most significant bit D5 changes, the change detection circuit 63 outputs a control signal SWCNT1 for precharging. The precharge control signal SWCNT1 is a switch control signal for turning off the switches 12 and 13 and turning on the precharge switch 14. The precharge control signal SWCNT1 is supplied to the switches 12 and 13 and the precharge switch 14 through the level shift circuit 55 described above. As a result, the node N1 is precharged to the first voltage VDD1. By this precharge operation, deterioration of the element lifetime is suppressed.

  When the two most significant bits D5 match, that is, when the most significant bit D5 does not change, the change detection circuit 63 does not output the precharge control signal SWCNT1. In this case, the states of the switches 12 and 13 and the precharge switch 14 do not change. That is, when the most significant bit D5 does not change, there is no fear that a voltage higher than the withstand voltage is applied to the positive D / A converters PH and PL, and thus the precharge operation is not performed. As a result, it is possible to reduce useless charging / discharging power due to precharging.

  When the control signal C1 is “0”, the change detection circuit 63 outputs a normal control signal SWCNT1. When the most significant bit D5 is “1”, the change detection circuit 63 outputs the control signal SWCNT that turns off the switch 12, turns on the switch 13, and turns off the switch 14. In this case, the positive gradation voltage (V32P to V63P) selected by the first positive D / A converter PL is output to the node N1. On the other hand, when the most significant bit D5 is “0”, the change detection circuit 63 turns on the switch 12, turns off the switch 13, and outputs a control signal SWCNT that turns off the switch. In this case, the positive gradation voltage (V0P to V31P) selected by the second positive D / A converter PH is output to the node N1.

  As described above, when the latch signal LAT is input, the contents of the second latch circuit 62 are updated to the digital signal of the next step. Therefore, it is preferable that the precharge operation is performed immediately before the second latch circuit 62 is updated. That is, it is preferable that the control signal C1 for controlling the change detection circuit 63 is set to “1” before the latch signal LAT is input. For example, the control signal C1 is set to “1” after the start of a certain horizontal period until the latch signal LAT is input. At the same time as the latch signal LAT is input, the control signal C1 is set to “0”.

(Operation example)
Next, an example of the operation of the data line driving circuit 5 according to the present embodiment will be described using the timing chart shown in FIG. In FIG. 9, the horizontal synchronization signal STB, the latch signal LAT, the polarity signal POL, the contents of the second latch circuit 62, the state of each switch, the voltage of each node, and the gradation voltage applied to the data lines Y1 and Y2 are shown. It is shown.

  It is assumed that a positive digital signal (first digital signal) is stored in the latch circuit 62-1. The contents of the positive digital signals D0 to D5 are sent to the positive D / A converters PH and PL, or used to control the positive switches 12 to 14. The latch circuit 62-2 stores a negative digital signal (second digital signal). The contents of the negative digital signals D0 to D5 are sent to the negative D / A converters NH and NL, or are used to control the negative side switches 22 to 24. Here, the polarity of the gradation voltage supplied to the data lines Y1, Y2 is inverted every horizontal period. Therefore, for example, a digital signal corresponding to the data line Y1 may be input alternately to the latch circuits 62-1 and 62-2.

  First, in the first horizontal period, the polarity signal POL is “1”. At this time, a positive gray scale voltage is applied to the data line Y1, and a negative gray scale voltage is applied to the data line Y2. Therefore, the first digital signal “111111” corresponding to the data line Y1 is stored in the latch circuit 62-1, and the second digital signal “000000” corresponding to the data line Y2 is stored in the latch circuit 62-2. Yes. In accordance with the lower bit group “11111” of the first digital signal, the first positive D / A converter PL selects the positive gradation voltage V63P, and the second positive D / A converter PH selects the positive The gradation voltage V31P is selected. Further, according to the most significant bit “1”, the switch 12 is turned off and the switch 13 is turned on. As a result, the positive gradation voltage V63P is applied to the node N1 and the node N2.

  Further, according to the lower bit group “00000” of the second digital signal, the first negative D / A converter NH selects the negative gradation voltage V32N, and the second negative D / A converter NL The negative gradation voltage V0N is selected. Further, according to the most significant bit “0”, the switch 22 is turned off and the switch 23 is turned on. As a result, the negative gradation voltage V0N is applied to the node N3 and the node N4. When the polarity signal POL is “1”, the switches 31 and 34 of the polarity selection circuit 30 are turned on and the switches 32 and 33 are turned off. As a result, the positive gradation voltage V63P corresponding to the first digital signal “111111” is applied to the data line Y1. Further, the negative gradation voltage V0N corresponding to the second digital signal “000000” is applied to the data line Y2.

  Next, at time t20, the horizontal synchronization signal STB rises and the second horizontal period starts. At time t20, the polarity signal POL is inverted in synchronization with the horizontal synchronization signal STB. When the polarity signal POL is “0”, a negative gradation voltage is applied to the data line Y1, and a positive gradation voltage is applied to the data line Y2. Therefore, in response to the later latch signal LAT, the second digital signal “111111” for the data line Y1 is latched by the latch circuit 62-2. In response to the subsequent latch signal LAT, the first digital signal “000000” for the data line Y2 is stored in the latch circuit 62-1.

  Before the latch signal LAT is input, the above-described precharge operation is first performed. Therefore, at time t20, the control signal C1 is set to “1” in synchronization with the horizontal synchronization signal STB. At this time, the digital signal “111111” for the data line Y1 in the first horizontal period is stored in the second latch circuit 62-1, and the second horizontal period is stored in the first latch circuit 61-1. The digital signal “000000” for the data line Y2 is stored. Therefore, the change detection circuit 63-1 detects the mismatch of the most significant bit D5 and outputs the precharge control signal SWCNT1. As a result, the switches 12 and 13 are turned OFF and the switch 14 is turned ON. As a result, the node N1 is precharged to the first voltage VDD1.

  The second latch circuit 62-2 stores a digital signal “000000” for the data line Y2 in the first horizontal period, and the first latch circuit 61-2 stores data in the second horizontal period. The digital signal “111111” for the line Y1 is stored. Therefore, the change detection circuit 63-2 detects the mismatch of the most significant bit D5 and outputs the precharge control signal SWCNT1. As a result, the switches 22 and 23 are turned OFF and the switch 24 is turned ON. As a result, the node N3 is precharged to the third voltage VDD3.

  Further, precharging of the nodes N2 and N4 is also performed for several clocks after the horizontal synchronization signal STB becomes “1”, that is, for several clocks after the polarity signal POL is inverted. Specifically, the switches 15 and 25 are turned off and the switches 16 and 26 are turned on. As a result, the node N2 and the node N4 are precharged to the ground GND. Further, since the switches 31 and 34 are ON, the data lines Y1 and Y2 are also precharged to the ground GND.

  At time t21, the horizontal synchronization signal STB changes to “0” and the latch signal LAT is input. As a result, the digital signals latched in the first latch circuit 61 are transferred to the second latch circuit 62 all at once and latched. As a result, the first digital signal “000000” for the data line Y2 is stored in the second latch circuit 62-1. The second latch circuit 62-2 stores the second digital signal “111111” for the data line Y1. At time t21, the control signal C1 returns to “0”. As a result, the switches 14 and 24 are turned OFF, and the precharge for the nodes N1 and N3 is completed.

  In accordance with the lower bit group “00000” of the first digital signal, the first positive D / A converter PL selects the positive gradation voltage V32P, and the second positive D / A converter PH The gradation voltage V0P is selected. Further, according to the most significant bit “0”, the switch 12 is turned ON and the switch 13 is turned OFF. As a result, the positive gradation voltage V0P is applied to the node N1. On the other hand, according to the lower bit group “11111” of the second digital signal, the first negative D / A converter NH selects the negative gradation voltage V63N, and the second negative D / A converter NL The negative gradation voltage V31N is selected. Further, according to the most significant bit “1”, the switch 22 is turned ON and the switch 23 is turned OFF. As a result, the negative gradation voltage V63N is applied to the node N3.

  Further, after several clocks, at time t22, in response to the control signal SWCNT2, the switches 15 and 25 are turned on and the switches 16 and 26 are turned off. Thereby, the precharge for the node N2 and the node N4 is completed. At time t22, in response to the control signal SWCNT2, the switches 31 and 34 of the polarity selection circuit 30 are turned off and the switches 32 and 33 are turned on. As a result, the positive gradation voltage V0P corresponding to the first digital signal “000000” is applied to the data line Y2. Further, the negative gradation voltage V63N corresponding to the second digital signal “111111” is applied to the data line Y1.

  Next, at time t30, the horizontal synchronization signal STB rises and the third horizontal period starts. At time t30, the polarity signal POL is inverted in synchronization with the horizontal synchronization signal STB. When the polarity signal POL is “1”, a positive gradation voltage is applied to the data line Y1, and a negative gradation voltage is applied to the data line Y2.

  Before the latch signal LAT is input, the above-described precharge operation is first performed. Therefore, at time t30, the control signal C1 is set to “1” in synchronization with the horizontal synchronization signal STB. At this time, the second latch circuit 62-1 stores the digital signal “000000” for the data line Y2 in the second horizontal period, and the first latch circuit 61-1 stores the digital signal “000000”. The digital signal “000000” for the data line Y1 at is stored. Since the most significant bit D5 matches, the change detection circuit 63-1 does not output the precharge control signal SWCNT1. Therefore, the state where the switch 12 is turned on and the switch 13 is turned off is maintained. Thereby, useless charging / discharging electric power by precharge is reduced.

  The second latch circuit 62-2 stores a digital signal “111111” for the data line Y1 in the second horizontal period, and the first latch circuit 61-2 stores data in the third horizontal period. A digital signal “000000” for the line Y2 is stored. Therefore, the change detection circuit 63-2 detects the mismatch of the most significant bit D5 and outputs the precharge control signal SWCNT1. As a result, the switches 22 and 23 are turned OFF and the switch 24 is turned ON. As a result, the node N3 is precharged to the third voltage VDD3.

  Further, precharging of the nodes N2 and N4 is also performed for several clocks after the horizontal synchronization signal STB becomes “1”, that is, for several clocks after the polarity signal POL is inverted. Specifically, the switches 15 and 25 are turned off and the switches 16 and 26 are turned on. As a result, the node N2 and the node N4 are precharged to the ground GND. Further, since the switches 32 and 33 are ON, the data lines Y1 and Y2 are also precharged to the ground GND.

  At time t31, the horizontal synchronization signal STB changes to “0” and the latch signal LAT is input. As a result, the digital signals latched in the first latch circuit 61 are transferred to the second latch circuit 62 all at once and latched. As a result, the first digital signal “000000” for the data line Y1 is stored in the second latch circuit 62-1. The second latch circuit 62-2 stores the second digital signal “000000” for the data line Y2. At time t31, the control signal C1 returns to “0”. Thereby, the switch 24 is turned OFF and the precharge for the node N3 is completed.

  In accordance with the lower bit group “00000” of the first digital signal, the first positive D / A converter PL selects the positive gradation voltage V32P, and the second positive D / A converter PH The gradation voltage V0P is selected. Further, according to the most significant bit “0”, the switch 12 is turned ON and the switch 13 is turned OFF. As a result, the positive gradation voltage V0P is applied to the node N1. On the other hand, according to the lower bit group “00000” of the second digital signal, the first negative D / A converter NH selects the negative gradation voltage V32N, and the second negative D / A converter NL The negative gradation voltage V0N is selected. Further, according to the most significant bit “0”, the switch 22 is turned OFF and the switch 23 is turned ON. As a result, the negative gradation voltage V0N is applied to the node N3.

  Further, after several clocks, at time t32, the switches 15 and 25 are turned on and the switches 16 and 26 are turned off in response to the control signal SWCNT2. Thereby, the precharge for the node N2 and the node N4 is completed. At time t32, in response to the control signal SWCNT2, the switches 31 and 34 of the polarity selection circuit 30 are turned on and the switches 32 and 33 are turned off. As a result, the positive gradation voltage V0P corresponding to the first digital signal “000000” is applied to the data line Y1. Further, the negative gradation voltage V0N corresponding to the second digital signal “000000” is applied to the data line Y2.

(Element structure)
In the present embodiment, the polarity selection circuit 30 is configured to operate in the seventh voltage range VDD4 to VDD2, and is manufactured by a “high voltage element”. In addition, the positive selector 11 is configured to operate in the fifth voltage range GND to VDD2, and the negative selector 21 is configured to operate in the sixth voltage range VDD4 to GND. Therefore, it is possible to manufacture the positive selector 11 and the negative selector 21 with “medium voltage elements” having a breakdown voltage lower than that of the high voltage elements. Furthermore, regarding the positive electrode D / A converters PH and PL and the negative electrode D / A converters NH and NL, it is possible to manufacture them with “low voltage elements” having a lower withstand voltage than the medium voltage elements. The breakdown voltages of the high voltage element, the medium voltage element, and the low voltage element are, for example, 12V, 6V, and 3V. Features that appear due to such differences in operating voltage and withstand voltage will be described below.

  FIG. 10 is a plan view schematically showing the layout of the data line driving circuit 5. Each circuit has various operating voltages, and circuits having different operating voltages are arranged in different regions on the substrate. For example, the first positive electrode D / A converter PL that operates in the first voltage range GND to VDD 1 is formed in the first continuous region 71 on the substrate 70. The second positive electrode D / A converter PH operating in the second voltage range VDD1 to VDD2 is formed in the second continuous region 72 on the substrate 70. The first negative D / A converter NH that operates in the third voltage range VDD3 to GND is formed in the third continuous region 73 on the substrate 70. The second negative D / A converter NL operating in the fourth voltage range VDD4 to VDD3 is formed in the fourth continuous region 74 on the substrate 70.

  Each continuous region is separated by a deep N-well layer. Further, in the liquid crystal display device 1, a plurality of D / A conversion circuits 10 to be used are provided corresponding to the plurality of data lines Y1 to Yn. Accordingly, a plurality of first positive electrode D / A converters PL are also provided. For example, the plurality of first positive electrode D / A converters PL may be continuously arranged in the first continuous region 71.

  Similarly, the positive selector 11 that operates in the fifth voltage range GND to VDD <b> 2 is formed in the fifth continuous region 75 on the substrate 70. The negative selector 21 that operates in the sixth voltage range VDD4 to GND is formed in the sixth continuous region 76 on the substrate 70. The polarity selection circuit 30 that operates in the seventh voltage range VDD4 to VDD2 is formed in the seventh continuous region 77 on the substrate.

  Each circuit in the logic circuit 60 (see FIG. 2) is formed of a low voltage element and is formed in an eighth continuous region 78 on the substrate 70. The level shift circuit may be provided between the second latch circuit 62 and each D / A converter, or may be provided before the first latch circuit 61. When the level shift circuit is provided before the first latch circuit 61, the logic circuit 60 is formed in the continuous region 78a, and the level shift circuit is formed in the ninth continuous region 79.

  The voltage followers 17 and 27 are formed of medium voltage elements. In the voltage followers 17 and 27, the offset voltage may vary due to manufacturing variations. Therefore, it is preferable to manufacture the voltage followers 17 and 27 on a silicon substrate in which the relative accuracy of the element is higher than that of the glass substrate on which the pixels are formed. On the other hand, the polarity selection circuit 30 including the switches 31 to 34 may be formed not on the silicon substrate but on the glass substrate on which the pixels are formed.

  FIG. 11A schematically shows a cross-sectional structure along the line A-A ′ in FIG. 10. FIG. 11B schematically illustrates a cross-sectional structure taken along line B-B ′ in FIG. 10. A fourth N well 84, a fifth N well 85, a sixth N well 86, and a seventh N well 87 are formed in the P-type substrate 70. These fourth to seventh N wells 84 to 87 correspond to the above-described fourth to seventh continuous regions 74 to 77, respectively.

  A P well is formed in the fourth N well 84. A fourth voltage VDD3 is applied to the fourth N well 84, and a fourth voltage VDD4 is applied to the P well. A P channel MOS transistor Q3p is formed on the fourth N well 84, and an N channel MOS transistor Q3n is formed on the P well. A gate electrode of each MOS transistor is formed on the substrate 70 via a gate oxide film 94. The MOS transistors Q3p and Q3n constitute a second negative D / A converter NL that operates in the fourth voltage range VDD4 to VDD3. That is, the MOS transistors Q3p and Q3n are low voltage elements. The circuits formed in the first to third and eighth continuous regions are also manufactured by MOS transistors Q3p and Q3n.

  A P well is formed in the fifth N well 85. A second voltage VDD2 is applied to the fifth N well 85, and a ground GND is applied to the P well. A P channel MOS transistor Q2p is formed on the fifth N well 85, and an N channel MOS transistor Q2n is formed on the P well. A gate electrode of each MOS transistor is formed on the substrate 70 via a gate oxide film 95. These MOS transistors Q2p and Q2n constitute a positive selector 11 that operates in the fifth voltage range GND to VDD2. That is, the MOS transistors Q2p and Q2n are medium voltage elements.

  A P well is formed in the sixth N well 86. The ground GND is applied to the sixth N well 86, and the fourth voltage VDD4 is applied to the P well. A P channel MOS transistor Q2p is formed on the sixth N well 86, and an N channel MOS transistor Q2n is formed on the P well. A gate electrode of each MOS transistor is formed on the substrate 70 via a gate oxide film 96. These MOS transistors Q2p and Q2n constitute a negative selector 21 that operates in the sixth voltage range VDD4 to GND. That is, the MOS transistors Q2p and Q2n are medium voltage elements.

  A second voltage VDD 2 is applied to the seventh N well 87, and a fourth voltage VDD 4 is applied to the P-type substrate 70. A P-channel MOS transistor Q1p is formed on the seventh N well 87, and an N-channel MOS transistor Q1n is formed on the P-type substrate 70. A gate electrode of each MOS transistor is formed on the substrate 70 via a gate oxide film 97. These MOS transistors Q1p and Q1n constitute a polarity selection circuit 30 that operates in the seventh voltage range VDD4 to VDD2. That is, the MOS transistors Q1p and Q1n are high voltage elements.

  As described above, each circuit formed in the first to fourth and eighth continuous regions is manufactured by the MOS transistors Q3p and Q3n which are low voltage elements. Each circuit formed in the fifth and sixth continuous regions is manufactured by MOS transistors Q2p and Q2n which are medium voltage elements. Each circuit formed in the seventh continuous region is manufactured by MOS transistors Q1p and Q1n which are high voltage elements. Here, the breakdown voltage of the MOS transistors Q3p and Q3n may be smaller than the breakdown voltage of the MOS transistors Q2p and Q2n. The breakdown voltage of the MOS transistors Q2p and Q2n may be smaller than that of the MOS transistors Q3p and Q3n.

  Therefore, the film thickness Tox of the gate oxide film 94 is smaller than the film thickness Tox of the gate oxide films 95 and 96. The film thickness Tox of the gate oxide films 95 and 96 is smaller than the film thickness Tox of the gate oxide film 97. Regarding the minimum gate length L and gate width W, the MOS transistors Q3p and Q3n are smaller than the MOS transistors Q2p and Q2n, and the MOS transistors Q2p and Q2n are smaller than the MOS transistors Q1p and Q1n. Thus, the circuit area decreases as the breakdown voltage decreases, and the circuit area increases as the breakdown voltage increases.

  Since the area of the D / A conversion circuit 10 increases as the number of bits of the digital signal increases, it is preferable that the D / A conversion circuit 10 be a circuit that uses as few high-voltage elements as possible. According to the present invention, the positive electrode D / A converters PH and PL and the negative electrode D / A converters NH and NL are formed of low voltage elements, and the positive electrode selector 11 and the negative electrode selector 21 are formed of medium voltage elements. Therefore, the circuit area of the D / A conversion circuit 10 is reduced, and the circuit area of the data line driving circuit 5 is also reduced. In addition, since the operating voltage of each circuit is suppressed, the power consumption of the data line driving circuit 5 can be reduced.

(effect)
As described above, according to the present embodiment, the area of the data line driving circuit 5 can be reduced. Here, it is not necessary to use the technique described in Patent Document 1 in order to reduce the area. That is, it is possible to reduce the area of the circuit responsible for D / A conversion without using an amplifier having an amplification factor α greater than 1. The positive polarity gradation signal and the negative polarity gradation signal described above may be output to the data line Y through the voltage followers 17 and 27. This eliminates variations in the amplification factor α due to manufacturing variations of the amplifier, and thus improves the accuracy of the pixel voltage supplied to the data line Y. That is, according to the present embodiment, not only the area of the data line driving circuit 5 is reduced, but also image quality deterioration such as “unevenness” is prevented. In particular, in the case of the dot inversion driving method, the configuration according to the present invention is effective. Furthermore, since the operating voltages of the D / A converters PH, PL, NH, and NL are reduced, the power consumption of the data line driving circuit 5 is also reduced.

2. Second Embodiment FIG. 12 is a circuit block diagram showing a configuration of a D / A conversion circuit 10 ′ according to a second embodiment of the present invention. In FIG. 12, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  As shown in FIG. 12, the node N <b> 1 and the node N <b> 3 are directly connected to the input of the polarity selection circuit 30. The output of the polarity selection circuit 30 is connected to the output terminal T1 through the voltage follower 17 and is connected to the output terminal T2 through the voltage follower 27. The polarity selection circuit 30 has switches 31 to 34. The switch 31 is provided between the node N1 and the voltage follower 17. The switch 32 is provided between the node N3 and the voltage follower 17. The switch 33 is provided between the node N1 and the voltage follower 27. The switch 34 is provided between the node N3 and the voltage follower 27.

  In the present embodiment, the D / A converters PH, PL, NH, and NL are formed of low voltage elements, but the other circuits are high voltage elements that operate in the seventh voltage range VDD4 to VDD2. It is formed. For example, the positive selector 11 and the negative selector 21 are formed of medium voltage elements in the first embodiment, but are formed of high voltage elements in the present embodiment. Therefore, the positive selector 11 and the negative selector 21 are formed in the seventh continuous region 77 on the substrate 70.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. As an additional effect, there is an effect that the configuration of the level shift circuit group 50 becomes simpler than the case shown in FIG. This is because the level shift circuits 55 and 56 that perform voltage conversion so as to conform to the fifth and sixth voltage ranges are not necessary. Since the types of level shift circuits used are reduced, the convenience in designing is improved. Moreover, the positive electrode D / A converters PH and PL may be manufactured with a medium voltage element, and may be configured to operate in the fifth voltage range GND to VDD2. Furthermore, the negative electrode D / A converters NH and NL may also be manufactured with medium voltage elements and configured to operate in the sixth voltage range VDD4 to GND. In this case, since only the level shift circuits 55 to 57 are used, the convenience in designing is further improved.

  In the first and second embodiments described above, the substrate on which the integration is performed may be a semiconductor substrate other than silicon, a glass substrate, a plastic substrate, or the like. The transistor is not limited to a MOS transistor, and may be a bipolar transistor, an organic transistor, or the like. Moreover, although the case where the reference voltage is the system ground GND has been illustrated, the reference voltage may be a voltage different from the system ground GND.

1 is a block diagram schematically showing a configuration of a liquid crystal display device according to an embodiment of the present invention. It is a block diagram which shows the structure of the data line drive circuit which concerns on embodiment of this invention. It is a graph which shows the correspondence of a gradation and a gradation voltage. 1 is a circuit block diagram showing a configuration of a D / A conversion circuit according to a first embodiment of the present invention. It is a circuit diagram which shows an example of a structure of a D / A converter. It is a circuit diagram which shows the other example of a structure of a D / A converter. It is a circuit block diagram which shows an example of a structure of a gradation voltage generation circuit. It is a circuit block diagram which shows the other example of a structure of a gradation voltage generation circuit. 1 is a block diagram showing a configuration of a level shift circuit group according to a first embodiment of the present invention. FIG. 3 is a circuit block diagram showing a configuration necessary for a precharge operation according to the first embodiment of the present invention. 3 is a timing chart showing an operation of the data line driving circuit according to the first exemplary embodiment of the present invention. 1 is a plan view schematically showing a layout of a data line driving circuit according to a first embodiment of the present invention. It is sectional drawing which shows typically the structure along line A-A 'in FIG. It is sectional drawing which shows typically the structure along line B-B 'in FIG. It is a circuit block diagram which shows the structure of the D / A converter circuit which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Display panel 3 Pixel 4 Scan line drive circuit 5 Data line drive circuit 6 Control circuit 10 D / A conversion circuit 11 Positive selector 12, 13 Switch 14 Precharge switch 15 Switch 16 Precharge switch 17 Voltage follower 21 Negative electrode Selector 22, 23 switch 24 precharge switch 25 switch 26 precharge switch 27 voltage follower 30 polarity selection circuit 31-34 switch 40 gradation voltage generation circuit 41 positive gradation voltage generation circuit 42 negative gradation voltage generation circuit 43-45 voltage Follower 46 Capacitor 50 Level shift circuit group 51-57 Level shift circuit 60 Logic circuit 61 First latch circuit 62 Second latch circuit 63 Change detection circuit 70 Substrate 71-79 Separation region 84-8 N-well 94 to 97 gate oxide film

Claims (19)

A driving circuit for a liquid crystal display device that outputs a positive analog voltage signal having a positive polarity with respect to a reference voltage and a negative analog voltage signal having a negative polarity to a data line of the liquid crystal display device,
A first positive analog voltage is obtained by operating in a first voltage range defined by the reference voltage and a first voltage higher than the reference voltage, and D / A converting a lower bit group of the first digital signal. A first positive D / A converter that outputs a signal;
It operates in a second voltage range defined by the first voltage and a second voltage higher than the first voltage, and performs D / A conversion on the lower bit group of the first digital signal. A second positive D / A converter that outputs two positive analog voltage signals;
A positive selector that selects one of the first and second positive analog voltage signals as the positive analog voltage signal according to the most significant bit of the first digital signal;
The first negative analog voltage operates in a third voltage range defined by the reference voltage and a third voltage lower than the reference voltage, and D / A converts a lower bit group of the second digital signal. A first negative D / A converter that outputs a signal;
It operates in a fourth voltage range defined by the third voltage and a fourth voltage lower than the third voltage, and performs D / A conversion on the lower bit group of the second digital signal. A second negative D / A converter that outputs two negative analog voltage signals;
A drive circuit for a liquid crystal display device, comprising: a negative selector that selects one of the first and second negative analog voltage signals as the negative analog voltage signal according to the most significant bit of the second digital signal. A drive circuit for a liquid crystal display device according to claim 1,
The first positive electrode D / A converter is formed in a first region on the substrate;
The second positive electrode D / A converter is formed in a second region on the substrate;
The first negative electrode D / A converter is formed in a third region on the substrate,
The second negative electrode D / A converter is formed in a fourth region on the substrate. A driving circuit for a liquid crystal display device. A drive circuit for a liquid crystal display device according to claim 1,
The positive selector operates in a fifth voltage range defined by the reference voltage and the second voltage;
The negative selector operates in a sixth voltage range defined by the reference voltage and the fourth voltage. A driving circuit for a liquid crystal display device. A drive circuit for a liquid crystal display device according to claim 3,
The first positive electrode D / A converter is formed in a first region on the substrate;
The second positive electrode D / A converter is formed in a second region on the substrate;
The first negative electrode D / A converter is formed in a third region on the substrate,
The second negative electrode D / A converter is formed in a fourth region on the substrate,
The positive selector is formed in a fifth region on the substrate;
The negative selector is formed in a sixth region on the substrate. A driving circuit for a liquid crystal display device. It is a drive circuit of the liquid crystal display device according to claim 4,
In each of the first to sixth regions, a MOS transistor is formed,
The driving circuit of the liquid crystal display device, wherein the thickness of the gate oxide film of the MOS transistor in the first to fourth regions is smaller than the thickness of the gate oxide film of the MOS transistor in the fifth and sixth regions. A drive circuit for a liquid crystal display device according to claim 1,
The positive electrode selector and the negative electrode selector operate in a seventh voltage range defined by a voltage equal to or higher than the second voltage and a voltage equal to or lower than the fourth voltage. A driving circuit for a liquid crystal display device. It is a drive circuit of the liquid crystal display device of Claim 6, Comprising:
The first positive electrode D / A converter is formed in a first region on the substrate;
The second positive electrode D / A converter is formed in a second region on the substrate;
The first negative electrode D / A converter is formed in a third region on the substrate,
The second negative electrode D / A converter is formed in a fourth region on the substrate,
The positive selector and the negative selector are formed in a seventh region on the substrate. A driving circuit for a liquid crystal display device. It is a drive circuit of the liquid crystal display device according to claim 7,
A MOS transistor is formed in each of the first to fourth and seventh regions,
The driving circuit of the liquid crystal display device, wherein the thickness of the gate oxide film of the MOS transistor in the first to fourth regions is smaller than the thickness of the gate oxide film of the MOS transistor in the seventh region. A driving circuit for a liquid crystal display device according to claim 1,
Each of the positive analog voltage signal and the negative analog voltage signal is output to the data line through a voltage follower. A drive circuit for a liquid crystal display device according to claim 1,
The positive analog voltage signal is supplied to a first data line of the liquid crystal display device,
The negative analog voltage signal is supplied to a second data line adjacent to the first data line. A driving circuit for a liquid crystal display device. A drive circuit for a liquid crystal display device according to any one of claims 1 to 10,
A polarity selection circuit that operates in a seventh voltage range defined by a voltage equal to or higher than the second voltage and a voltage equal to or lower than the fourth voltage, and that receives the positive analog voltage signal and the negative analog voltage signal; ,
The polarity selection circuit outputs the positive analog voltage signal to one of the first data line and the second data line adjacent to the first data line of the liquid crystal display device, and the first data line and the second data. A driving circuit for a liquid crystal display device that outputs the negative analog voltage signal to the other of the lines. It is a drive circuit of the liquid crystal display device according to claim 11,
The polarity selection circuit outputs the positive analog voltage signal to the first data line in response to a first polarity signal, and outputs the negative analog voltage signal to the second data line,
The polarity selection circuit outputs the positive analog voltage signal to the second data line and outputs the negative analog voltage signal to the first data line in response to a second polarity signal. . A drive circuit for a liquid crystal display device according to claim 12,
The driving circuit of the liquid crystal display device, wherein the first polarity signal and the second polarity signal are switched every horizontal period. A drive circuit for a liquid crystal display device according to any one of claims 11 to 13,
The first positive electrode D / A converter is formed in a first region on the substrate;
The second positive electrode D / A converter is formed in a second region on the substrate;
The first negative electrode D / A converter is formed in a third region on the substrate,
The second negative electrode D / A converter is formed in a fourth region on the substrate,
The polarity selection circuit is formed in a seventh region on the substrate. A driving circuit for a liquid crystal display device. A drive circuit for a liquid crystal display device according to any one of claims 11 to 13,
The first positive electrode D / A converter is formed in a first region on the substrate;
The second positive electrode D / A converter is formed in a second region on the substrate;
The first negative electrode D / A converter is formed in a third region on the substrate,
The second negative electrode D / A converter is formed in a fourth region on the substrate,
The polarity selection circuit is formed in a seventh region on a substrate where pixels are formed. A driving circuit for a liquid crystal display device. A drive circuit for a liquid crystal display device according to claim 14 or 15,
A MOS transistor is formed in each of the first to fourth and seventh regions,
The driving circuit of the liquid crystal display device, wherein the thickness of the gate oxide film of the MOS transistor in the first to fourth regions is smaller than the thickness of the gate oxide film of the MOS transistor in the seventh region. A driving circuit for a liquid crystal display device according to claim 1,
A positive precharge switch connected to the output terminal of the positive selector and precharging the output terminal of the positive selector to a predetermined voltage;
A drive circuit for a liquid crystal display device, further comprising: a negative precharge switch connected to the output terminal of the negative selector and precharging the output terminal of the negative selector to a predetermined voltage. A driving circuit for a liquid crystal display device according to claim 17,
Precharging by the positive polarity precharge switch is performed before the value of the most significant bit of the first digital signal changes,
The precharge by the negative precharge switch is performed before the value of the most significant bit of the second digital signal is changed. A drive circuit for a liquid crystal display device according to claim 17 or 18,
The positive polarity precharge switch precharges the output terminal of the positive polarity selector to the first voltage,
The negative precharge switch precharges the output terminal of the negative selector to the third voltage. A driving circuit for a liquid crystal display device.

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