201128603 六、發明說明： 【發明所屬之技術領域】 本發明之例示性實施例係關於用於驅動平面顯示面板之 電路及方法’且更特定而言，係關於用於將影像資料以電 壓或電机之形式施加至顯示面板之資料驅動器的有效結 構。可將資料驅動器稱為行線驅動器或源驅動器。 本申請案主張分別於2009年9月18日及2〇〇9年1〇月23曰 申请之韓國專利申請案第10-2009-0088640號及第10_2009_ 0101398號的優先權，其全部内容以引用之方式併入本文 中。 【先前技術】 平面顯示面板之資料驅動器將數位視訊資料轉換為類比 視訊資料且將該類比視訊資料傳送至顯示面板。數位轉類 比轉換器（DAC)佔用資料驅動器之整個結構之大的面積， 且已存在用以減小數位轉類比轉換器之面積的不同嘗試。 其中之一為使用時變信號（TVS)之燈型數位轉類比轉換 器，其被視為一替代。 藉由接收表示複數個灰階電壓之時變信號且選擇並輸出 一特定灰階電壓來驅動燈型數位轉類比轉換器。 圖1A為展示使用單一時變信號之習知驅動器之主要部分 的方塊圖。使用單一時變信號之驅動器揭示於題為「Du" Mode Track and Hold Drivers for Active LCD’s」之美國專 利第5,44〇,256號中。 參看圖1 ’使用單一時變信號之驅動器包括單TVs產生 149700.doc 201128603 器n〇、N位元切換器m、N位元脈衝信號產生器i3〇及通 道緩衝器―單Tvs產生器110產生單一時變信號，其依 序地表示在-個線時間之每一週期的所有灰階電壓。雜 元切換器120接收單一時變信號且對該單一時變信號執行 切換以選擇對應於視訊資料之灰階電壓。N位元脈衝信號 產生器130控制N位元切換器120。通道緩衝器14〇經由一源 線輸出N位元切換器12〇之輸出。 N位元切換器12〇、N位元脈衝信號產生器13〇及通道緩 衝器140為驅動器之通道區塊的構成元件中之一些，且其 被提供至構成驅動器之每一通道區塊。單7¥3產生器ιι〇 係由所有通道共用。 圖1B說明使用單一時變信號之驅動器的操作。單產 生器110與一時脈信號同步且產生時變信號16〇,其依序地 表示一個線時間的2n個灰階電壓。時變信號16〇輸入至每 —通道之N位元切換器120 β N位元脈衝信號產生器13〇產 生N位兀脈衝信號17〇。N位元切換器12〇藉由根據”個脈 衝L號中之一脈衝信號開啟/關斷而選擇時變信號^ 6〇之灰 階電壓中的一特定灰階電壓。N位元切換器12〇所選擇之灰 階電壓信號180經由通道緩衝器14〇傳送至顯示面板之源 線。 因為數位轉類比轉換器使用單一時變信號依序地表示一 個線時間之2N個灰階電壓，所以該數位轉類比轉換器缺乏 時間來對面板負載充電。因此，像素之電壓之間存在誤 差。此外’當所有通道之脈衝信號產生器與一時脈信號同 I49700.doc 201128603 :而操料，消耗大量電力。且，因為將切換器及N位元 氏衝t號產生n添加至每—通道，所以通道面積增大。者 顯示裝置具有高的灰階、高清晰度及大的大小時，此等; 題變得較嚴重。 圖2A為展示使用複數個時變信號之習知驅動器之主要部 刀的方塊圖。使用複數個時變信號之驅動器揭示於題為 Γ Digital-to-Analog Converting Circuit and Method f〇r Driving a Flat Display Panel Using Multi-Ramp SignalSj 之韓國專利第727,4 10號中。 提出使用複數個時變信號之驅動器以解決以上提及之問 題。該驅動器包括多TVS產生器210、Μ位元切換器22〇、 (Ν-Μ)位元脈衝信號產生器23〇及通道緩衝器24〇。 多TVS產生器210針對一個線時間之每一週期將所有灰 階電壓之一區域劃分為（1/2M)個灰階電壓區域且產生複數 個（2M個）時變信號。M位元切換器22〇接收該複數個時變信 號且對該複數個時變信號執行切換以選擇對應於視訊資料 之灰階電壓。通道緩衝器240輸出Μ位元切換器220之輸出 至顯示面板之源線。本文中，Ν及Μ為正整數且Ν大於 Μ(Ν>Μ)。 Μ位元切換器220、（Ν-M)位元脈衝信號產生器230及通 道緩衝器240為驅動器之通道區塊的構成元件中之一些， 且其被提供至構成驅動器之每一通道。多TVS產生器21〇 係由所有通道共用。 圖2B說明使用複數個時變信號之驅動器的操作。 149700.doc 201128603 多TVS產纟器210產生複數個時變信號26〇。因為複數個 (2、)時變信號260以區域來表示所有灰階電壓，所以每 一時變k號260依序地表示—個線時間之一週期的"…個 灰階電壓。 該複數個（2、固）時變信號26〇輸入至每一通道之μ位元切 換器220。（Ν-Μ)位元脈衝信號產生器23〇產生2Ν·μ個脈衝 L號270 Μ4立元切換器220藉由根據2ν·μ個脈衝信號27〇中 之脈衝信號中的一者開啟/關斷而選擇時變信號之灰階電 壓中的一特定灰階電壓β Μ位元切換器22〇所選擇之一灰 階電壓信號280經由通道緩衝器24〇傳送至顯示面板之源 線。 田使用複數個時變信號時，顯示面板充電時間增大多達 2 。因此，有可能減小像素電壓之間的誤差。且因為使 用慢至2Μ倍之時脈頻率，所以可減少電力消耗。另外，因 為將（Ν-Μ)位元脈衝彳s號產生器23〇之電路減小至（Ν_Μ)個 位元，所以亦減小通道面積。 然而，每一通道包括由複數個正反器形成之計數器及由 夕個邏輯電路形成之（Ν_Μ)位元脈衝信號產生器23 〇，該數 位轉類比轉換器仍佔用大的面積。此外，當所有通道之 (Ν-Μ)位元脈衝信號產生器與時脈信號同步而操作時，仍 消耗大量電力。 【發明内容】 本發明之一貫施例係針對一種用於驅動一具有顯著減小 之尺寸之顯示面板的設備及方法。 149700.doc 201128603 本發明之另一實施例係針對一種用於驅動一具有低電力 消耗之顯示面板的設備及方法。 本發明之另一實施例係針對一種用於驅動視訊品質得以 容易地改良之一顯示面板的設備及方法。 本發明之其他目標及優點可藉由以下描述來理解，且參 考本發明之實施例變得顯而易見。且，對於熟習本發明所 屬技術者而言明顯的是，本發明之目標及優點可藉由所主 張之構件及其組合來實現。 根據本發明之一實施例，一種用於驅動一顯示面板之設 備包括：一時變信號（TVS)產生器，其經組態以產生一時 變信號群組；一共同脈衝信號產生器，其經組態以產生複 數個脈衝信號；一選擇器，其經組態以接收該時變信號、 «玄複數個脈衝信號及視訊資料且選擇對應於該視訊資料之 一灰階電ϋ及一緩衝！I , |_且態以緩衝並傳送該選擇 之輸出本文中，該選擇器及該緩衝器被提供至複數 個通遏中之每—者’且該時變信號及該複數個脈衝信號共 同輸入至該選擇器。 該TVS產生器可將所有灰階電壓之—範圍劃分為複數個 又P白電£ In 15且產生《時變信號群組，該時變信號群組具 有各自對應於每一灰階電壓範圍的複數個時變信號。該 T V ^產生器可產生具有依序地表示所有灰階電壓之一範圍 之單一時變信號的該時變信號群組。 該共同脈衝信號產生 號之一開/關作用時間比 器可包括經組態以控制每一脈衝信 率的一暫存器。 149700.doc 201128603 根據本發明之另一實施例，一種用於驅動一顯示面板之 設備包括：一時變信號（TVS)產生器，其經組態以產生複 數個時變信號；一共同脈衝信號產生器，其經組態以產生 複數個脈衝信號；一取樣器’其經組態以取樣並輸出視訊 資料，一脈衝選擇器，其經組態以基於該經取樣之視訊資 料中之一下部位元資料來選擇該複數個脈衝信號中之任一 者，及一TVS選擇器，其經組態以基於該經取樣之視訊資 料中之上部位元資料來選擇該複數個時變信號中之任一 者在5亥選定之脈衝信號之一啟用持續時間中切換該選定 之時變信號，且傳送該經切換之時變信號。 根據本發明之又一實施例，一種用於驅動一顯示面板之 二備包括.一 TVS產生器，其經組態以產生單一時變信 號，一共同脈衝信號產纟器H组態以產生複數個脈衝 信號；-取樣g，其經組態以取樣並輸出視訊資料；一脈 衝選擇器，其經組態以基於該經取樣之視訊資料來選擇該 複數個脈衝信號中之任一者；及一切換器，其經組態以‘ 該選定之脈衝信號之—啟用持續時間中切換該時變信號且 傳送該經切換之時變信號。 根據本發明之再一實施例’ 一種數位轉類比轉換方法包 括··基於經取樣之視訊資料中的一下部位元資料來選擇複 數個脈衝信射之任-者；基於該經取樣之視訊f料中的 一上部位元資料來選擇複數個時變信號中之任—者；及在 ㈣定之脈衝信號之-啟用持續時間中切換該選定之時燃 4舌號且傳送該經切換之時變信號。 文 149700.doc 201128603 根據本發明之再一實施例，一種數位轉類比轉換方法包 括：基於經取樣之視訊資料來選擇複數個脈衝信號中之任 一者，及在該選定之脈衝信號之一啟用持續時間中切換單 一時變信號且將該經切換之時變信號傳送至一通道緩衝 器。 【實施方式】 下文將 > 看h附圖式更詳細地描述本發明之例示性實施 例。然而’本發明可以不同形式來體現且不應被解釋為限 於本文中所閣述之實施例。實情為，提供此等實施例以使 得本發明將為詳盡且完整的，且將完整地將本發明之範鳴 傳達給熟習此項技術者。遍及本發明，相同參考數字遍及 本發明之各種圖及實施例指代相同部分。圖式未必按比例 繪製且在一些情況下可誇大比例以便清楚地說明實施例之 特徵。當第-層被稱作「在第二層上」或「在基板上」 時’其不僅指代第-層直接形成於第二層或基板上之狀況 且亦心代-第三層存在於第―層與第二層或基板之間的狀 況。 下文中，在本說明書中描述本發明之實施例，將本發明 之技術應用於液晶f ， 貝下(LCD)以減小液晶顯示器之面積 及電力消耗。然而，可將本發明 一 j肝不知明之技術應用於諸如場發射 顯不益（FED)、電致發光顯示器（助）、電漿顯示面板 (PDP)及其類似者之平面顯示裝置的所有驅動器。 第一實施例 圖3為說明根據本發明第_ 弟貫施例的使用多時變信號 149700.doc 201128603 (TVS)產生器及共同脈衝信號產生器的顯示面板之驅動器 的方塊圖。 參看圖3，該驅動器包括經組態以產生複數個（2m個）時 變信號之多時變信號(TVS)產生器31〇及經組態以產生具有 不同脈衝寬度之複數個（2關個）脈衝信號的共同脈衝信號 產生器330。i，該驅動器包括選擇器32〇及通道緩衝器 340。選擇器320接收該複數個（2m個）時變信號、該複數個 (2N M個）脈衝信號及視訊資料D<(N_1):〇>以選擇對應於該 視訊資料之灰階電壓。通道緩衝器⑽輸出選擇器32〇之輸 出至顯示面板之源線。本文中，為正整數且N大於 M(N>M)。針對一個線時間之每一週期，將所有灰階電壓 之區域劃分為1/2m灰階電壓區域，且對應於每一灰階電壓 範圍而產生該複數個（2M個）時變信號中之每一者。 選擇器320及通道緩衝器34〇為單位通道區塊之構成元件 且其被提供至構成驅動器之每一冑冑。多tvs產生器η。 及共同脈衝信號產生器330係由所有通道共用。換言之， 該複數個時變信號及該複數個脈衝信號共同輸人至；一通 道之選擇器320。 如圖3中所說明’根據本發明之實施例製造的驅動器並 不在每一通道中包括脈衝信號產生器，而是其具有共同脈 ㈣號產生器330由所有通道共用的結構。因& ,有可能 顯著地減小數位轉類比轉換器及驅動器之晶片面積。 圖4為說明應用圖3之驅動器之軍位通道區塊的詳細方塊 149700.doc •10· 201128603 參看圖4，驅動器包括取樣器45〇、多TVS產生器410、 共同脈衝信號產生器430、選擇器420及通道緩衝器440。 取樣器45〇對Ν位元視訊資料〇<(>1-1):〇>執行取樣。多 TVS產生器4 1 0產生複數個（2*^個）時變信號。共同脈衝信號 產生益430產生具有不同脈衝寬度之複數個（2n-m個）脈衝信 號。選擇器420接收該複數個（2m個）時變信號、該複數個 (2Ν·Μ個）時脈信號及經取樣之視訊資料，選擇該複數個時 變信號中之任一者，且輸出選定之時變信號。通道缓衝器 440輸出選擇器420之輪出至顯示面板之源線。 取樣器450、選擇器420及通道緩衝器44〇為單位通道區 塊之構成元件且其被提供至構成驅動器之每一通道。多 TVS產生器410及共同脈衝信號產生器43〇係由所有通道共 用。 ’、 選擇器420包括脈衝選擇單元422、位準移位單元424及 tvs選擇單元426。脈衝選擇單元422基於經取樣之視訊資 料之下部（N-M)個位元來選擇2ν·μ個脈衝信號中之一者。 位準移位早7C 424將經取樣之視訊f料的上部河個位元及 脈衝選擇單元422之-輸出脈衝信號位準移位。TVS選擇 單元426基於位準移位單元似之輸出來選擇广個時變信號 中之任I。本文中’ N&M為正整數且N大於M(N>M)。 口。取樣盗45G包括移位暫存器單元452及取樣/保持鎖存器 單儿454 °因為移位暫存器單元452及取樣/保持鎖存器單 7L 454之電路組態為眾所周知的，所以為了簡明起見將省 略其泮細描述。 149700.doc 201128603 圖5為說明選擇器42〇之詳細方塊圖。在此實施例中，驅 動器使用兩個時變信號’且該驅動器為6位元數位轉類比 轉換器。亦即，假設整數!^為6，且整數乂為丄。 脈衝選擇單元422可形成為-5位元解碼器，其接收經取 樣之視訊資料〇<5:0>中之下部5位元資料D<4:〇>，選擇32 個脈衝㈣<31:0>中之一者，且輸出選定之脈衝信號。 TVS選擇單元426包括1位元解碼元件426A及切換器元件 426B。1位兀解碼元件426八基於自位準移位單元々μ獲得 之上部1位元資料D<5>選擇兩個時變信號Tvs<〇>與 TVS<1>之間的一者。切換器元件426B僅在自位準移位單 元424獲得之脈衝信號的啟用（其變為邏輯高位準）持續時間 中執行切換且將1位元解碼元件426A之輸出傳送至通道緩 衝器440。 歸根結底，因為將全部灰階電壓相等地劃分為兩個灰階 電壓區域且選擇分別表示兩個灰階電壓區域之兩個時變信 號丁\^<0>與7^8<1>之間的一者，所以選擇—較佳灰階電 壓區域且基於脈衝信號之脈衝寬度來選擇一目標灰階電 壓。 如上文所描述，根據本發明之一實施例的數位轉類比轉 換方法包括：基於經取樣之視訊資料的一下部位元來選擇 複數個脈衝信號中之任一者；基於經取樣之視訊資料的— 上部位7L來選擇複數個時變信號中之任一者；及藉由在選 定之脈衝信號之啟用持續時間中對選定之時變信號執行切 換而將選定之時變信號傳送至通道緩衝器。本文中，針對 149700.doc 12 201128603 一個線時間之每— "2M灰階電屬區域，且，將所有灰階電塵相等地劃分為 (2、)時納卢 'W皆電壓範圍而產生複數個 -週期内之不同啟用捭碎± 。就為具有-個線時間之 個）脈衝錢 持續㈣（其為脈㈣請多個『 圖6為展示根據本發明之一實 PULSE <οΝ-Μ η η 、也例的共同脈衝信號 • )·>之開/關作用時間比率的時序圖。 —個線時間之一週期BACKGROUND OF THE INVENTION 1. Field of the Invention An exemplary embodiment of the present invention relates to a circuit and method for driving a flat display panel and, more particularly, to voltage or electricity for image data. The form of the machine is applied to the effective structure of the data drive of the display panel. A data drive can be referred to as a row or drive. Priority is claimed on Korean Patent Application No. 10-2009-0088640 and No. 10_2009_0101398, filed on Sep. 18, 2009, and the entire disclosure of the entire disclosure of The manner is incorporated herein. [Prior Art] The data driver of the flat display panel converts the digital video data into analog video data and transmits the analog video data to the display panel. The digital to analog converter (DAC) occupies a large area of the overall structure of the data driver, and there have been different attempts to reduce the area of the digital to analog converter. One of them is a lamp-type digital-to-analog converter using time-varying signals (TVS), which is considered as an alternative. The lamp type digital to analog converter is driven by receiving a time varying signal representing a plurality of gray scale voltages and selecting and outputting a specific gray scale voltage. Figure 1A is a block diagram showing the main portions of a conventional driver using a single time varying signal. A driver using a single time-varying signal is disclosed in U.S. Patent No. 5,44,256, entitled "Du" Mode Track and Hold Drivers for Active LCD's. Referring to FIG. 1 'The driver using a single time-varying signal includes a single TVs generation 149700.doc 201128603 〇n〇, N-bit switch m, N-bit pulse signal generator i3〇 and channel buffer-single Tvs generator 110 generation A single time varying signal that sequentially represents all gray scale voltages for each of the - line times. The fuse switcher 120 receives a single time varying signal and performs switching on the single time varying signal to select a gray scale voltage corresponding to the video material. The N-bit pulse signal generator 130 controls the N-bit switch 120. The channel buffer 14 outputs the output of the N-bit switch 12A via a source line. The N-bit switcher 12A, the N-bit pulse signal generator 13A, and the channel buffer 140 are some of the constituent elements of the channel block of the driver, and are supplied to each of the channel blocks constituting the driver. The single 7¥3 generator ιι〇 is shared by all channels. Figure 1B illustrates the operation of a driver using a single time varying signal. The single generator 110 is synchronized with a clock signal and produces a time varying signal 16 〇 which sequentially represents 2n gray scale voltages for one line time. The time-varying signal 16〇 is input to the N-bit switch 120 of each channel. The β-N-bit pulse signal generator 13 generates an N-bit chirp signal 17〇. The N-bit switcher 12 selects a specific gray-scale voltage of the gray-scale voltage of the time-varying signal ^6〇 by turning on/off according to one of the pulse signals of the one pulse L. The N-bit switcher 12 The selected gray scale voltage signal 180 is transmitted to the source line of the display panel via the channel buffer 14. The digital to analog converter sequentially uses a single time varying signal to sequentially represent 2N gray scale voltages of one line time, so The digital to analog converter lacks time to charge the panel load. Therefore, there is an error between the voltages of the pixels. In addition, when the pulse signal generator of all channels is the same as the one clock signal, I49700.doc 201128603: The material is consumed, which consumes a lot of power. Moreover, since the switch and the N-bit s-t is generated to add n to each channel, the channel area is increased. When the display device has high gray scale, high definition, and large size, etc.; Figure 2A is a block diagram showing the main knives of a conventional driver using a plurality of time-varying signals. A driver using a plurality of time-varying signals is disclosed in Γ Digital-to-Analog Conver Ting Circuit and Method f〇r Driving a Flat Display Panel Using Multi-Ramp SignalSj, Korean Patent No. 727, 410. A driver using a plurality of time-varying signals is proposed to solve the above mentioned problem. The driver includes multiple TVS. The generator 210, the Μ bit switcher 22, the (Ν-Μ) bit pulse signal generator 23〇, and the channel buffer 24. The multi-TVS generator 210 applies all gray scale voltages for each cycle of one line time. One region is divided into (1/2M) gray scale voltage regions and generates a plurality of (2M) time-varying signals. The M-bit switch 22 receives the plurality of time-varying signals and performs the plurality of time-varying signals. Switching to select a gray scale voltage corresponding to the video data. The channel buffer 240 outputs the output of the bit switch 220 to the source line of the display panel. Here, Ν and Μ are positive integers and Ν is greater than Μ (Ν > Μ) The Μ bit switch 220, the (Ν-M) bit pulse signal generator 230, and the channel buffer 240 are some of the constituent elements of the channel block of the driver, and are supplied to each of the channels constituting the driver. Multiple TVS generator 21〇 Figure 2B illustrates the operation of a driver using a plurality of time-varying signals. 149700.doc 201128603 The multi-TVS generator 210 generates a plurality of time-varying signals 26 〇 because a plurality of (2) time-varying signals 260 The area represents all the gray scale voltages, so each time change k number 260 sequentially represents the "..." gray scale voltage of one cycle of the line time. The plurality of (2, solid) time varying signals 26〇 are input to The μ bit switch 220 of each channel. The (Ν-Μ) bit pulse signal generator 23 generates 2 Ν·μ pulses L 270 Μ 4 erect switch 220 is turned on/off by one of the pulse signals according to 2 ν·μ pulse signals 27 〇 A particular gray scale voltage β of the gray scale voltage of the time varying signal is selected to be selected. One of the selected gray scale voltage signals 280 is transmitted to the source line of the display panel via the channel buffer 24 . When the field uses a plurality of time-varying signals, the display panel charging time is increased by up to two. Therefore, it is possible to reduce the error between the pixel voltages. And because the clock frequency is as slow as 2 times, the power consumption can be reduced. In addition, since the circuit of the (Ν-Μ) bit pulse 彳s generator 23 is reduced to (Ν_Μ) bits, the channel area is also reduced. However, each channel includes a counter formed by a plurality of flip-flops and a (Ν_Μ) bit pulse signal generator 23 formed by a logic circuit, which still occupies a large area. In addition, when all (通道-Μ) bit pulse signal generators operate in synchronization with the clock signal, a large amount of power is still consumed. SUMMARY OF THE INVENTION A consistent embodiment of the present invention is directed to an apparatus and method for driving a display panel having a significantly reduced size. Another embodiment of the present invention is directed to an apparatus and method for driving a display panel having low power consumption. Another embodiment of the present invention is directed to an apparatus and method for easily improving a display panel for driving video quality. Other objects and advantages of the present invention will be understood from the following description, and embodiments thereof. It is apparent to those skilled in the art that the objects and advantages of the present invention can be realized by the components of the invention and combinations thereof. According to an embodiment of the invention, an apparatus for driving a display panel includes: a time varying signal (TVS) generator configured to generate a time varying signal group; a common pulse signal generator, grouped State to generate a plurality of pulse signals; a selector configured to receive the time-varying signal, «Xiao complex number of pulse signals and video data and select one of the video data corresponding to gray scale power and a buffer! I, |_ and the state buffers and transmits the output of the selection. Here, the selector and the buffer are provided to each of the plurality of buffers and the time-varying signal and the plurality of pulse signals are input together To the selector. The TVS generator can divide the range of all gray scale voltages into a plurality of P white batteries £ In 15 and generate a group of time-varying signals having respective voltage ranges corresponding to each gray scale. Multiple time-varying signals. The TV^ generator can generate the set of time varying signals having a single time varying signal that sequentially represents one of a range of all gray scale voltages. The on/off action time ratio of the common pulse signal generation number can include a register configured to control the rate of each pulse. 149700.doc 201128603 In accordance with another embodiment of the present invention, an apparatus for driving a display panel includes a time varying signal (TVS) generator configured to generate a plurality of time varying signals; a common pulse signal generation And configured to generate a plurality of pulse signals; a sampler configured to sample and output video data, a pulse selector configured to be based on a lower portion of the sampled video material Data for selecting any one of the plurality of pulse signals, and a TVS selector configured to select any one of the plurality of time varying signals based on the upper portion metadata of the sampled video data The selected time-varying signal is switched during one of the durations of the pulse signal selected by the 5H, and the switched time-varying signal is transmitted. In accordance with yet another embodiment of the present invention, a second device for driving a display panel includes a TVS generator configured to generate a single time varying signal, a common pulse signal generator H configured to generate a complex number a pulse signal; - a sample g configured to sample and output video data; a pulse selector configured to select any one of the plurality of pulse signals based on the sampled video data; and A switch configured to switch the time varying signal during the enable duration of the selected pulse signal and to transmit the switched time varying signal. According to still another embodiment of the present invention, a digital to analog conversion method includes: selecting a plurality of pulsed signals based on the next part of the metadata in the sampled video data; based on the sampled video material The upper part of the metadata is used to select any one of the plurality of time-varying signals; and the selected four-timed number is switched during the (four)-determined pulse signal-enabled duration and the switched time-varying signal is transmitted . According to still another embodiment of the present invention, a digital to analog conversion method includes: selecting any one of a plurality of pulse signals based on the sampled video data, and enabling one of the selected pulse signals A single time varying signal is switched over the duration and the switched time varying signal is transmitted to a channel buffer. [Embodiment] Hereinafter, an exemplary embodiment of the present invention will be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and the invention will be fully conveyed. Throughout the invention, the same reference numerals refer to the same parts throughout the various figures and embodiments of the invention. The drawings are not necessarily to scale, and in some cases may be exaggerated in order to clearly illustrate the features of the embodiments. When the first layer is referred to as "on the second layer" or "on the substrate", it not only refers to the condition in which the first layer is directly formed on the second layer or the substrate but also the core layer - the third layer exists in The condition between the first layer and the second layer or substrate. Hereinafter, embodiments of the present invention are described in the present specification, and the technique of the present invention is applied to liquid crystal f, under the LCD to reduce the area and power consumption of the liquid crystal display. However, the present invention can be applied to all drivers of a flat display device such as a field emission display (FED), an electroluminescence display (Assist), a plasma display panel (PDP), and the like. . [First Embodiment] Fig. 3 is a block diagram showing a driver of a display panel using a multi-time-varying signal 149700.doc 201128603 (TVS) generator and a common pulse signal generator according to the first embodiment of the present invention. Referring to Figure 3, the driver includes a plurality of time varying signal (TVS) generators 31 configured to generate a plurality (2m) of time varying signals and configured to generate a plurality of different pulse widths (2 off) A common pulse signal generator 330 of the pulse signal. i, the driver includes a selector 32 and a channel buffer 340. The selector 320 receives the plurality of (2m) time-varying signals, the plurality of (2N M) pulse signals, and the video data D<(N_1): 〇> to select a grayscale voltage corresponding to the video material. The channel buffer (10) outputs the output of the selector 32 to the source line of the display panel. In this paper, it is a positive integer and N is greater than M(N>M). For each cycle of a line time, all regions of the gray scale voltage are divided into 1/2 m gray scale voltage regions, and each of the plurality of (2M) time varying signals is generated corresponding to each gray scale voltage range. One. The selector 320 and the channel buffer 34 are constituent elements of the unit channel block and are supplied to each of the switches constituting the driver. Multiple tvs generator η. And the common pulse signal generator 330 is shared by all channels. In other words, the plurality of time-varying signals and the plurality of pulse signals are jointly input; a channel selector 320. The driver manufactured according to the embodiment of the present invention as illustrated in Fig. 3 does not include a pulse signal generator in each channel, but has a structure in which the common pulse (four) generator 330 is shared by all channels. Due to & , it is possible to significantly reduce the wafer area of the digital to analog converter and the driver. 4 is a detailed block diagram 149700.doc •10·201128603 for applying the driver channel block of the driver of FIG. 3. Referring to FIG. 4, the driver includes a sampler 45〇, a multi-TVS generator 410, a common pulse signal generator 430, and a selection. 420 and channel buffer 440. The sampler 45 performs sampling on the bit video data 〇 <(>1-1): 〇>. The multi-TVS generator 4 1 0 generates a plurality of (2*^) time-varying signals. The common pulse signal yield 430 produces a plurality of (2n-m) pulse signals having different pulse widths. The selector 420 receives the plurality of (2m) time-varying signals, the plurality of (2 Ν) clock signals, and the sampled video data, and selects any one of the plurality of time-varying signals, and outputs the selected Time-varying signal. Channel buffer 440 outputs the output of selector 420 to the source line of the display panel. The sampler 450, the selector 420, and the channel buffer 44 are constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. The multiple TVS generator 410 and the common pulse signal generator 43 are shared by all channels. The selector 420 includes a pulse selecting unit 422, a level shifting unit 424, and a tvs selecting unit 426. The pulse selection unit 422 selects one of the 2ν·μ pulse signals based on the lower (N-M) bits of the sampled video material. The level shift early 7C 424 shifts the upper river bit of the sampled video material and the output pulse signal level of the pulse selecting unit 422. The TVS selection unit 426 selects any of the wide time varying signals based on the output of the level shifting unit. Here, 'N&M is a positive integer and N is greater than M(N>M). mouth. The sample stealer 45G includes a shift register unit 452 and a sample/hold latch unit 454 ° because the circuit configuration of the shift register unit 452 and the sample/hold latch unit 7L 454 is well known, so A detailed description will be omitted for the sake of brevity. 149700.doc 201128603 FIG. 5 is a detailed block diagram illustrating the selector 42. In this embodiment, the driver uses two time varying signals ' and the driver is a 6 bit digital to analog converter. That is, assume that the integer !^ is 6, and the integer 乂 is 丄. The pulse selecting unit 422 can be formed as a -5-bit decoder that receives the sampled video data 〇<5:0> lower 5-bit data D<4:〇>, selects 32 pulses (4) <31 One of :0>, and outputs the selected pulse signal. The TVS selection unit 426 includes a 1-bit decoding element 426A and a switcher element 426B. The 1-bit 兀 decoding element 426 八 selects one of the two time-varying signals Tvs < 〇 > and TVS < 1 > based on the upper 1-bit data D < 5 > obtained from the level shifting unit 々 μ. Switcher element 426B performs switching only in the enable of the pulse signal obtained from level shifting unit 424 (which becomes a logic high level) and transmits the output of 1-bit decoding element 426A to channel buffer 440. In the final analysis, the entire gray scale voltage is equally divided into two gray scale voltage regions and two time-varying signals representing the two gray scale voltage regions are selected between the two time-varying signals, and between 8^8<1> One, so select - the preferred gray scale voltage region and select a target gray scale voltage based on the pulse width of the pulse signal. As described above, the digital to analog conversion method according to an embodiment of the present invention includes: selecting any one of a plurality of pulse signals based on a lower portion of the sampled video data; based on the sampled video data - The upper portion 7L selects any one of a plurality of time varying signals; and transmits the selected time varying signal to the channel buffer by performing switching on the selected time varying signal during the enabled duration of the selected pulse signal. In this paper, for 149700.doc 12 201128603 one line time - " 2M gray-scale electric area, and all gray-scale electric dust is equally divided into (2) time Nalu 'W all voltage range Multiples - different in the period enable mashing ±. In the case of having one line time, the pulse money is continued (four) (which is a pulse (four), please multiple" FIG. 6 is a diagram showing a common PULSE <οΝ-Μ η η according to the present invention, and also a common pulse signal. · > Timing diagram of the on/off action time ratio. One cycle time
Tr?N-M, m线刀為複數個持續時間T1至 ”且母一持續時間為對應灰階電塵到達之時 展不於圖6中之眚点丨a > ^ 、…： 每一脈衝信號為自初始時刻至 準）。 ㈣而啟用的信號（其變為邏輯高位 使用一時變信號之數位轉類比轉換器在一個 始持續時㈣中比在_個線時間之其他持續時間中需要Z 長充電時間’因為在初始持續時間T1中需要大寬度之電 壓。且’在初始時間T1之後，需要用於使通道緩衝器摔作 顯不面板之充足的充電時間。當充電時間不夠長時，發生 偏移且因此視訊品質可惡化。為了防止視訊品質惡化，根 據本發明之-實施例製造之驅動器的脈衝信號產生写可針 對每一持續時間丁丨至丁口心、而獨立設置時間。 本文中，根據時變信號之時間的電壓變化速率與持續時 間T1至Τ(2ΝΜ)連鎖且基於持續時間71至了(2&、改變。經 由此方法，可解決視訊品質之問題。 圖7為說明共同脈衝信號產生器43〇之詳細方塊圖。 149700.doc 13 201128603 參看圖7 ’共同脈衝信號產生器43〇包括計數器43 1、暫 存器432、加法器433及比較與正反器單元434。 計數器43 1輸出與時脈CLOCK同步而增大之計數信號 CNT—OUT ’且在一個線時間之每一週期藉由重設信號 RESET重設。暫存器儲存具有所有持續時間之時間資 机的k號T1至T(2N M)。加法器43 3接收來自暫存器432之信 號T1至T(2N M)且輸出判定脈衝信號之開啟持續時間（其為 高位準持續時間）之值。包括於比較與正反器 單元434中之比較器在值中之任一者與計數信 號CNT—OUT相同時產生一旗標信號，且該旗標信號被傳 送至正反器F/F。正反器jr/F在計數信號CNT—〇υτ變為 〇」時啟用一脈衝k號，且當產生旗標信號時，其停用 该脈衝信號》因此，產生脈衝信$puLSE， 且控制脈衝信號PULSE <(2N-M_1):〇>之開/關作用時間比 率。 第二實施例 上文所描述之第一實施例描述使用複數個時變信號之狀 況。下文中，將描述使用單一時變信號之第二實施例。正 如在第-實施例中，待在下文中描述H施例使用_ 共同脈衝信號產生器。該共同脈衝信號產生器包括用於控 制脈衝信號之開/關作用時間比率的一暫存器。 圖8為說明根據本發明之第二實施例的使用單T v s產生 器及共同脈衝信號產生器之驅動器的方塊圖。 參看圖8,該驅動器包括單Tvs產生器81〇、共同脈衝信 I49700.doc 201128603 號產生器830、選擇器820及通道缓衝器840。單TVS產生 器810產生單一時變信號。共同脈衝信號產生器830產生具 有不同脈衝寬度之複數個^^^固）脈衝信號。選擇器820接收 該單一時變信號、該複數個脈衝信號及視訊資料d<(N-1):〇> ’且選擇對應於該視訊資料之灰階電壓。通道缓衝器 840輸出選擇器820之輸出至顯示面板之源線。本文中，n 為正整數。對應於一個線時間之週期之所有灰階電壓而產 生該單一時變信號。 選擇器820及通道緩衝器840為單位通道區塊之内部構成 元件且其被提供至構成驅動器之每一通道。單產生器 810及共同脈衝信號產生器83〇係由每一通道共用。 圖9為說明應用圖8之驅動器之單位通道區塊的詳細方塊 圖。 參看圖9，該驅動器包括取樣器95〇、單Tvs產生器 910、共同脈衝信號產生器93〇、選擇器92〇及通道緩衝器 940。取樣器95_N位元視訊資料d<(n_i):〇>執行取樣。 單TVS產生器910產生單—時變信號。共同脈衝信號產生 器930產生具有不同脈衝寬度之複數個(2n個)脈衝信號。選 擇器920接收該單-時變信號、該複數個脈衝信號及經取 樣之視訊資料，且選擇並輸出由該時變信號表示之灰階電 麼。通道緩衝器940輸出選擇器92〇之輸出至顯示面板之源 線。 取樣器950、選擇器950及通谨堪你。 次逋道緩衝态94〇為單位通道區 塊之内部構成元件且並姑括也s '、破美供至構成驅動器之每一通道。 149700.doc 201128603 單TVS產生器910及共同脈衝信號產生器93〇係由每一通道 共用。 選擇器920包括脈衝選擇單元922、位準移位單元”斗及 tvs選擇單元926。脈衝選擇單元922基於經取樣之視訊資 料來選擇複數個（2n個）脈衝信號中之一者。位準移位單元 924將脈衝選擇單元922之輸出信號（其為選定之脈衝信號） 位準移位。tvs選擇單元926基於位準移位單元924之輸出 自單一時變信號選擇一目標灰階電壓。 取樣器950包括移位暫存器單元及取樣/保持鎖存器 單元954。 圖1〇為說明展示於圖9中之選擇器92〇的詳細方塊圖。在 此實施例中，驅動器為6位元數位轉類比轉換器。亦即， 假設整數N為6。 參看圖1〇，脈衝選擇單元922接收經取樣之6位元視訊資 料D<5:0>且選擇並輸出26個脈衝信號<63:()>中之—者。因 此，脈衝選擇單元922可形成為一 6位元解碼器。 二S選擇單元926可形成為一切換器，其僅在自位準移 4單兀924獲^之選定之脈衝信號的啟用（其變為邏輯高位 準）持續時間中對時變信號執行切換且將該時變信號傳送 k道緩衝器940。換言之，該切換之輸出根據選定之脈 衝信號之脈衝寬度來選擇一目標灰階值。 在本發月之第二實施例中描述之共同脈衝信號 產生器830或930可形成為能夠控制脈衝信號之開，關作用 時間比率。簡s之’共同腑输拉號產生器包括用以設置一 149700.doc -16* 201128603 :線時間之每—持續時間之時間的-暫存n且在初始持續 時間中及在初始持續時間之後獲取充電時間。 如上文所描述，根據本發明之第二實施例的數位轉類比 轉換方法包括：基於經取樣之視訊資料來選擇複數個脈衝 七旎中之任一者；及在選定之脈衝信號之啟用持續時間中 切換單一時變信號且將該單一時變信號傳送至通道缓衝 益。本文中，該複數個脈衝信號為在一個線時間之一週期 内之啟用持續時間（其為脈衝寬度）不同的多個（2Ν·Μ個）脈 衝信號。 第三實施例 在上文描述的第一實施例及第二實施例中，基於具有一 電壓值之時變信號及脈衝信號之寬度來判定目標灰階電 壓。然而，在待在下文中描述之第三實施例中，基於具有 一電流值之時變信號及脈衝信號之寬度來判定該目標灰階 電壓’且所有其他構成元件及操作為相同的。 圖11Α為說明展示於圖5中之驅動器之選擇器的經修改實 例的方塊圖。 參看圖UA，TVS選擇單元426」包括1位元解碼元件 426A—1、電壓轉電流轉換（vcc)元件426C及切換器元件 426B_1 〇 1位元解碼元件426A_1基於自位準移位單元424獲得之上 部1位元資料D<5>選擇並輸出兩個電壓時變信號 !'\^_\/><0>與TVS_V<1>之間的一者。電壓轉電流轉換元件 426C自電壓位準時變信號TVS-V<〇>或TVS-V<1>(其為^立 149700.doc 201128603 元解碼元件426A一1之輸出）產生電流位準時變信號 TVS_I<〇>或TVS_I<1>。切換器元件426B_1僅在自位準移 位單元424獲得之選定之脈衝信號的啟用（其變為邏輯高位 準）持續時間中切換電壓轉電流轉換元件426C之輸出且將 電壓轉電流轉換元件426C之輸出傳送至通道緩衝器。其他 構成元件及其操作與圖5中所說明之對應構成元件大體上 相同。 本文中’通道緩衝器之輸入電壓基於電流之強度及脈衝 信號之脈衝寬度增大多達一目標電壓。 描述於圖11A中之根據本發明之該實施例的數位轉類比 轉換方法包括：基於經取樣之視訊資料中之一下部位元選 擇複數個脈衝信號中之任一者；基於經取樣之視訊資料中 之一上部位元選擇複數個電壓時變信號中之任一者；將該 選定之電壓時變信號轉換為一電流時變信號；及在選定之 脈衝信號之啟用持續時間中切換該電流時變信號且將該電 流時變信號傳送至通道緩衝器。 圖11B為說明展示於圖1〇中之驅動器之選擇器的經修改 實例的方塊圖。 參看圖11B，TVS選擇單元926一1包括電壓轉電流轉換 (VCC)元件926A及切換器元件926B。電壓轉電流轉換元件 926A自電壓位準單一時變信號TVS_V產生一電流位準時變 信號TVS_I。切換器元件926B僅在自位準移位單元924獲 得之選定之脈衝信號的啟用（其變為邏輯高位準）持續時間 中切換電壓轉電流轉換元件926A之輸出且將電壓轉電流轉 149700.doc •18· 201128603 換元件926A之輸出傳送至通道緩衝器。其他構成元件及其 操作與展示於圖10中之對應構成元件大體上相同。 根攄圖11Β之實施例的數位轉類比轉換方法包括：基於 經取樣之視訊資料選擇複數個脈衝信號中之任一者；將單 一電壓時變jg號轉換為一電流時變信號；及在選定之脈衝 信號之啟用持續時間中切換該電流時變信號且將該電流時 變信號傳送至通道緩衝器。 第四實施例 圖12為根據本發明之第四實施例的可應用於第一實施例 至第三實施例之脈衝信號的波形。 參看圖12，該圖展示當共同脈衝信號產生器產生複數個 脈衝信號PULSE <(2關]):0>時，每一脈衝信f虎之高持續 時間並未與其他脈衝信號之高持續時間重疊。換言之該 等脈衝信號可形成為在一個線時間之各別持續時間T1至 T(2(N M))中被啟用。不同於圖6中所說明之脈衝信號，一脈 衝k唬可形成為僅在達到對應灰階電壓之特定持續時間中 被啟用。 根據本發明之技術，脈衝信號產生器並未提供至每一通 道且所有通道共同使用一個脈衝信號產生器。因此，有可 成減小脈衝信號產生器之面積及電力消耗。大體而言，在 一資料驅動器中，數位轉類比轉換器佔用大部分面積及電 力消耗。 、 且’根據本發明之技術，可控制開/關作用時間比率。 可基於開/關作用時間比率適當地判定每一持續時間之充 M9700.doc -19- 201128603 電時間’且可解決由缺乏充電時間引起的惡化之視訊品質 問題。 儘管已關於特定實施例描述本發明，但熟習此項技術者 將顯而易見的是’可在不脫離如以下申請專利範圍中所界 定之本發明之精神及範疇的情況下進行各種改變及修改。 【圖式簡單說明】 圖1A為展示使用單一時變信號之習知驅動器之主要部分 的方塊圖》 圖1Β說明使用單一時變信號之驅動器的操作； 圖2Α為展示使用複數個時變信號之習知驅動器之主要部 分的方塊圖； 圖2Β說明使用複數個時變信號之驅動器的操作； 圖3為說明根據本發明之第一實施例的使用多時變信號 (TVS)產生器及共同脈衝信號產生器的顯示面板之驅動器 的方塊圖； 圖4為說明應用圖3之驅動器之單位通道區塊的詳細方塊 圖； 圖5為說明展示於圖3中之選擇器的詳細方塊圖； 圖6為展不根據本發明之一實施例的共同脈衝信號之開/ 關作用時間比率的時序圖； 圖7為說明展示於圖3中之共同脈衝信號產生器的詳細方 塊圖； η。圖8為說明根據本發明之第二實施例的使用單TVS產生 及、同脈衝钇唬產生器之驅動器的方塊圖； 149700.doc •20· 201128603 圖9為說明應用圖8之驅動器之單位通道區塊的詳細方塊 圖； 圖10為說明展示於圖9中之選擇器的詳細方塊圖； 圖11A及圖11B為說明根據本發明之第三實施例的分別 展不於圖5及圖1〇中之驅動器的選擇器之修改實例的方塊 圖；及 圖12為根據本發明之第四實施例之脈衝信號的波形。 【主要元件符號說明】 110 單時變信號產生器 120 N位元切換器 130 N位元脈衝信號產生器 140 通道緩衝器 160 時變信號 170 N位元脈衝信號 180 灰階電壓信號 210 多時變信號產生器 220 Μ位元切換器 230 (Ν-Μ)位元脈衝信號產生器 240 通道緩衝器 260 時變信號 270 脈衝信號 280 灰階電壓信號 310 多時變信號（TVS)產生器 320 選擇器 149700.doc 201128603 330 共同脈衝信號產生器 340 通道緩衝器 410 多時變信號產生器 420 選擇器 422 脈衝選擇單元 424 位準移位單元 426 時變信號選擇單元 426_1 時變信號選擇單元 426A 1位元解碼元件 426A_1 1位元解碼元件 426B 切換器元件 426B_1 切換器元件 426C 電壓轉電流轉換（VCC)元件 430 共同脈衝信號產生器 431 計數器 432 暫存器 433 加法器 434 比較與正反器單元 440 通道緩衝器 450 取樣器 452 移位暫存器單元 454 取樣/保持鎖存器單元 810 單時變信號產生器 820 選擇器 149700.doc -22- 201128603 830 840 910 920 922 924 926 926_1 926A 926B 930 940 950 952 954 共同脈衝信號產生器 通道緩衝器 單時變信號產生器 選擇器 脈衝選擇單元 位準移位單元 時變信號選擇單元 時變信號選擇單元 電壓轉電流轉換（VCC)元件 切換器元件 共同脈衝信號產生器 通道缓衝器 取樣器 移位暫存器單元 取樣/保持鎖存器單元 149700.doc -23 -Tr?NM, the m-line knife is a plurality of durations T1 to "and the duration of the mother is not corresponding to the point in Fig. 6 when the corresponding gray-scale electric dust arrives. 丨a > ^,...: Each pulse signal (from the initial time to the standard). (d) The enabled signal (which becomes a logic high bit uses a time-varying signal. The digital-to-class analog converter requires Z length in one initial duration (four) than in other durations of the _ line time). Charging time 'Because a large width voltage is required in the initial duration T1. And 'after the initial time T1, a sufficient charging time for the channel buffer to be dropped as a panel is required. When the charging time is not long enough, it occurs The offset and thus the video quality can be deteriorated. In order to prevent the deterioration of the video quality, the pulse signal generation of the driver manufactured according to the embodiment of the present invention can set the time independently for each duration. The voltage change rate according to the time of the time-varying signal is interlocked with the duration T1 to Τ(2ΝΜ) and is based on the duration 71 to (2&, change. By this method, the video quality can be solved. Fig. 7 is a detailed block diagram illustrating the common pulse signal generator 43. 149700.doc 13 201128603 Referring to Fig. 7 'common pulse signal generator 43 〇 includes counter 43 1 , register 432 , adder 433 and comparison and The flip-flop unit 434. The counter 43 1 outputs the count signal CNT_OUT ' which is increased in synchronization with the clock CLOCK and is reset by the reset signal RESET every cycle of one line time. The register store has all the continuation. Time k of the time slot T1 to T (2N M). The adder 43 3 receives the signals T1 to T (2N M) from the register 432 and outputs the on-duration of the decision pulse signal (which is a high level continuous The value of time. The comparator included in the comparison and flip-flop unit 434 generates a flag signal when any of the values is the same as the count signal CNT_OUT, and the flag signal is transmitted to the flip-flop F/F. The flip-flop jr/F enables a pulse k number when the count signal CNT_〇υτ becomes 〇", and when the flag signal is generated, it deactivates the pulse signal. Therefore, a pulse letter $puLSE is generated. And control pulse signal PULSE < (2N-M_1): 〇 > The on/off action time ratio. Second Embodiment The first embodiment described above describes the use of a plurality of time varying signals. Hereinafter, a second embodiment using a single time varying signal will be described. In the embodiment, the H embodiment uses a common pulse signal generator to be described later. The common pulse signal generator includes a register for controlling the on/off action time ratio of the pulse signal. A block diagram of a driver using a single T vs generator and a common pulse signal generator of a second embodiment of the invention. Referring to Figure 8, the driver includes a single TVS generator 81, a common pulse letter I49700.doc 201128603 generator 830 The selector 820 and the channel buffer 840. Single TVS generator 810 produces a single time varying signal. The common pulse signal generator 830 generates a plurality of pulse signals having different pulse widths. The selector 820 receives the single time varying signal, the plurality of pulse signals and the video data d<(N-1): 〇>' and selects a gray scale voltage corresponding to the video material. The channel buffer 840 outputs the output of the selector 820 to the source line of the display panel. In this article, n is a positive integer. The single time varying signal is generated corresponding to all gray scale voltages of a period of one line time. The selector 820 and the channel buffer 840 are internal constituent elements of the unit channel block and are supplied to each of the channels constituting the driver. The single generator 810 and the common pulse signal generator 83 are shared by each channel. Figure 9 is a detailed block diagram showing the unit channel block to which the driver of Figure 8 is applied. Referring to Figure 9, the driver includes a sampler 95A, a single Tvs generator 910, a common pulse signal generator 93A, a selector 92A, and a channel buffer 940. The sampler 95_N bit video data d<(n_i):〇> performs sampling. The single TVS generator 910 generates a single-time varying signal. The common pulse signal generator 930 generates a plurality of (2n) pulse signals having different pulse widths. The selector 920 receives the single-time-varying signal, the plurality of pulse signals, and the sampled video data, and selects and outputs the gray-scale power represented by the time-varying signal. The channel buffer 940 outputs the output of the selector 92 to the source line of the display panel. Sampler 950, selector 950 and pass through you. The secondary channel buffer state 94〇 is the internal component of the unit channel block and is also included in each channel of the driver. 149700.doc 201128603 Single TVS generator 910 and common pulse signal generator 93 are shared by each channel. The selector 920 includes a pulse selection unit 922, a level shifting unit, and a tvs selection unit 926. The pulse selection unit 922 selects one of a plurality of (2n) pulse signals based on the sampled video data. Bit unit 924 shifts the output signal of pulse selection unit 922, which is the selected pulse signal. The tvs selection unit 926 selects a target gray scale voltage from a single time varying signal based on the output of level shifting unit 924. The 950 includes a shift register unit and a sample/hold latch unit 954. Figure 1A is a detailed block diagram illustrating the selector 92 shown in Figure 9. In this embodiment, the driver is 6 bits. The digital to analog converter. That is, the integer N is assumed to be 6. Referring to Figure 1, the pulse selection unit 922 receives the sampled 6-bit video data D<5:0> and selects and outputs 26 pulse signals <63 Therefore, the pulse selection unit 922 can be formed as a 6-bit decoder. The second S selection unit 926 can be formed as a switch, which is only obtained in the self-alignment 4 single 924 ^The activation of the selected pulse signal ( Switching to a logic high level performs a switching on the time varying signal during the duration and transmits the time varying signal to the k-channel buffer 940. In other words, the output of the switching selects a target gray level value based on the pulse width of the selected pulse signal. The common pulse signal generator 830 or 930 described in the second embodiment of the present month may be formed to be capable of controlling the opening and closing time ratio of the pulse signal. The 'common transmission number generator includes a setting for setting A 149700.doc -16* 201128603: every time of the line time - the duration of the time - temporary storage n and the charging time is obtained in the initial duration and after the initial duration. As described above, according to the second aspect of the invention The digital to analog conversion method of an embodiment comprises: selecting any one of a plurality of pulses based on the sampled video data; and switching a single time varying signal during an enabled duration of the selected pulse signal and the single time The variable signal is transmitted to the channel buffer. In this paper, the plurality of pulse signals are the activation duration (which is the pulse width) in one cycle of one line time. a plurality of different (2Ν·Μ) pulse signals. The third embodiment is based on the width of the time-varying signal and the pulse signal having a voltage value in the first embodiment and the second embodiment described above. The target gray scale voltage is determined. However, in the third embodiment to be described hereinafter, the target gray scale voltage is determined based on the width of the time varying signal having a current value and the pulse signal, and all other constituent elements and operations are Figure 11A is a block diagram showing a modified example of the selector of the driver shown in Figure 5. Referring to Figure UA, the TVS selection unit 426" includes a 1-bit decoding element 426A-1, voltage to current conversion (vcc). The element 426C and the switch element 426B_1 〇1 bit decoding element 426A_1 obtains and outputs two voltage time-varying signals based on the upper-level 1-bit data D<5> from the level shifting unit 424!'\^_\/ ><0> and one of TVS_V<1>. The voltage-to-current conversion element 426C generates a current level time-varying signal from a voltage level time-varying signal TVS-V<〇> or TVS-V<1> (which is the output of the 149700.doc 201128603 element decoding element 426A-1) TVS_I<〇> or TVS_I<1>. The switcher element 426B_1 switches the output of the voltage to current conversion component 426C only during the duration of the enable of the selected pulse signal (which becomes a logic high level) obtained from the level shifting unit 424 and converts the voltage to the current conversion component 426C. The output is transferred to the channel buffer. The other constituent elements and their operations are substantially the same as the corresponding constituent elements illustrated in Fig. 5. In this paper, the input voltage of the channel buffer is increased by up to a target voltage based on the intensity of the current and the pulse width of the pulse signal. The digital transom conversion method according to the embodiment of the present invention described in FIG. 11A includes: selecting any one of a plurality of pulse signals based on a lower portion of the sampled video data; based on the sampled video data One of the upper portion elements selects any one of a plurality of voltage time varying signals; converts the selected voltage time varying signal into a current time varying signal; and switches the current time varying during an enable duration of the selected pulse signal The signal is transmitted to the channel buffer. Figure 11B is a block diagram showing a modified example of the selector of the driver shown in Figure 1B. Referring to Figure 11B, TVS selection unit 926-1 includes a voltage to current conversion (VCC) component 926A and a switcher component 926B. The voltage to current conversion component 926A generates a current level time varying signal TVS_I from the voltage level single time varying signal TVS_V. Switcher element 926B switches the output of voltage to current conversion component 926A only during the duration of the enable of the selected pulse signal obtained from level shifting unit 924 (which becomes a logic high level) and turns the voltage to current 149700.doc •18· 201128603 The output of the replacement component 926A is transferred to the channel buffer. Other constituent elements and their operation are substantially the same as the corresponding constituent elements shown in Fig. 10. The digital to analog conversion method of the embodiment of FIG. 11 includes: selecting any one of a plurality of pulse signals based on the sampled video data; converting a single voltage time varying jg number into a current time varying signal; and selecting The current time varying signal is switched during the enable duration of the pulse signal and the current time varying signal is transmitted to the channel buffer. Fourth Embodiment Fig. 12 is a waveform of a pulse signal applicable to the first to third embodiments according to a fourth embodiment of the present invention. Referring to Figure 12, the figure shows that when the common pulse signal generator generates a plurality of pulse signals PULSE <(2 off)): 0 >, the duration of each pulse is not consistent with other pulse signals. The time overlaps. In other words, the pulse signals can be formed to be enabled in respective durations T1 to T(2(N M)) of one line time. Unlike the pulse signal illustrated in Figure 6, a pulse k 唬 can be formed to be enabled only for a particular duration of time to reach the corresponding gray scale voltage. According to the technique of the present invention, a pulse signal generator is not supplied to each channel and a pulse signal generator is used in common for all channels. Therefore, it is possible to reduce the area and power consumption of the pulse signal generator. In general, in a data drive, the digital to analog converter takes up most of the area and power consumption. And, according to the technique of the present invention, the on/off action time ratio can be controlled. The duration of each of the durations can be appropriately determined based on the on/off action time ratio and the video quality problem caused by the lack of charging time can be solved. Although the present invention has been described with respect to the specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a block diagram showing the main part of a conventional driver using a single time-varying signal. Figure 1A illustrates the operation of a driver using a single time-varying signal; Figure 2A shows the use of a plurality of time-varying signals. A block diagram of a main portion of a conventional driver; FIG. 2A illustrates operation of a driver using a plurality of time varying signals; FIG. 3 is a diagram illustrating the use of a multi-time varying signal (TVS) generator and a common pulse in accordance with the first embodiment of the present invention. Figure 4 is a block diagram showing the unit channel block of the driver of Figure 3; Figure 5 is a detailed block diagram illustrating the selector shown in Figure 3; A timing diagram for the on/off action time ratio of a common pulse signal not according to an embodiment of the present invention; FIG. 7 is a detailed block diagram illustrating the common pulse signal generator shown in FIG. 3; Figure 8 is a block diagram showing a driver using a single TVS generating and synchronizing pulse generator according to a second embodiment of the present invention; 149700.doc • 20· 201128603 Figure 9 is a block diagram illustrating the application of the driver of Figure 8 Detailed block diagram of the block; Fig. 10 is a detailed block diagram showing the selector shown in Fig. 9; Fig. 11A and Fig. 11B are diagrams showing the third embodiment of the present invention, respectively, not shown in Fig. 5 and Fig. 1 A block diagram of a modified example of a selector of a driver in the middle; and FIG. 12 is a waveform of a pulse signal according to a fourth embodiment of the present invention. [Major component symbol description] 110 Single time-varying signal generator 120 N-bit switcher 130 N-bit pulse signal generator 140 Channel buffer 160 Time-varying signal 170 N-bit pulse signal 180 Gray-scale voltage signal 210 Multiple time-varying Signal generator 220 Μ bit switch 230 (Ν-Μ) bit pulse signal generator 240 channel buffer 260 time-varying signal 270 pulse signal 280 gray-scale voltage signal 310 multi-time-varying signal (TVS) generator 320 selector 149700.doc 201128603 330 Common pulse signal generator 340 Channel buffer 410 Multiple time varying signal generator 420 Selector 422 Pulse selecting unit 424 Level shifting unit 426 Time varying signal selecting unit 426_1 Time varying signal selecting unit 426A 1 bit Decoding component 426A_1 1-bit decoding component 426B Switcher component 426B_1 Switcher component 426C Voltage-to-current conversion (VCC) component 430 Common pulse signal generator 431 Counter 432 Register 433 Adder 434 Comparison and flip-flop unit 440 Channel buffer 450 sampler 452 shift register unit 454 sample/hold latch Element 810 Single Time Shift Signal Generator 820 Selector 149700.doc -22- 201128603 830 840 910 920 922 924 926 926_1 926A 926B 930 940 950 952 954 Common Pulse Signal Generator Channel Buffer Single Time Varying Signal Generator Selector Pulse Selecting unit level shifting unit time varying signal selecting unit time varying signal selecting unit voltage to current conversion (VCC) element switcher element common pulse signal generator channel buffer sampler shift register unit sampling/holding latch Unit 149700.doc -23 -