JP3271102B2 - Digital image signal decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal receiving / reproducing apparatus applied to record / reproduce a digital image signal by, for example, a digital VTR, and more particularly to a method for converting quantized data into a restored value. For decoding digital image signals.

[0002]

2. Description of the Related Art When a digital video signal is recorded on a recording medium such as a magnetic tape, the amount of information is large.
To achieve a recording / playback transmission rate,
It is common to compress digital video signals with high efficiency coding. ADRC and DCT (Discrete Cosine Transf) which divide a digital video signal into a number of small blocks and process each block
orm) is known.

The ADRC is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-1449.
No. 89, the dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block is determined, and high-efficiency coding that performs coding adapted to the dynamic range is performed. is there. DCT
Is to perform cosine transform on the pixels in a block, re-quantize the coefficient data obtained by the transform, and further perform variable length coding. Here, an encoding method has been proposed in which a difference between an average value for each block and an average value of pixels in the block is vector-quantized.

[0004] Conventional ADRC decoding is a process of converting a quantized code into a representative value of the quantized code and adding a minimum value to the representative value. FIG. 13 shows an example of decoding when the number of quantization bits is two. The quantization code of each pixel is one of 00, 01, 10, and 11. These quantization codes are decoded into representative values indicated by black dots in FIG. The minimum value MIN of the block is added to this representative value. The number of bits of the quantization code is fixed or variable. As the number of bits decreases, the error of the restored image with respect to the original image increases, and the restored image deteriorates.

In order to solve this problem, the present applicant has proposed a peripheral pixel data adaptive decoding apparatus (see Japanese Patent Application No. 4-282376). This decoding device outputs decoded data with a smaller error than before by referring to a mapping table prepared in advance from the pattern of the quantized data of the decoding target pixel and the quantized data of a plurality of peripheral pixels. Yes, this makes it possible to reduce errors in reproduced images without increasing recorded data.

[0006]

In the coding performed on a block basis, for example, ADRC, when the above-described method is used, if a target pixel is present at a block boundary of a target block including the target pixel, the peripheral block may be used. It is necessary to use the quantized data of the included peripheral pixels. in this case,
The quantized data of the peripheral pixels included in the peripheral block is locally decoded once, and the data locally encoded using the dynamic range and the minimum value of the target block is used.

At this time, for example, a 4-bit fixed-length ADRC
, The appearing quantized data is limited to 0 to 15. However, when a peripheral pixel is included in a peripheral block different from the target block, the quantized data of the peripheral pixel obtained as a result of local encoding is smaller than `0`,
Or it can be larger than `15 '. FIG. 14A shows an example. The bold line in the figure indicates the block boundary of the target block of (3 × 3) pixels. Five peripheral pixels included in the peripheral block are used to correct the value of the target pixel at the left corner of the target block.

In FIG. 14A, a value of `16` which should not be generated originally is included as a quantized value of a peripheral pixel. Of course, a value equal to or greater than '17' or another value may occur as quantized data of a peripheral pixel included in a peripheral block.
This is because the minimum value MIN or the dynamic range DR is not always equal between the target block including the target pixel and the peripheral block including the peripheral pixel. In the above method, the correction data table is
Since it was structured not to accept data other than 5,
In such a case, it is conceivable that data smaller than `0` is clipped with` 0` and data larger than `15 'is clipped with` 15'. FIG. 14B shows the result of clipping the data of FIG. 14A.

Therefore, when clipping occurs,
According to the peripheral pixel data adaptive decoding method described above, performance is not always as expected, and the effect of reducing the coding error between the block of interest and the peripheral block, that is, reducing the block distortion, is low. There was a case. Hereinafter, the minimum value of quantized data that can appear in correspondence with the number of quantization bits is referred to as a predetermined minimum value, and the maximum value of quantized data that can appear is referred to as a predetermined maximum value.

One method of solving this problem is to make the correction data table a structure that accepts data other than a predetermined minimum value to a predetermined maximum value.
A method of creating a correction data table by performing training also on data between blocks can be considered. When this method is used, for example, the pattern in FIG. 14A can be directly input, and in terms of image quality,
It is considered that the highest performance can be obtained for both the decoding method of the image in which the quantized data is decoded in the target block and the image in which the quantized data is decoded between the target block and the peripheral block. However, the range that the data can take when the quantized data of the peripheral block is locally decoded is much larger than a predetermined minimum value to a predetermined maximum value, and the size of the correction data table becomes enormous, The feasibility of this approach is extremely low. Also, in practice, data smaller than a predetermined minimum value,
Considering that the probability of appearance of data larger than the predetermined maximum value is not so high, the advantage of making the correction data table large cannot be expected so much.

Accordingly, an object of the present invention is to provide a method of decoding quantized data at a block boundary without enlarging a correction data table, by using data smaller than a predetermined minimum value for data of peripheral pixels included in a peripheral block. It is an object of the present invention to provide a digital image signal decoding device capable of improving the quality of a decoded image when data larger than the maximum value of.

[0012]

SUMMARY OF THE INVENTION The present invention provides a digital
In a digital image signal decoding device configured to decode transmission data obtained by quantizing an image signal in block units , peripheral pixels located around the pixel of interest are different from the pixel of interest.
Belong to different blocks when included in different blocks
Local decoding of the quantized data
To the minimum value and dynamic range of the block of interest including
Of surrounding pixels obtained by performing quantization again based on
Calculate child data, and quantized data of surrounding pixels appear
If not within the scope of ur quantized data, to fit a range of quantized data all the values of the quantized data of the peripheral pixels may appear, shifted with respect to the corresponding quantized data, or the processing of clipping Data conversion means for applying the target pixel and the peripheral image from the data conversion means.
Given the raw quantized data, the quantized data pattern
Characterized by, a correction data generation means for outputting the corrected data for the quantized data of the pixel of interest, based on the correction data, to have a decoding means for generating decoded data of the pixel of interest based on Is a digital image signal decoding device.

[0013]

In the case where non-predetermined quantized data is generated in any of the quantized data of a plurality of peripheral pixels input to the mapping table for generating an appropriate decoded value for the target pixel, the offset of the quantized data is changed. By shifting, all the quantized data of the pattern determined by the quantized data of the pixel of interest and the plurality of peripheral pixels fall within the range of the predetermined quantized data. Then, by inputting the shifted quantized data to the mapping table and shifting the obtained correction data by the same amount in the opposite direction, appropriate correction data can be obtained.

[0014]

An embodiment of the present invention will be described below. FIG. 1 illustrates this embodiment, namely, the digital VT.
1 shows a schematic configuration of R signal processing. A video signal is supplied from an input terminal 1 and one sample is digitized by the A / D converter 2 into, for example, 8 bits. The output data of the A / D converter 2 is supplied to the blocking circuit 3. In this embodiment, the blocking circuit 3 divides the effective area of one frame into blocks each having a size of (4 × 4) pixels, (8 × 8) pixels, or the like.

A digital video signal scan-converted in the order of blocks from the blocking circuit 3 is supplied to a shuffling circuit 4. In the shuffling circuit 4, for example, shuffling is performed in block units. The output of the shuffling circuit 4 is supplied to the block encoding circuit 5. The block encoding circuit 5 compresses the pixel data by requantizing the pixel data for each block. Here, the shuffling circuit 4 may be provided after the block encoding circuit 5.

In this embodiment, as the block coding,
ADRC is used. FIG. 2 is an example of a block diagram for explaining in detail the ADRC encoding circuit as the block encoding circuit 5. In FIG. 2, A /
The digital signal from the D converter 2 is supplied, and is converted by the blocking circuit 3 into a block structure. A maximum value detection circuit 22, a minimum value detection circuit 23, and a delay circuit 24 are connected to the output of the blocking circuit 3, respectively.

A maximum value detection circuit 22 detects a maximum value MAX of pixel data values for each block, and a minimum value detection circuit 23
Detects the minimum value MIN of the pixel data value for each block. In the subtraction circuit 25, (MAX-MIN) is calculated, and the dynamic range DR is detected. In the subtraction circuit 26, the minimum value MIN is subtracted from the pixel data passed through the delay circuit 24. Pixel data from which the minimum value MIN has been subtracted, that is, normalized pixel data is supplied to the quantization circuit 27.

In the quantization circuit 27, the pixel data from which the minimum value MIN has been removed is re-quantized in accordance with the dynamic range DR. As an example, 4-bit fixed length ADRC
In the case of, the quantization step DR is obtained by reducing the dynamic range DR to 1/16. The pixel data from which the minimum value MIN has been removed, that is, the normalized pixel data is divided by the quantization step Δ, and a value converted to an integer by truncating the quotient is used as the quantized data DT. The dynamic range DR, the minimum value MIN, and the quantized data DT are output data of the block encoding circuit 5. Output data of the block encoding circuit 5 is supplied to a framing circuit 6. Recording data is generated from the framing circuit 6 to the output terminal 28.

The framing circuit 6 generates parity of an error correction code and generates recording data having a structure in which sync blocks are continuous. As the error correction code, for example, a product code for performing error correction coding in each of the horizontal direction and the vertical direction of the matrix arrangement of data can be adopted. In the sync block, a sync block synchronization signal and an ID signal are added to encoded data and parity. Recording data in which sync blocks continue is supplied from the framing circuit 6 to the channel encoding circuit 7, and the channel encoding circuit 7 undergoes encoding processing for reducing the DC component of the supplied recording data.

The output data of the channel encoding circuit 7 is converted into a bit stream, and is further supplied to the rotary head H via the recording amplifier 8 so that the recording data is transferred to the magnetic tape T.
Recorded as diagonal tracks on top. Usually, a plurality of rotating heads are used, but for simplicity only one head is shown.

The reproduction data taken out of the magnetic tape T by the rotary head H is supplied to a channel decoding circuit 12 via a reproduction amplifier 11 and is subjected to channel coding decoding. Output data of the channel decoding circuit 12 is supplied to a frame decomposing circuit 13, where various data are separated from recording data and error correction is performed. The output data generated from the frame decomposition circuit 13 includes, in addition to the reproduced data, an error flag indicating whether or not the error has been corrected.

The output data of the frame decomposition circuit 13 is supplied to an important word correction circuit 14. The important word correction circuit 14
An important word indicating an error by the error flag (that is, the dynamic range DR for each block)
And the minimum value MIN). here,
When the important word correction circuit 14 cannot correct the error,
It is desirable to have a function of estimating an important word. The output data of the important word correction circuit 14 is the block decoding circuit 1
5 is supplied. The block decoding circuit 15 performs ADRC decoding by using a non-error key word.
For a block in which an important word is in error, the important word correction circuit 14 performs ADRC decoding using the corrected important word. The block decoding circuit 15, as described later,
A decoded value is generated with reference to a mapping table for correction.

The decoded data of the block decoding circuit 15, that is, restored data corresponding to each pixel is supplied to the deshuffling circuit 16. This deshuffling circuit 1
Numeral 6 is complementary to the shuffling circuit 4 on the recording side.
A process of returning the spatial position of the block to the original position is performed.
Output data of the deshuffling circuit 16 is supplied to a block decomposition circuit 17. In the block decomposition circuit 17, the order of the data is returned to the order of the raster scanning. The output data of the block decomposition circuit 17 is supplied to an error interpolation circuit 18. The error interpolation circuit 18 performs error detection on a pixel-by-pixel basis. The pixel data detected as an error is interpolated with peripheral pixel data.

As the interpolation processing, for example, a processing in which an interpolation circuit in a spatial direction, that is, a two-dimensional direction and an interpolation circuit in a time direction are sequentially connected can be used. Output data of the error interpolation circuit 18 is supplied to a D / A converter 19, and an output terminal 20
, Restored data in the raster scanning order corresponding to each pixel is obtained.

The present invention is applied to the block decoding circuit 15 described above. FIG. 3 shows an example of the block decoding circuit 15 according to the present invention. Reproduction data is supplied from an input terminal denoted by reference numeral 41 to the frame decomposition circuit 13, where the dynamic range DR, the minimum value MIN, and the quantized data DT are separated from the supplied reproduction data, extracted, and output. You. Here, in FIG. 3, the important word correction circuit 14 is omitted from the drawing because it has no direct relation to the gist of the present invention.

The quantized data DT is supplied to the memory 43. When the peripheral pixel exists in the block of interest including the pixel of interest, the memory 43 sets the quantized data of, for example, (3 × 3) pixels around the pixel of interest to be decoded as one block, and the data conversion circuit 44 Output to When the peripheral pixel exists in a peripheral block different from the target pixel, the quantized data of the peripheral pixel is locally decoded once, and further, the local value is locally determined using the dynamic range DR and the minimum value MIN of the target block including the target pixel. Quantization. The quantized data is output from the memory 43 to the data conversion circuit 44.

By the way, for example, a 4-bit fixed-length ADRC
In the case of, the appearing quantized data DT is limited to 0 to 15. Therefore, the correction data table 45 is configured to receive only a combination of 0 to 15 data. However, when the peripheral pixel is included in a peripheral block different from the target block, the quantized data of the peripheral pixel sent from the memory 43 may be smaller than '0' or larger than '15'. Hereinafter, an example of 4-bit fixed-length ADRC will be described. In this case, `0` is a predetermined minimum value and` 15 'is a predetermined maximum value.

Therefore, the data conversion circuit 44 performs a process of transforming the data sent from the memory 43 into a form applicable to the correction data table 45. Data conversion circuit 44
Is larger than a predetermined maximum value and the minimum value in the quantized data is equal to or greater than the predetermined minimum value, the data conversion circuit 44 determines whether or not (in the quantized data, Subtraction is performed from all the quantized data by a difference value of (minimum value−predetermined minimum value). That is, the quantized data is shifted by the amount of the difference value.

For example, in the quantized data shown in FIG. 7A, the above-mentioned difference value becomes “14”, and the data conversion circuit 44 shifts the quantized data by “14”, and the quantized data shown in FIG. Is output. Here, in the shifted quantized data, when the maximum value in the quantized data is equal to or smaller than a predetermined maximum value, the data conversion ends. For example, no further conversion is performed on the data of FIG. 7B.

On the other hand, in the quantized data once shifted, if the maximum value in the quantized data is larger than the predetermined maximum value, a process of clipping the quantized data larger than the predetermined maximum value to the predetermined maximum value is performed. Apply. For example, FIG.
The difference value of the quantized data indicated by A is “8”, and the quantized data is shifted by “8” to each quantized data, and is converted into the quantized data of FIG. 8B. Even after this shift, there is quantized data (`17 'and` 18' values) larger than a predetermined maximum value, so that quantized data larger than the predetermined maximum value is converted to a predetermined maximum value (`15 '). Is performed, and the quantized data of FIG. 8B is converted into the quantized data of FIG. 8C.

Here, the maximum value in the quantized data supplied to the data conversion circuit 44 is equal to or less than a predetermined maximum value,
If the minimum value in the quantized data is smaller than the predetermined minimum value, the data conversion circuit 44 adds the difference value of (predetermined maximum value-maximum value in the data) to all the quantized data. . That is, the quantized data is shifted by the amount of the difference value.

For example, the quantized data shown in FIG. 9A has a difference value of `13` and is shifted by` 13` to each quantized data, and is converted into the quantized data of FIG. 9B. Here, in the shifted quantized data, when the minimum value in the quantized data is equal to or larger than a predetermined minimum value, the data conversion ends. For example, no further conversion is performed on the data in FIG. 9B.

On the other hand, in the quantized data once shifted, if the minimum value in the quantized data is smaller than the predetermined minimum value, a process of clipping the quantized data smaller than the predetermined minimum value to the predetermined minimum value is performed. Apply. For example, FIG.
10A, the difference value is “10”, and the quantized data is shifted by “10” for each quantized data.
Is converted to quantized data. Even after this shift, since there is quantized data (`-2` value) smaller than the predetermined minimum value, the quantized data is changed to the predetermined minimum value (` 0 ').
) Is subjected to clipping processing, and the quantized data in FIG. 10B is converted to the quantized data in FIG. 10C.

If the maximum value in the quantized data supplied to the data conversion circuit 44 is larger than the predetermined maximum value and the minimum value in the quantized data is smaller than the predetermined minimum value, the data conversion is performed. The circuit 44 performs a process of clipping quantized data larger than a predetermined maximum value to a predetermined maximum value and clipping quantized data smaller than a predetermined minimum value to a predetermined minimum value. For example, FIG.
Each value of `-6` and` 18` in the quantized data shown in 1A corresponds to the above-described condition. Therefore, `0 'and` 15'
Respectively, and the quantized data of FIG. 11A is converted into the quantized data of FIG. 11B.

However, the maximum value in the quantized data supplied to the data conversion circuit 44 is equal to or less than a predetermined maximum value,
When the minimum value in the quantized data is equal to or larger than the predetermined minimum value, the data conversion circuit 44 does not perform the shift processing on the quantized data. For example, the quantized data shown in FIG. 12 is not converted.

When quantization data is shifted in the data conversion circuit 44, the shift amount, that is, the difference value is transmitted from the data conversion circuit 44 to the correction data conversion circuit 46. The correction data conversion circuit 46 holds this shift amount.

The output of the data conversion circuit 44 is supplied to a correction data table 45. When the combination of the quantized data is supplied, the correction data table 45 converts the quantized data DT of the pixel of interest into an optimal correction value and outputs it. The correction data table 45 is configured by a memory, and stores correction values formed in advance by training as described later. The read output of the correction data table 45 is supplied to the correction data conversion circuit 46.

When data is shifted in the data conversion circuit 44, the correction data conversion circuit 46 uses the amount of shift supplied from the data conversion circuit 44 to hold the output data of the correction data table 45. Then, the correction is performed by the shift amount in the direction opposite to the correction performed by the data conversion circuit 44. For example, if the data conversion circuit 44 performs a shift of “+2” and the output data of the correction data table 45 is “7.2438”, the correction data conversion circuit 46 performs a shift of “−2”, The data is converted to `5.2438 '. The output signal F of the correction data conversion circuit 46 is supplied to a decoding circuit 47.

The decoding circuit 47 is a circuit for decoding the data of interest. For the decoding circuit 47, the dynamic range DR and the minimum value MIN
And an output signal F is supplied from the correction data conversion circuit 46. The decoding circuit 47 includes a multiplication circuit and an addition circuit.
The decoded value L supplied to 8 is represented by the following equation. L = [F × Δ + MIN + 0.5] where Δ is a quantization step and [] is a Gaussian symbol.

FIG. 4 shows an example of a block diagram at the time of training for creating the correction data table 45. 4, a digital video signal is supplied to an input terminal 51, and the supplied digital video signal is ADR.
It is input to the C encoding circuit 52. This input data is preferably a standard digital video signal for training. Here, for ease of explanation, as shown in FIG. 6, one block is treated as coded data C1 to C9 as an area of (3 × 3) pixels.

The ADRC encoding circuit 52 performs an ADRC encoding process on the input digital video signal, and supplies encoded data C1 to C9 to the synchronization circuit 53.
× 3) The pixel of interest C5 located at the center of the pixel is added to the addition circuit 5
Supply to 4. At this time, the encoded data C1 to C9 supplied to the synchronization circuit 53 are integer-converted values, and the pixel of interest C5 supplied to the addition circuit 54 is data before conversion to integers, for example, This is the value up to the fourth decimal place.

In the memory 55, the encoded data C1 to C9 are supplied from the synchronization circuit 53 and the address RAD is supplied from the address counter 58, respectively. The encoded data C1 to C
Reference numeral 9 denotes an address AD from the synchronization circuit 53 to the memory 5.
5. The data read from the address AD is supplied from the memory 55 to the adding circuit 57, and the adding circuit 57 adds "1". The output result of the adding circuit 57 is written to the address AD read from the memory 55. Therefore, each address of the memory 55 stores the frequency data of that address.
That is, the memory 55 counts the number of occurrences of the pattern of the coded data C1 to C9 of the peripheral pixels supplied from the synchronization circuit 53, and creates a frequency distribution table. This memory 55
In one cycle, reading and writing are performed in one cycle period.

In the memory 56, the encoded data C1 to C9 are supplied from the synchronization circuit 53 and the address RAD is supplied from the address counter 58, respectively. The encoded data C1 to C
Reference numeral 9 denotes an address AD from the synchronization circuit 53 to the memory 5.
6. The data read from the address AD is supplied from the memory 56 to the addition circuit 54, and the addition circuit 54 adds the coded data C5 of the target pixel and the data read from the memory 56. The output result of the adding circuit 54 is written to the address AD read from the memory 56. Therefore, at each address of the memory 56, the integrated value of the encoded data of the pixel of interest at that address is stored. That is, in the memory 56,
The pattern of the encoded data C1 to C9 of the peripheral pixels supplied from the synchronization circuit 53 is compared with the encoded data C5 of interest.
Create an integrated value of. In addition, as with the memory 55, reading and writing are performed in the memory 56 in one cycle period.

When the processing of the digital video signals of various patterns is completed, that is, when the training is completed, the frequency distribution table is stored in the memory 55, and the integrated value of the encoded data is stored in the memory 56. The data at each address in the memories 55 and 56 is read by the address RAD supplied from the address counter 58. The data respectively read from the memories 55 and 56 are supplied to a dividing circuit 59. The dividing circuit 59 divides the integrated data by a frequency and obtains an average value (for example, a value up to the fourth decimal place). ) Occurs, and the average value is supplied to the correction data table 60. In the correction data table 60, the average value supplied from the division circuit 59 is written to the address RAD supplied from the address counter 58.

As a result of the training performed as described above, the encoded data C1 to C1 are stored in the correction data table 60.
A value statistically closest to the true value of the coded data C5 of the target pixel is stored for each pattern defined by C9. The table stored in the correction data table 60 is the correction data table 45 used in the block decoding circuit 15 as described above.

FIG. 5 shows an example of the above-mentioned correction data table. The patterns of the encoded codes C1 to C9 in FIG. 5 are output from the synchronization circuit 53.
This is an example where the ADRC encoding circuit 52 is a 2-bit ADRC. 5 is stored in the memory 56 for each pattern. The number of appearances is stored in the memory 55.
The dividing circuit 59 forms an average value, that is, correction data. By training using actual images. The value of the correction data can be automatically made suitable for the actual image.

Although the above embodiment is an example in which the present invention is applied to a two-dimensional block ADRC, the present invention can be applied to a three-dimensional block ADRC. Further, in the case of performing decoding using a weighting factor separately from the method of performing decoding using an average value in the above-described embodiment,
A weight coefficient corresponding to each of the encoded data C1 to C9 is obtained using a linear linear combination expression. The weight coefficient is determined so that the error between the pixel of interest and the encoded data C5 is minimized. Therefore, the obtained weight coefficient is stored in the correction data table 60 and is decoded using the linear combination equation.

[0048]

According to the present invention, even in the decoding of data at a block boundary, the ratio of the pattern of the encoded data of the pixel of interest to be decoded and the encoded data of a plurality of peripheral pixels, for example, the clipping ratio, is greatly increased. , It is possible to reduce performance degradation in decoding data at block boundaries. Also, there is no increase in the amount of transmitted information,
It has the advantage that the hardware burden is small.

[Brief description of the drawings]

FIG. 1 shows a digital V to which the present invention can be applied.
It is a block diagram of a recording / reproducing circuit of TR.

FIG. 2 is a block diagram illustrating a configuration of an example of an ADRC encoding circuit to which the present invention can be applied;

FIG. 3 is a block diagram illustrating an example of a configuration of a block decoding circuit to which the present invention has been applied.

FIG. 4 is a block diagram showing a configuration at the time of training for creating a correction data table in one embodiment of the present invention.

FIG. 5 is a schematic diagram for explaining a case where a correction data table is created.

FIG. 6 is a schematic diagram for explaining a case where a correction data table is created.

FIG. 7 is a schematic diagram for explaining a pattern data modification method according to the present invention;

FIG. 8 is a schematic diagram for explaining a pattern data modification method according to the present invention.

FIG. 9 is a schematic diagram for explaining a pattern data modification method according to the present invention.

FIG. 10 is a schematic diagram for explaining a pattern data modification method according to the present invention.

FIG. 11 is a schematic diagram for explaining a pattern data modification method according to the present invention.

FIG. 12 is a schematic diagram for explaining a pattern data modification method according to the present invention.

FIG. 13 is a schematic diagram illustrating an example of quantization of ADRC.

FIG. 14 is a schematic diagram for explaining a conventional pattern data deformation method.

[Explanation of symbols]

 13 Frame decomposition circuit 44 Data conversion circuit 45 Correction data table 46 Correction data conversion circuit 47 Decoding circuit

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Claims (3)

(57) [Claims] In a digital image signal decoding apparatus for decoding transmission data obtained by quantizing a digital image signal in block units , peripheral pixels located around the target pixel are different from the target pixel.
Are included in different blocks,
Locally belonging quantized data, and the above peripheral pixels are
The minimum value of the block of interest including the pixel of interest and the dynamics
Obtained by performing quantization again based on the cleanse
Calculating a quantized data of the peripheral pixels, if not included within the scope of the quantized data quantized data of the peripheral pixels can appear, the quantization of all values of the quantized data of the peripheral pixels can appear above Data conversion means for performing a shift or clipping process on the corresponding quantized data so as to fall within the range of data ; and
Given raw quantized data, the pattern of the quantized data
Correction data generating means for outputting correction data for the quantized data of the pixel of interest based on the pattern, and decoding data of the pixel of interest based on the correction data. decoding apparatus in a digital image signal; and a decoding means. 2. The digital image signal decoding device according to claim 1, wherein an error is statistically minimized for each pattern determined by the quantized data of the target pixel and the quantized data of the plurality of peripheral pixels. An apparatus for decoding a digital image signal, comprising a memory storing such correction data. 3. A decoding apparatus, the correction data supplied is from the correction data generating means of the digital image signal according to claim 1
The shift or clock in the data conversion means.
In the opposite direction to ripping, the supplied correction data is
The image processing apparatus further includes correction data conversion means for shifting, wherein the decoding means outputs the correction data as the correction data.
Using the correction data shifted by the
A decoding device for a digital image signal, which generates decoded data of a pixel of interest .