JP3269284B2 - Decision feedback type equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decision feedback equalizer in digital signal processing.

[0002]

2. Description of the Related Art A conventional decision feedback equalizer has been realized with the configuration shown in FIG. FIG. 1 shows a 4-tap decision feedback equalizer. This will be described for a case where a BT equalizer for ping-pong transmission in a digital subscriber line is realized.

In FIG. 1, reference numeral 1 denotes a signal input means which samples an input signal and converts it into digital data.
Reference numeral 2 denotes a signal equalizing means for performing an equalizing process on the digital data converted by the signal input means 1. Numeral 3 denotes data determining means for determining the data which has been equalized by the signal equalizing means 2,
The result of the determination is output. Reference numeral 4 denotes a delay unit that holds the result of the previous data determination. Reference numeral 5 denotes a delay unit that holds the data determination result two times before. Reference numeral 6 denotes a delay unit that holds the data determination result three times before. Reference numeral 7 denotes a delay device that holds the data determination result four times before. A multiplier 8 performs a multiplication operation of the equalized data h1 and the delay unit 4. 9 is a multiplier, and the equalized data h
The multiplication operation of 2 and the delay unit 5 is performed. A multiplier 10 performs a multiplication operation of the equalized data h3 and the delay unit 6. A multiplier 11 performs a multiplication operation of the equalized data h4 and the delay unit 7. Reference numeral 12 denotes an adder for adding the outputs of the multipliers 8, 9, 9, 10 and 11 to obtain an equalization amount.

The operation of the above configuration will be described. The signal input converted into digital data by the signal input means 1 is
Equalization processing is performed in the signal equalization means 2 using the equalization amount output from the adder 12. The data determination unit 3 determines the data that has been equalized by the signal equalization unit 2 and outputs the determination result. The delay unit 4 holds the determination result of the data determination unit 3, the delay unit 5 holds the data determination result of the delay unit 4, the delay unit 6 holds the data determination result of the delay unit 5, and the delay unit 7 The data judgment result of the delay unit 6 is held. As described above, each time the result is updated by the data determination unit 3, the data determination result is updated. When the updating of each delay unit is performed, the multiplier 8 equalizes the data h1 and the delay unit 4
, The multiplier 9 performs a multiplication operation on the equalized data h2 and the delay unit 5, the multiplier 10 performs a multiplication operation on the equalized data h3 and the delay unit 6, and the multiplier 11 performs a multiplication operation on the equalized data h4.
And the delay unit 7 are multiplied. The adder 12 adds each of the outputs of the multiplier 8, the multiplier 9, the multiplier 10, and the multiplier 11, obtains an equalization amount, and outputs the equalization amount to the signal equalization means.

The setting of the equalization data h1, h2, h3, h4 will be described with reference to FIG. In FIG. 2, reference numeral 13 denotes digital data which is sampled by the signal input means 1 and output. 14 is equalization processing data,
The signal is equalized by the signal equalizing means 2 and output.

Referring to FIG. 2, a method for setting equalized data will be described. In the training mode based on the isolated pattern of the ping-pong transmission in the digital subscriber line, the input signal is sampled by the signal input means 1 and the digital data 13 is output. Where h1, h2,
h3 and h4 are equalization data necessary for the BT equalization processing.
The BT equalizer detects the 4-tap equalized data in the training mode, and outputs the equalized data h1 to the multiplier 8, the equalized data h2 to the multiplier 9, and the equalized data h3 to the multiplier 10 in FIG. , And the multiplier 11 holds the equalized data h4. As a result, in the training mode, the signal equalization means 2
Is output like the equalization processing data 14.

[0007]

However, in order to realize a decision feedback equalizer by software processing using a processor in the configuration of the conventional example described above, processing time for multiplication processing and addition processing for the number of taps is required. And real-time processing was difficult.

In view of the above problems, the present invention performs an equalization process operation for the number of taps in advance, creates an equalization table using addresses of past determination results as addresses, and calculates an equalization amount from the equalization table. An object of the present invention is to provide a decision feedback equalizer realized by software processing by taking out and performing equalization processing.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, a decision feedback equalizer according to the present invention provides a transmission mode in which a transition is made to a normal communication mode via a training mode of an isolated pulse. Signal input means for sampling an input signal and converting it to digital data;
The digital data converted by the signal input means is determined, the data determination means for outputting the result of the determination, and the digital data of the signal input means are used for signal equalization based on the past determination result of the data determination means. A data capturing unit that captures as equalized data for each tap of the equalizer; and an equalization amount corresponding to all addresses generated by the equalization amount selection unit based on the equalization data captured by the data capturing unit. The digital data converted by the signal input means in a communication mode is constituted by accumulated data creating means for calculating and outputting the data, and equalizing amount accumulating means for storing the equalized amount created by the accumulated data creating means. A signal equalizing unit that performs equalization processing with the equalization amount output from the equalization amount accumulation unit; and a data equalized by the signal equalization unit. A data determination unit that outputs the determination result, and an equalization amount selection unit that holds the past determination result of the data determination unit and generates an address for reading the equalization amount from the equalization amount accumulation unit. It is provided with.

[0010] Further, an equalization residue by the signal equalization processing means is detected from the judgment result output by the data judgment means and the data equalized by the signal equalization means. A storage correction unit that corrects the equalization data for each tap of the equalizer based on, and an equalization amount of the input signal data is calculated based on the equalization data corrected by the storage correction unit. And storage data creating means for storing.

The equalization amount accumulating means has a function of storing an equalization amount for compensating by determining that the forbidden pattern is erroneous when the forbidden pattern is detected by the equalization amount selecting means. .

In the ping-pong transmission, the data capturing means has a function of performing a timing synchronization process before capturing the equalized data, thereby capturing the equalized data with a small sampling bit synchronization deviation.

[0013] In the ping-pong transmission, the data fetching means includes a signal data accumulating means for holding one burst of signal data of a received signal in a memory, and a training signal specific to burst transmission from the signal data accumulating means. Signal data selecting means for selecting received data from which signal distortion due to intersymbol interference of frame bits has been removed, and averaging the signal data selected by the signal data selecting means, and using the result of the calculation as equalized data It is provided with equalization data calculation means.

[0014]

According to the present invention, the following operations are performed by the above configuration.

In the training mode, the signal input means samples the input signal and converts it into digital data. The data determination means determines the digital data converted by the signal input means and outputs a result of the determination. The data capturing means captures digital data of the signal input means as equalized data for each tap of an equalizer for signal equalization based on a past determination result of the data determining means. The accumulated data creation means calculates and outputs an equalization amount corresponding to all addresses generated by the equalization amount selection means based on the equalization data fetched by the data fetching means. The equalization amount accumulation means stores the equalization amount created by the accumulation data creation means.

In the communication mode, the signal equalizing means performs an equalization process on the digital data converted by the signal input means with an equalization amount output from the equalization amount storage means. The data determination means determines the data that has been equalized by the signal equalization means, and outputs a result of the determination. The equalization amount selection means holds the past judgment result of the data judgment means and generates an address for reading the equalization amount from the equalization amount accumulation means.

The equalization amount accumulating means has a function of storing an equalization amount for compensating the prohibited pattern by judging the error pattern as an error when the equalization amount selecting means detects the prohibited pattern. Can be provided.

The accumulation correction means detects an equalization residue in the signal equalization processing means from the judgment result output from the data judgment means and the data equalized by the signal equalization means. The equalization data for each tap of the equalizer is corrected based on the remaining equalization. The accumulated data creation means calculates an equalization amount of the input signal data based on the equalized data corrected by the accumulation correction means, and stores the calculated amount in the equalization amount accumulation means. In addition,
The accumulation correction means and the accumulation data creation means do not need to be constantly operated, but may be operated periodically, for example, in the case where all of the equalization data of four taps is corrected based on the result of the binary decision, and the processing efficiency and noise may be reduced. It is possible to design in consideration of the followability such as.

Further, the data capturing means in the ping-pong transmission captures the equalized data with a small sampling bit synchronization deviation by performing a timing synchronization process before capturing the equalized data.

Further, the data fetch means operates as follows. The signal data accumulating means holds all the signal data of the received signal for one burst in the memory. The signal data selecting means selects received data from the signal data accumulating means, excluding signal distortion due to inter-symbol interference of frame bits due to a training signal specific to burst transmission. The equalization data calculation means performs an average calculation of the signal data selected by the signal data selection means, and sets the calculation result as equalized data.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A decision feedback equalizer according to one embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 3 shows a BT equalizer for ping-pong transmission using a digital subscriber line according to Embodiment 1 of the present invention, in which an equalization amount corresponding to a past judgment result is created in advance and stored. FIG. 3 is a block diagram of a 4-tap decision feedback equalizer that realizes an equalizer by extracting the accumulated equalization amount.

In FIG. 3, reference numeral 1 denotes signal input means for sampling an input signal and converting the input signal into digital data.
Numeral 15 is a mode switching means for switching the output destination of the digital data output from the signal input means 1 in the training mode and the output destination in the communication mode. Numeral 3 denotes data determining means for determining the digital data of the signal input means 1 output via the mode switching means 15 in the training mode into three values of "1", "0", and "-1". The result of the value judgment is "01" and "
The data is output as 00 "," 10 ", and 16 is a data capturing means for detecting the output of the signal input means 1 as the equalized data h1, h2, h3, h4 based on the determination result of the data determining means 3. Here, the equalization data h1 for equalizing the first tap is output data sampled by the signal input unit 1 at the last “0” when the binary determination result is determined to be “000010”. Similarly, the equalized data h2 at the second tap is the last “0” when the binary determination result is determined to be “000100”, and the equalized data h at the third tap.
3 is the last “0” when the binary determination result is “001000”, and the equalization data h4 at the fourth tap is 2
When the value determination result is determined to be "010000", the output of the signal input means 1 at the last "0" is equalized data at each tap. Note that the binary determination result here is that “0” is “0”, “1” and “−”.
“1” represents the result determined to be “1” 17. Numeral 17 denotes accumulated data creating means, which equalizes all past ternary determination result patterns using the equalized data detected by the data fetching means 16. Numeral 18 denotes an equalization amount accumulating means for preliminarily determining an equalization amount for equalizing input signal data for each combination of past ternary judgment results output from the accumulated data creating means 17. It is an equalization amount table stored.

Numeral 2 denotes a signal equalizing means, which calculates the equalization amount stored in the equalization amount accumulating means 18 from the digital data of the signal input means 1 output via the mode switching means 15 in the communication mode. An equalization process for subtraction is performed. 19
Is data determination means, which determines the data equalized by the signal equalization means 2 into three values of "1", "0", and "-1", and determines the three-valued determination result as "01" in binary. ”,” 0
Outputs as 0 "and" 10 "20 is an equalization amount selection means,
The past ternary determination result of the data determination unit 19 is held as an 8-bit address, and an address for reading the accumulated equalization amount is generated.

The operation of the decision feedback equalizer configured as described above will be described with reference to FIG.

First, in the training mode,
When a signal is input from the transmission line, the input signal is sampled in the signal input means 1 and converted into digital data. In the training mode, digital data output from the signal input means 1 is output to the data determination means 3 and the data acquisition means 16 in the mode switching means 15. The data determination means 3 converts the digital data output via the mode switching means 15 into "
1 "," 0 ", and" -1 "are determined, and the ternary determination results are expressed as binary numbers" 01 "," 00 ", and" 10 ", respectively.
To output. The data capturing unit 16 determines a past binary determination result pattern based on the determination result output from the data determination unit 3, and outputs the same via the mode switching unit 15 if the pattern is a pattern that detects equalized data. Import digital data as equalized data. The accumulated data creation unit 17 detects the 4
An equalization table is constructed based on the equalization data for the taps, and the equalization amount based on the equalization data detected as a result is stored in the equalization amount accumulation means 18.

When the training mode is completed and the mode is shifted to the communication mode, when a signal is input from the transmission line, the input signal is sampled in the signal input means 1 and converted into digital data. In the communication mode, digital data output from the signal input means 1 is output to the signal equalization means 2 in the mode switching means 15. The signal equalizing means 2 stores the equalizing amount accumulating means 18 with respect to the digital data output via the mode switching means 15.
The equalization processing is performed by subtracting the equalization amount output from. Next, the data determination unit 19 determines the data equalized by the signal equalization unit 2 into three values of “1”, “0”, and “−1”, and determines the three-valued determination results in binary numbers. "0
1 "," 00 ", and" 10 "Next, the equalization amount selection means 20 holds the past four taps of the determination result output by the data determination means 19, and assigns an 8-bit address. Generate.

Here, a method of generating an address in the equalization amount selecting means 20 will be described with reference to FIG.

FIG. 4 is a diagram illustrating a method of generating an address according to the present invention. 21 is the last generated 8
It is a bit address. Reference numeral 22 denotes a two-bit determination result output from the data determination unit 19. 23 is an 8-bit address generated this time.

The method of FIG. 4 will be described. Regarding the address generation, the previous 8-bit address 21 has the ternary judgment result four times before the D7 and D6 bits, the ternary judgment result three times before the D5 and D4 bits, and twice the D3 and D2 bits. The previous ternary determination result is represented by the D1 and D0 bits, which represent the previous ternary determination result. Therefore, in order to generate the current 8-bit address, first, the previous 8-bit address is shifted left by 2 bits. As a result, the ternary determination result three times before is stored in the D7 and D6 bits, the ternary determination result two times before is stored in the D5 and D4 bits, and the ternary determination result one time before is stored in the D3 and D2 bits. Next, the 2-bit decision result 22 output by the data decision means 19 is inserted into the D1 and D0 bits. As a result, the current 8-bit address 23 is generated.

By performing the above operation, an 8-bit address is easily created. When an 8-bit address is generated by the equalization amount selecting means 20, the equalization amount accumulating means 18 reads the next input signal from the equalization table corresponding to the address generated by the equalization amount selecting means 20. The equalization amount for performing the equalization process is read out and output.

As described above, the BT equalizer can be realized by referring to the table based on the past determination result.
The processing time of the T equalizer can be reduced.

(Embodiment 2) FIG. 5 shows a BT equalizer for ping-pong transmission using a digital subscriber line according to Embodiment 2 of the present invention, in which an equalization amount corresponding to a past judgment result is created in advance and stored. A four-tap decision feedback type or the like having a function of realizing an equalizer by extracting the accumulated equalization amount, and having a function of detecting an equalization residue and correcting the accumulated equalization amount. FIG. 2 is a block diagram showing a case where the present invention is realized by a converter.

In FIG. 5, reference numeral 1 denotes a signal input means which samples an input signal and converts it into digital data.
Reference numeral 2 denotes a signal equalizing means for performing an equalizing process of subtracting an equalization amount from the digital data converted by the signal input means 1. 1
Numeral 9 is a data determining means for determining the data equalized by the signal equalizing means 2 into three values of "1", "0", and "-1".
The ternary determination results are expressed as binary numbers “01” and “0”, respectively.
Outputs as 0 "and" 10 "20 is an equalization amount selection means,
The past ternary determination result of the data determination unit 19 is held as an 8-bit address, and an address for reading the accumulated equalization amount is generated. Reference numeral 18 denotes an equalization amount storage unit, which is an equalization amount table in which equalization amounts for equalizing input signal data for each combination of past ternary determination results are stored in advance, and are generated by the equalization amount selection unit 20. Output according to the specified address. Note that the process of storing the equalization amount in the equalization amount accumulation means 20 is performed by detecting the equalization data of the four taps of the decision feedback equalizer in the training mode of the isolated pulse, and adding the same to the past ternary determination result. The corresponding equalization amount is calculated and stored in advance. Numeral 24 denotes an accumulation correcting means for detecting a residual equalized by the signal equalizing means 2 from the judgment result outputted by the data judging means 19 and the data which has been subjected to the equalizing processing by the signal equalizing means 2. The equalization data is corrected based on the remaining. Here, as for the equalization residual in the equalization data h1 for equalizing the first tap, the binary determination result is “00001”.
The result of the equalization processing by the signal equalizing means 2 at the last “0” when it is determined to be “0.” Similarly, for the equalization residue of the second tap, the binary determination result is “000100”. The final "0" in the case where it is determined that the last tap is equal to the last "01000" in the case where the binary determination result is "001000".
0, the equalization residue of the fourth tap is “010”
000 "means that the output at the last" 0 "is equalization residue at each tap. In this case, the binary judgment result is that" 0 "is" 0 ", "
“1” and “−1” represent the results determined to be “1.” Reference numeral 25 denotes a stored data creating unit, and all past ternary determinations are made using the equalized data corrected by the storage correcting unit 24. The equalization amount is calculated for the result pattern, and the equalization amount accumulation means 1
8 is stored.

The operation of the decision feedback equalizer configured as described above will be described with reference to FIG.

When a signal is input from the transmission line, the input signal is sampled in the signal input means 1 and converted into digital data. The signal equalizing means 2 performs an equalizing process by subtracting the equalizing amount output from the equalizing amount accumulating means 18 on the digital data converted by the signal inputting means 1. Next, the data determination unit 19 converts the data equalized by the signal equalization unit 2 into “1”, “0”, “−”.
The ternary value is determined as a ternary value of “1”, and the ternary determination result is output in binary notation as “01”, “00”, and “10”. The 8-bit address is generated by retaining the past 4 taps of the determination result, and the equalization amount accumulating unit 18 inputs the next input from the equalization table corresponding to the address generated by the equalization amount selecting unit 15. The accumulation correction unit 24 reads out and outputs an equalization amount for performing equalization processing on the signal, and determines a past binary determination result pattern based on the determination result output from the data determination unit 19 to perform equalization. In the case of a pattern for correcting data, the equalization processing data which has been equalized by the signal equalization means 2 is taken in as an equalization residue, and is then fixed to the equalization residue so as to be less susceptible to noise. Multiply variables,
Adds the result of multiplication to the current equalized data,
This addition result is treated as corrected equalized data. The accumulated data creation unit 25 reconstructs the equalization table based on the corrected equalization data, and as a result, the equalization amount based on the corrected equalization data is stored in the equalization amount accumulation unit 18.

The provision of the accumulation correction means eliminates the necessity of always operating the processing for performing the correction processing, the correction processing of the decision feedback equalizer can be realized if necessary, and the processing time of the BT equalizer can be reduced. Processing efficiency can be improved.

(Embodiment 3) Table 1 shows that in the BT equalizer for ping-pong transmission using a digital subscriber line according to the third embodiment of the present invention, an equalization amount corresponding to a past judgment result is previously created and stored. 9 is a table illustrating a storage method of an equalization amount storage unit to be kept.

[0039]

[Table 1]

Table 1 shows the past ternary judgment results as seen from the point of time of the equalization processing. Case 1 consists of "1" and "-
1 "appear alternately, and the result of adding the equalization data of each tap is stored in a table. Case 2
Is a forbidden pattern in which "-1" is continuously determined in three values. If this is added as it is to the equalized data, the effect of the prohibition will be affected even at the present time. Therefore,
As a countermeasure, the second determination of "-1" is determined to be an error, and is replaced with "0" to calculate the equalization amount.

This countermeasure is an example. However, as for the storage method of the equalization amount storage means, in the case of a prohibition pattern, a storage method for storing an optimum equalization amount for the prohibition pattern is adopted. The effect on subsequent equalization can be reduced.

(Embodiment 4) FIG. 6 is a diagram showing the creation of an equalization amount stored in the equalization amount storage means of a 4-tap BT equalizer in ping-pong transmission using a digital subscriber line according to a fourth embodiment of the present invention. FIG. 3 shows a block diagram of a data capturing unit.

In FIG. 6, reference numeral 1 denotes signal input means for sampling an input signal and converting the input signal into digital data.
Numeral 3 denotes data determining means for determining the data sampled by the signal input means 1 into three values of "1", "0", and "-1", and determining the three-valued determination result as "01", "
Output is 00 "," 10 ". 18 is an equalization amount storage means, which is an equalization amount table in which the equalization amount for equalizing input signal data for each combination of past ternary determination results is stored in advance. Reference numeral 16 denotes a data capturing unit that detects the output of the signal input unit 1 as the equalized data h1, h2, h3, and h4 based on the determination result of the data determining unit 3. Here, the first tap is detected. The equalized data h1 to be equalized is
This is the output data sampled by the signal input unit 1 at the last "0" when the binary determination result is determined to be "000010". Similarly, the equalization data at the second tap is
The last “0” when the binary determination result is “000100”, the last “0” when the binary determination result is “001000”,
The equalization data at the fourth tap has a binary determination result of “0100”
The output of the signal input means 1 at the last "0" when it is determined to be "00" is equalized data at each tap. The binary determination result here is "
“0” represents the result of determination as “0”, and “1” and “−1” represent the result of determination as “1.” Reference numeral 17 denotes accumulated data creation means, which uses the equalized data detected by the data acquisition means 16. hand,
The equalization amount is calculated for all past ternary determination result patterns and stored in the equalization amount accumulation means 18. Reference numeral 26 denotes a signal data storage unit that stores all the equalized data for one burst in the memory. 27 is a signal data selecting means for selecting, from the equalized data held in the signal data storing means 26, equalized data excluding signal distortion due to inter-symbol interference of frame bits due to a training signal specific to burst transmission. I do. Numeral 28 denotes an equalization data calculation means for performing an average calculation of the equalization data selected by the signal data selection means 27 and using the calculation result as equalization data for creating an equalization table.

The operation of the decision feedback equalizer configured as described above will be described with reference to FIG.

When a signal is input from the transmission line, the input signal is sampled in the signal input means 1 and converted into digital data. The data determination means 3 converts the data equalized by the signal input means 1 into "1", "0", "-".
The ternary value is determined to be 1 ", and the three-valued determination result is output as binary numbers" 01 "," 00 ", and" 10 ", respectively. Is used to determine a past binary determination result pattern, and if the pattern is a pattern for detecting equalized data, the digital data sampled by the signal input means 1 is fetched as equalized data. At 26, the equalized data h1, h2, h3, h
The equalization data is accumulated in the memory for each of the patterns No. 4 and No. 4. When one burst of the four equalized data is accumulated, the signal data selecting unit 27 extracts the equalized data excluding several bits of the equalized data from the head of the burst reception period. The equalization data calculation means 28 performs an averaging operation of the equalization data extracted by the signal data selection means 27, and uses the result as equalization data of this equalizer.
Next, the accumulated data creation means 17 outputs the averaged data by the data acquisition means 16, that is, the equalized data calculation means 28.
An equalization table is constructed based on the equalization data for the taps, and the equalization amount based on the equalization data detected as a result is stored in the equalization amount accumulation means 18.

[0046]

As described above, according to the present invention, when this decision period type equalizer is realized in a BT equalizer that performs a burst signal equalization process, the BT echo amount can be determined by referring to a table based on past determination results. Can be compensated, so that the BT equalization processing time can be shortened. This makes it possible to realize a BT equalizer by software processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a decision feedback equalizer according to a conventional example of the present invention.

FIG. 2 is an explanatory diagram of an equalization process of a decision feedback equalizer in a conventional example of the present invention.

FIG. 3 is a block diagram of a decision feedback equalizer according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an address generation method of the decision feedback equalizer according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a decision feedback equalizer according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a decision feedback equalizer according to a fourth embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 signal input means 2 signal equalization means 3 data determination means 4 delay device 5 delay device 6 delay device 7 delay device 8 multiplier 9 multiplier 10 multiplier 11 multiplier 12 adder 13 signal equalization means input 14 signal equalization Means output 15 Mode switching means 16 Data acquisition means 17 Accumulated data creation means 18 Equalization amount accumulation means 19 Data judgment means 20 Equalization amount selection means 21 Previous 8-bit address 22 Output result of data judgment means 23 Current 8-bit address 24 accumulation correction means 25 accumulation data creation means 26 signal data accumulation means 27 signal data selection means 28 equalization data calculation means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-102885 (JP, A) JP-A-5-102886 (JP, A) JP-A-5-22194 (JP, A) JP-A-7-102 141776 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04B 3/06 H04B 3/10

Claims (8)

(57) [Claims] 1. After a training mode of an isolated pulse,
In a training mode of transmission for transition to a normal communication mode, a signal input unit that samples an input signal and converts the input signal into digital data, determines the digital data converted by the signal input unit, and outputs a result of the determination. Data determining means, data capturing means for capturing digital data of the signal input means as equalized data of an equalizer based on a past determination result of the data determining means, and data equalizing data captured by the data capturing means. Means for calculating and outputting an equalization amount corresponding to all addresses generated by the equalization amount selection means; and an equalization amount storage for storing the equalization amount created by the storage data creation means. Means for storing the digital data converted by the signal input means in the communication mode in the equalization amount. Signal equalizing means for performing equalization processing with the equalization amount output from the stage, data determining means for determining data equalized by the signal equalizing means, and outputting the determination result; and A decision feedback equalizer characterized by comprising: an equalization amount selecting means for holding an past judgment result of the means and generating an address for reading the equalization amount from the equalization amount accumulating means. . 2. A method according to claim 1, further comprising: detecting an equalization residue in said signal equalization processing means based on a determination result output from said data determination means and equalized data equalized by said signal equalization means; An accumulation correcting means for correcting the equalization data for each tap of the equalizer based on the residual, and an equalization amount of the input signal data calculated by the equalization data corrected by the accumulation correction means; 2. A decision feedback equalizer according to claim 1, further comprising: stored data creating means for storing in said means. 3. In ping-pong transmission, reception data storage means for storing, in a memory, equalized data that has been equalized by the signal equalization means during a reception period, and the equalization data held during a transmission period. 3. The determination according to claim 2, further comprising: the accumulation correction unit configured to detect a residual equalization from data; and the accumulation data creation unit configured to calculate an equalization amount to be stored in the equalization amount accumulation unit. Feedback type equalizer. 4. The accumulation correcting means judges whether the correction of the equalization amount is performed on the positive side or the negative side based on the sign of the remaining equalization, and performs equalization on the current equalization data. 3. The decision feedback equalizer according to claim 2, having a function of adding a fixed amount if the remainder is on the positive side and subtracting a fixed amount on the negative side to correct the equalized data. 5. The accumulation correction means has a function of multiplying the equalization residue by a constant coefficient and adding the multiplication result to the current equalization data to correct the equalization data. The decision feedback equalizer according to claim 2. 6. The equalization amount accumulating means stores an equalization amount for compensating by determining that the forbidden pattern is erroneous when the forbidden pattern is detected by the equalization amount selecting means. The decision feedback equalizer according to claim 1, wherein: 7. A ping-pong transmission wherein the data fetching means performs a timing synchronization process before fetching the equalized data, thereby fetching the equalized data with a small bit synchronization deviation of the sampling. The decision feedback equalizer according to claim 1. 8. A ping-pong transmission, wherein the data fetching means stores signal data of a received signal for one burst in a memory, and a training signal specific to burst transmission from the signal data storage means. A signal data selecting means for selecting received data excluding signal distortion caused by inter-symbol interference of frame bits, and an average operation of the signal data selected by the signal data selecting means, and the operation result is referred to as equalized data. 2. The decision feedback equalizer according to claim 1, further comprising: