JPH057128A - Equalizer - Google Patents

Abstract

PURPOSE:To realize the equalization system in which the S/N is not deteriorated even on the condition that an echo wave arrives faster than a main signal while being at almost the same level as that of the main signal in a multiple propagation path. CONSTITUTION:A branchmetric generator 1 obtains and outputs a branchmetric based on a reception signal, an estimate object signal and an equalization object signal. A Viterbi decoder 2 receives the branchmetric, applies Viterbi decoding thereto and outputs an equalization tentative discrimination series. An estimate object signal generator 3 outputs an estimate object signal. An estimate object signal generator 4 receives an equalization tentative discrimination series and outputs an equalization signal. Thus, the equalization of a precurser component having not been realized so far is realized by the discrimination feedback equalizer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer for equalizing a digitized signal, and more particularly to an equalizer for estimating and equalizing a precursor component in an impulse response signal.

[0002]

2. Description of the Related Art In a wireless transmission path of a data signal, when there are a plurality of propagation paths, some echo signals in addition to the main signal are added on the receiving side. Therefore, in the worst case when echo signals with different propagation delay times are added,
As shown in FIG. 22, the signal component attenuates at a certain frequency.

When this signal is attempted to be equalized, the frequency characteristic of the equalizer shows a characteristic that the equalization gain becomes large at the frequency where the signal component is attenuated, as shown in FIG. If this equalization characteristic is realized by a transversal type equalizer, the noise component is also amplified at the same time, and the signal-to-noise ratio after equalization deteriorates.

As a method of avoiding this deterioration, there is a decision feedback equalizer. FIG. 17 shows an embodiment of the decision feedback equalizer.
Shown in. Distorted digital binary signal (0.
I will explain using 1). The determination signal determined so far is stored in each register 58. Judge 55
Outputs “0” to the computing unit 56. In the calculator 57,
The output of each register 58 is weighted by multiplying the coefficient to generate an estimated signal for the received signal. Subtractor 5
In 4, the difference signal is obtained by subtracting the outputs of the calculator 56 and each calculator 57 from the received signal. This difference signal is "0"
Will be the difference signal when the reception is assumed. Next, the judging device 5
5 outputs "1" to the computing unit 56, and similarly, a difference signal under the assumption that "1" is received is obtained. After that, the determiner 5
The difference signal when "0" is assumed in 5 and the difference signal when "1" is assumed are compared, and the one having a smaller value is output as the determination signal. On the other hand, the difference signal is output from the decision unit 55 to the operation unit 5
6 and each arithmetic unit 57, and the coefficient is corrected so that optimum weighting can be performed. By these operations, the received signal is equalized.

As described above, the decision feedback equalizer performs equalization by using the decision result of the received signal. Since the signal of the determination result does not include a noise component, it has the frequency characteristic shown in FIG. 23 for the equalization of the signal component, but does not have the frequency characteristic for the noise component. Therefore, it is possible to prevent the deterioration of the signal-to-noise ratio caused by the amplification of the noise component as in the transversal equalizer.

However, the decision feedback equalizer cannot equalize the precursor component that reaches before the center component in the impulse response is received because the decision feedback equalizer performs equalization using the decision signal. This means that the decision feedback equalizer does not have an equalizing ability for an echo signal that arrives earlier than the main signal in time.

Therefore, as shown in FIG. 18, a transversal type equalizer 59 is used for a precursor component that cannot be equalized by the decision feedback type equalizer, and a decision feedback type equalizer is used for the postcursor component. A method of performing equalization at 60 is used.

[0008]

In the decision feedback type equalizer,
In order to equalize the signal in which the echo signal is received earlier in time than the main signal, the judgment value of the main signal must be known when the echo signal is received. However, it is impossible to realize this with a conventional decision feedback equalizer. Therefore, in the conventional equalization method, for equalization of the received signal in which the echo signal arrives earlier than the main signal in time,
We have no choice but to rely on a transversal equalizer. Therefore, when the characteristics of the transversal type equalizer are as shown in FIG. 23, the equalization characteristics are deteriorated due to the amplification of the noise component.

[0009]

According to a first aspect of the invention, a digital M-value signal (M is an integer of 2 or more) causes intersymbol interference by extending a transmission path impulse response to m (m is an integer of 1 or more) symbols. Received reception signals and M ⁿ estimation candidate signals for estimation for n (n is an integer of 1 or more and m or less) symbols including at least a precursor component of the impulse response of the received signals, and (m− except the first one symbol of the n symbols for performing equalization n) symbols (n-1) consists of the number of states of symbols M ^{n -} M ⁿ for ^one received signal from the equalization candidate signal a branch metric generator for outputting seek number of branch metrics; enter the M ^n-number of the branch metrics from the branch metric generator performs Viterbi decoding, equalization dexterity outputs the received estimated signal And M ^{n -} Viterbi decoder which outputs a ¹ consists single equalization tentative decision sequence and; M ^n-number of the estimated candidate signal output to the branch metric generator estimation candidate signal generator and, the Viterbi decoder To M
and characterized in that it is composed of a ^single equalization candidate signal generator of the equalization candidate signal output to the branch metric generator ^{- n -1} amino inputs the equalization tentative decision sequence M ⁿ To do.

The second invention is that the transmitter impulse response is m.
(M is an integer greater than or equal to 1) The digital M-value signal (M is an integer greater than or equal to 2) is interleaved with a received signal and the impulse response of the received signal has at least a precursor component n (n). Is an integer from 1 to m)
M ⁿ estimated candidate signals for estimating symbols and ⁿ for performing (mn) symbol equalization.
A branch metric generator for calculating and outputting M ⁿ branch metrics for the received signal from M ^{n -1} equalization candidate signals consisting of the number of (n-1) symbol states excluding the first symbol of the symbols; A modified signal generator for outputting a modified signal from the received signal, modified estimated signal and modified equalized signal; M ⁿ from the branch metric generator
A Viterbi decoder that inputs the number of branch metrics, performs Viterbi decoding, uses a received estimation signal consisting of one M-value symbol as an output for an equalizer, and outputs an equalization provisional decision sequence consisting of M ^{n -1} A shift register that receives the received estimation signal of the Viterbi decoder for m symbols, outputs a signal for M value (mn) symbols therein, and outputs a signal for M value n symbols; M ^{The n} estimated candidate signals are output to the branch metric generator, and the corrected estimated signal is output to the corrected signal generator while receiving the signals of the M-value n symbols from the shift register and the correction. inputting the corrected signal from the signal generator, the estimated candidate signal generator for correcting the estimated candidate signal; the M ⁿ from Viterbi decoder ^- enter ^one of the equalization tentative decision sequence M ^{n - one} of the Outputting a candidate signal for equalization to the branch metric generator, receiving a signal for the M-value (mn) symbols from the shift register, outputting the modified equalization signal to the modified signal generator, and the modified signal. An equalization candidate signal generator configured to receive the correction signal from the signal generator and correct the equalization candidate signal.

[0011]

As a method of not amplifying the noise component, which is a feature of the decision feedback equalizer, and equalizing the precursor component in the transmission path impulse response, estimation for all possible states of the precursor component and the center component The candidate signal is generated based on the estimated transmission path characteristics, the branch metric is calculated from the received signal and each estimated candidate signal, and the Viterbi decoding method is used to determine which estimated candidate signal is the most likely for the received signal. Conceivable. That is, since there is a constraint condition in the temporal transition of the states of the precursor component and the center component, it is possible to perform equalization using the Viterbi decoding method by using the difference between the received signal and the estimated candidate signal as the branch metric.

Further, in each state at a certain time on the trellis transition diagram in the Viterbi algorithm, the state of the postcursor component corresponding to each state is uniquely determined by tracing the survivor path leading to each state. An equalized signal for equalizing the postcursor component can be generated at the same time.

Therefore, when equalizing both the precursor component and the postcursor component, the estimation candidate signal for equalizing the received signal, the precursor component, and the center component and the equalization for equalizing the postcursor component are equalized. By obtaining the branch metric from the signal, further obtaining the path metric by the Viterbi decoder, and then performing the traceback, the most probable estimated value for the received signal can be obtained as the received signal determination value. This equalizer is described in claim 1 of the present invention.

Further, the estimated candidate signal and the equalized signal are temporally modified with respect to the received signal by sequentially correcting the estimated channel characteristic for obtaining the estimated candidate signal and the equalized signal using the judgment value of the Viterbi decoder and the received signal. It is possible to realize an adaptive automatic equalizer that follows changes. This adaptive automatic equalizer is described in claim 2 of the present invention.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of claim 1 of the present invention. It is a binary signal consisting of two types of distorted (0.1) as a received signal to be equalized. The precursor component in the impulse response is 2 symbols and the postcursor component is 3 symbols, and the estimation is made for 3 symbols of the precursor component and the center component. Shall be performed. First, the branch metric generator 1 will be explained based on a time division method in which each branch metric for one received signal is obtained one by one in time.

The input signal is a branch metric generator 1
Is input to. In the branch metric generator 1, FIG.
As shown in, the adder 11 adds the estimation candidate signal from the estimation candidate signal generator 3 and the equalization candidate signal from the equalization candidate signal generator 4, and outputs the addition result to the subtractor 12. The subtracter 12 subtracts the output signal of the adder 11 from the received signal and outputs the subtracted signal to the square operation register 13. In the square calculation register 13, the output signal of the subtracter 12 is squared and temporarily stored in a register in the square calculation register 13 as a branch metric.

These operations are eight (ie, the total number of branch metrics corresponding to "000" to "111" each consisting of two symbols of the precursor component and one symbol of the center component) and four (4) Since one equalization candidate signal corresponds to two estimated candidate signals, eight equalization candidate signals correspond to four equalization candidate signals). The calculation result is stored in all the square calculation registers 13. The output of each square operation register 13 is output to the Viterbi decoder 2 as a branch metric. FIG. 19 shows the timing at which the branch metric is stored in each square operation register 13.

The received signal is R and the eight estimated candidate signals are X _0.
To X ₇ and four equalization candidate signals from Y ₀ to Y ₃ , branch metrics e ₀ to e ₇ are obtained as follows.

E ₀ = (R-X ₀ -Y ₀ ) ² e ₁ = (R-X ₁ -Y ₀ ) ² e ₂ = (R-X ₂ -Y ₁ ) ² e ₃ = (R-X _{3 ^{-Y 1) 2 e 4 = (}} R-X 4 -Y 2) 2 e 5 = (R-X 5 -Y 2) 2 e 6 = (R-X 6 -Y 3) 2 e 7 = (R- In the X ₇ -Y ₃ ) ² Viterbi decoder 2, the branch metric from the branch metric generator 1 is first added to the adder 1 as shown in FIG.
Input to 5. On the other hand, each register 14 stores the value of each path metric. Each adder 15 adds the value of each branch metric and the value of each path metric. Each comparator 16 compares the output signals from the adder 15, selects a signal having a small value, stores it in the register 14 as a new path metric, and stores the impulse response corresponding to the branch metric. The state value is input from the shift register 17, the input from the shift register 17 is selected according to the selection of the branch metric, and the selection result is output to the shift register 17 again. Each shift register 17 outputs to the equalization candidate signal generator 4 an equalization provisional decision sequence for determining an equalization candidate signal when the branch metric generator 1 obtains a branch metric. In the traceback in Viterbi decoding, first, the selector 18 finds the smallest value among the path metrics stored in each register 14, and the past value stored in the corresponding shift register 17 is used as the reception estimation signal. Output as.

Specific examples of these operations will be described with reference to FIGS. 20 and 21.

FIG. 20 is a trellis transition diagram of the Viterbi decoder 2. E ₀ in FIG. _{20, 0} (the beginning of the _zero index ₀ after. Indicating the time indicates the state of the branch metric) from e _{0, 7} until the precursor component and the center component of the impulse response of the received signal It is a branch metric corresponding to "111" from the state "000" (the right two bits correspond to the precursor component and the left one bit corresponds to the center component). S _{0, 0 (0} at the beginning of the subscript represents the time, ₀ indicates the state of the path metric after) is the path metric from to S _{0, 3.} Each path metric corresponds to the postcursor component (any one of "000" to "111") of the impulse response determined by the surviving path, and is used as an equalization candidate signal generator as an equalization temporary decision sequence. 4 is output.

A state of temporal change in Viterbi decoding will be described with reference to FIG.

[0024] First of all, S from the path metric S _{0, 0}
Up to _{0 and 3} , the post-cursor status is "01
It is assumed that 0 "," 011 "," 011 ", and" 010 "correspond to each other. (The time sequence of the three symbols in the postcursor state is the direction in which time progresses from right to left.) First, e
_{When 0, 0} and e _{0, 1} are obtained, the postcursor state “010” of S _{0, 0} is output from the Viterbi decoder 2 as an equalization provisional decision sequence. Therefore, as the estimated candidate signal corresponding to e _{0, 0} , the state of the precursor component is “00” and the state of the center component is “00” from the estimated candidate signal generator 3.
The value at the time of 0 ”is output from the equalization candidate signal generator 4 when the state of the postcursor component is at“ 010 ”. Similarly, when e _{0, 1} is obtained, the value of the precursor component is calculated. The value when the state is "01" and the state of the center component is "0"
The equalization candidate signal generator 4 outputs the value when the state of the postcursor component is "010". Hereinafter _, the equalization candidate signals from the equalization candidate signal generator 4 from e _0,2 to e 0,7 have the postcursor component states of “011,” 01.
1 "," 011 "," 011 "," 010 "," 01 "
It becomes the value at the time of 0 ".

[0025] When determining the S _{1, 0 is,} S _{0, 0} + e
_{0, 0} and S _{0, 2} + e _{0, 4} are compared, and the smaller one is selected as S _{1, 0} . Here, S _{0, 0} + e _{0, 0}
If one is selected, _since the center component of e _{0, 0} is assumed to be “0” in the state of the postcursor corresponding to S _{1, 0} , input “0” to “010” from the right, By shifting to the left, it becomes "100". Similarly, if S _{1, 1} , S _{1, 2} , S _{1, 3} are determined,
S _{0, 0} + e _{0, 1} , S _{0, 3} + e _{0, 6} , S _{0, 1} +
By selecting e _{0, 3} , the post-cursor states in the respective path metrics are “011,” 01
1, "010" to "100", "101", "110"
Becomes

Similarly, the path metric and the branch metric are calculated.

On the other hand, traceback is performed as follows. Here, assuming that traceback is performed for 8 symbols, when path metrics S _{8, 0} to S _{8, 3} are obtained, the selector 18 selects the smallest value among S _{8, 0} to S _{8, 3.} Select a path metric that has and perform a traceback. The traceback can be realized by extracting the past value stored in the shift register 17.

It is assumed that S _{0, 3} is confirmed by traceback. Since the state of the postcursor corresponding to S _{0, 3} is “010”, “0” is output as the reception estimated value. Similarly, S _{9, 2} , S _{1 0, 0} , S _{1 1, 1}
When is selected by the selector 18, the traceback outputs the estimated reception values “1”, “1”, “0” corresponding to S _{1, 2} , S _{2, 0} , S _{3, 3} . .

As shown in FIG. 5, the estimation candidate signal generator 3 outputs the output of the counter 19 which outputs 8 kinds of binary signals of 3 bits to the multiplication adder 20. That is, when calculating the branch metric e _{0, 0} ,
When 000 ”determines e _{0, 1} ,“ 001 ”is output to the multiplication adder 20. In the coefficient generator 21, the coefficients for weighting each of the 3-bit signals output from the counter 19 are multiplied and added. Output to the container 20.

In the multiplication adder 20, the 3-bit signal from the counter 19 and the output signal from the coefficient generator 21 are respectively multiplied and added, and output as an estimation candidate signal.

The outputs X ₀ to X ₇ of the multiplication adder 20 when the 3 bits of the output signal from the counter 19 sequentially change from “000” to “111” are the output signals of the coefficient generator 21 (c ₀ , If c ₁ and c ₂ ) are satisfied, the following is obtained. X ₀ = 0 X ₁ = c ₀ X ₂ = c ₁ X ₃ = c ₀ + c ₁ X ₄ = c ₂ X ₅ = c ₀ + c ₂ X ₆ = c ₁ + c ₂ X ₇ = c ₀ + c ₁ + c ₂ etc. In the equalization candidate signal generator 4, as shown in FIG. 6, one of four equalization provisional decision sequences of 3 bits output from the Viterbi decoder 2 is selected by the selector 22, and the multiplication adder 23 is selected. 3 bit signal from selector 22 and coefficient generator 2
The output signals from 4 are respectively multiplied and added to be output as an equalization candidate signal.

The output signal of the coefficient generator 24 is (c ₃ ,
c ₄ , c ₅ ) and the path metric S of the Viterbi equalizer 2
_{0, 0} , S _{0, 1} , S _{0, 2} , S _{0, 3} are set to (g _{0, 0} , g _{0, 1} , g _{0, 2} ), (g _{0, 0} , g _{0, 1} , g _{0, 2} ),
_{1, 0} , g _{1, 1} , g _{1, 2} ), (g _{2, 0} ,
g _{2, 1} , g _{2, 2} ), (g _{3, 0} , g _{3, 1} , g
_{3 and 2} ), the equalization candidate signals Y ₀ to Y ₃ are obtained as follows.

Y ₀ = g _{0, 0} × c 4 + g _{0, 1} × c 5 + g _{0, 2} × c 6 Y 1 = g _{1, 0} × c 4 + g _{1, 1} × c 5 + g _{1, 2} × c 6 Y 2 = g _{2, 0} × c4 + g2 _{, 1} xc5 + g2 _{, 2} xc6 Y3 = g3 _{, 0} xc4 + g3 _{, 1} xc5 + g3 _{, 2} xc6 By the above operation, equalization including the precursor component of the received signal can be performed. Like

Next, a parallel processing method for simultaneously obtaining each branch metric for one received signal will be described.

In the branch metric generator 1, as shown in FIG. 7, eight types of estimated candidate signals are generated from the estimated candidate signal generator 3, and four types of equalized candidate signals are equalized candidate signal generator 4.
Is input from each adder 25 and added by each adder 25. The subtractor 26 subtracts the output signal of the adder 25 from the received signal and outputs the subtracted signal to the square calculation register 27.

The square operator 27 squares the input signal to obtain the branch metric, and the square operator 2
It is stored in the register in 7.

The operation of the Viterbi equalizer 2 is the same as the method of obtaining the branch metric by time division.

In the estimated candidate signal generator 3, as shown in FIG. 8, the estimated candidate signals X ₀ to X ₇ are estimated candidate signal calculators 2.
At 8, the signals from the coefficient generator 29 are received, and 8 signals are simultaneously obtained.

As shown in FIG. 9, the equalization candidate signal generator 4 generates the equalization candidate signals Y ₀ to Y ₃ from the equalization provisional decision sequence from the Viterbi decoder 2 and the output signal from the coefficient generator 31. By multiplying and adding by the multiplying adder 30, four are obtained at the same time.

Here, the equalization of 6 symbols of 2 symbols of the precursor component and 3 symbols of the postcursor component has been described, but the present invention is not limited to this, and the same applies to distortion of any length. You can

On the other hand, FIG. 2 shows an embodiment of claim 2 of the present invention.

The received signal to be equalized has the same structure as in the explanation of FIG. First, the branch metric generator 5 temporally sets each branch metric for one received signal to 1
The explanation is based on the time-divisional method, which is called for.

The input signal is a branch metric generator 5
Are input to the Viterbi decoder 7 and eight branch metrics are output to the Viterbi decoder 7.

On the other hand, the received signal is further processed by the modified signal generator 6
Is input to. A configuration diagram of the correction signal generator 6 is shown in FIG. First, the received signal is input to the delay device 32 and delayed. This is to match the timings of the received estimated signal and the received signal of the Viterbi decoder 7 used when correcting the estimated candidate signal and the equalization candidate signal. Viterbi decoder 7
Then, if the traceback is performed for 8 symbols, for example, a delay of 10 symbols including 2 symbols of the precursor component is performed. In the adder 33, the modified estimated signal from the estimation candidate signal generator 9 and the equalization candidate signal generator 10
The corrected equalization signal from is added and output to the subtractor 34.
In the subtractor 34, the output signal of the delay device 32 is added to the adder 33.
Is subtracted and output as a correction signal to the estimation candidate signal generator 9 and the equalization candidate signal generator 10. When the output signal of the delay device 32 is P, the modified estimation signal is U, and the modified equalization signal is V, the modified signal ε is obtained as follows.

The ε = P-U-V Viterbi decoder 7 receives the branch metric from the branch metric generator 5 and outputs an equalization provisional decision sequence and a received estimation signal.

On the other hand, when performing traceback, S
_{When 0 and 3} are determined, the reception estimated value "0" corresponding to S _{0 and 3} is output not only to the outside but also to the shift register. Similarly, S _{1, 2} , S _{2, 0} , S
Estimated reception values "1", "1", "0" corresponding to _{3, 3}
Is also output to the outside and the shift register.

FIG. 11 shows the configuration of the shift register 8 to which the reception estimation signal obtained by the Viterbi decoder 7 is input.
In the shift register 8, six registers 35 are connected in series, and each register 35 outputs a 3-bit parallel signal to the estimation candidate signal generator 9 and the equalization candidate signal generator 10.

That is, the value of the shift register is "010".
When it is 110 ″, the upper 3 bits “010” are output to the estimation candidate signal generator 9 and the lower 3 bits “010” are output to the equalization candidate signal generator 10.

As shown in FIG. 12, the estimation candidate signal generator 9 multiplies the output of the counter 36, which outputs 8 types of binary signals of 3 bits, and the output of the coefficient generator 38, by the multiplication adder 37, and The estimated candidate signals are added and output.

On the other hand, the corrected estimated signal is multiplied by the adder 39 to generate the 3-bit signal from the shift register 8 and the coefficient generator 38.
Is calculated by multiplying and adding the output signals from. The signals from the shift register 8 are (b ₀ , b ₁ ,
b ₂ ), the output U from the multiplication adder 39 is obtained as follows.

U = b ₀ × c ₀ + b ₁ × c ₁ + b ₂ × c ₂ The content of the coefficient generator 38 is modified by the modification signal from the modification signal generator 6 and the signal from the shift register 8. . The following maximum gradient method is an example of the correction algorithm. Here, ε is a correction signal, and μ is a correction coefficient that determines the speed of correction.

C ₀ ← c ₀ + μ × ε × b ₀ c ₁ ← c ₁ + μ × ε × b ₁ c ₂ ← c ₂ + μ × ε × b ₂ A block diagram of this algorithm is shown in FIG. The correction signal is multiplied by the correction coefficient in the coefficient multiplier 44, and further multiplied by the signal from the shift register 8 in the multiplier 45. The output signal of the multiplier 45 is added to the output signal of the register 46 in which the coefficient is stored in the adder 47, and is stored in the register 46 as a new coefficient. Further, the timing of performing this correction is shown in FIG.

In the equalization candidate signal generator 10, as shown in FIG. 13, the selector 40 selects one from the four equalization provisional decision sequences output from the Viterbi decoder 7, and the multiplication adder 4
At 1, the output of the coefficient generator 42 is multiplied and added to obtain an equalization candidate signal, which is output.

On the other hand, the 3-bit signal from the shift register 8 and the output signal from the coefficient generator 42 are multiplied and added by the multiplication adder 43 and output as a corrected equalization signal. The signals from the shift register 8 are (b ₃ , b ₄ ,
b ₅ ), the output V from the multiplication adder 43 is obtained as follows.

V = b ₃ × c ₃ + b ₄ × c ₄ + b ₅ × c ₅ The content of the coefficient generator 42 is modified by the modification signal from the modification signal generator 6 and the signal from the shift register 8. . The following maximum gradient method is an example of the correction algorithm. Here, ε is a correction signal, and μ is a correction coefficient that determines the speed of correction.

C ₃ ← c ₃ + μ × ε × b ₃ c ₄ ← c ₄ + μ × ε × b ₄ c ₅ ← c ₅ + μ × ε × b _{5 By the} above operation, the precursor component of the received signal is included, etc. Can be realized.

Next, a parallel processing method for simultaneously obtaining each branch metric for one received signal will be described.

The configuration of the branch metric generator 5 is the same as that shown in FIG.

The method of obtaining the corrected estimated signal and the corrected equalized signal is the same as the method of obtaining the branch metric by time division.

The operations of the Viterbi equalizer 7 and the shift register 8 are the same as the method of obtaining the branch metric by time division.

In the estimation candidate signal generator 9, as shown in FIG. 15, eight estimation candidate signals X ₀ to X ₇ are obtained at the same time by the estimation candidate signal calculator 48 receiving the signal from the coefficient generator 49.

The corrected estimation signal is obtained by the multiplication adder 50 from the 3-bit signal from the shift register 8 and the signal from the coefficient generator 49. Assuming that the signal from the shift register 8 is (b ₀ , b ₁ , b ₂ ), the output signal U from the multiplication adder 50 is obtained as follows.

U = b ₀ × c ₀ + b ₁ × c ₁ + b ₂ × c _{2 The} coefficient correction method in the coefficient generator 49 is the same as the method for obtaining the branch metric by time division.

As shown in FIG. 16, the equalization candidate signal generator 10 compares the equalization candidate signals Y ₀ to Y ₃ with the temporary equalization decision sequence from the Viterbi decoder 7 and the output signal from the coefficient generator 52. By multiplying and adding in the multiplying adder 51, four can be obtained at the same time.

The corrected equalized signal is obtained by the multiplication adder 53 from the 3-bit signal from the shift register 8 and the signal from the coefficient generator 52. When the signals from the shift register 8 are (b ₃ , b ₄ , b ₅ ), the output signal V from the multiplication adder 53 is obtained as follows.

V = b ₃ × c ₀ + b ₄ × c ₁ + b ₅ × c _{2 The} method of correcting the coefficient in the coefficient generator 62 is the same as the method of obtaining the branch metric by time division.

[0067]

As described above, by combining the decision feedback equalizer with the Viterbi decoder for estimating the precursor component of the received signal, not only the delayed echo signal generated by multiple propagation but also the advanced echo signal is generated. It becomes possible to equalize without increasing the noise.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of claim 1 in the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of claim 2 in the present invention.

FIG. 3 is an explanatory diagram showing an embodiment of a branch metric generator when it is configured by a method of obtaining eight branch metrics in time division in claim 1 of the present invention.

FIG. 4 is an explanatory diagram showing an embodiment of a Viterbi decoder that equalizes a binary signal in which a precursor component of an impulse response is 2 symbols and a center component is 1 symbol according to claim 1 of the present invention.

FIG. 5 is an explanatory diagram showing an embodiment of an estimated candidate signal generator when it is configured by a method of obtaining eight branch metrics in time division in claim 1 of the present invention.

FIG. 6 is an explanatory diagram showing an embodiment of an equalization candidate signal generator when the eight branch metrics according to claim 1 of the present invention are configured by a method of time division division.

FIG. 7 is an explanatory diagram showing an embodiment of a branch metric generator when it is configured by a method of simultaneously obtaining eight branch metrics in parallel according to claim 1 of the present invention.

FIG. 8 is an explanatory diagram showing an embodiment of an estimated candidate signal generator when it is configured by a method of simultaneously obtaining eight branch metrics in parallel according to claim 1 of the present invention.

FIG. 9 is an explanatory diagram showing an embodiment of an equalization candidate signal generator when it is configured by a method of simultaneously obtaining eight branch metrics in parallel according to claim 1 of the present invention.

FIG. 10 is an explanatory diagram showing an embodiment of a modified signal generator according to claim 2 of the present invention.

FIG. 11 is an explanatory diagram showing one embodiment of the shift register according to claim 2 of the present invention.

FIG. 12 is an explanatory diagram showing an embodiment of an estimated candidate signal generator when it is configured by a method of obtaining eight branch metrics by time division in claim 2 of the present invention.

FIG. 13 is an explanatory diagram showing an embodiment of an equalization candidate signal generator when it is configured by a method of obtaining eight branch metrics by time division in claim 2 of the present invention.

FIG. 14 is an explanatory diagram showing an embodiment of a coefficient generator in the estimation candidate signal generator and the equalization candidate signal generator in claim 2 of the present invention.

FIG. 15 is an explanatory diagram showing an embodiment of an estimated candidate signal generator when it is configured by a method of simultaneously obtaining eight branch metrics in parallel according to claim 2 of the present invention.

FIG. 16 is an explanatory diagram showing an embodiment of an equalization candidate signal generator when it is configured by a method of simultaneously obtaining eight branch metrics in parallel according to claim 2 of the present invention.

FIG. 17 is an explanatory diagram showing an embodiment of a decision feedback equalizer.

FIG. 18 is an explanatory diagram showing an example of a system in which a conventional transversal type equalizer and a decision feedback type equalizer are combined.

19 is an explanatory diagram showing a temporal flow of coefficients in the branch branch metric generation and coefficient generator in the branch metric generator shown in FIG. 3;

20 is an explanatory diagram showing a state transition diagram of the Viterbi decoder in FIG. 5. FIG.

21 is an explanatory diagram showing the operation principle of the Viterbi decoder based on the state transition diagram of FIG. 11. FIG.

FIG. 22 is a diagram showing the frequency characteristic on the receiving side when the amplitude of the main signal and the amplitude of the echo signal become substantially equal.

23 is a diagram showing frequency characteristics of the equalizer when the signal having the frequency characteristics of FIG. 12 is equalized by the transversal type equalizer.

[Explanation of symbols]

1 Branch metric generator 2 Viterbi decoder 3 Estimated candidate signal generator 4 Equalization candidate signal generator 5 Branch metric generator 6 Modified signal generator 7 Viterbi decoder 8 shift registers 9 Estimated candidate signal generator 10 Equalization candidate signal generator 11 adder 12 Subtractor 13 Square operation register 14 registers 15 adder 16 Comparator 17 shift register 18 selector 19 counter 20 Multiplier adder 21 coefficient generator 22 Selector 23 Multiply adder 24 coefficient generator 25 adder 26 Subtractor 27 Square arithmetic register 28 Estimated candidate signal calculator 29 coefficient generator 30 multiplication adder 31 coefficient generator 32 delay device 33 adder 34 Subtractor 35 registers 36 counter 37 Multiply adder 38 coefficient generator 39 Multiply adder 40 selector 41 Multiply adder 42 coefficient generator 43 Multiplier adder 44 coefficient multiplier 45 multiplier 46 registers 47 adder 48 Estimated candidate signal calculator 49 coefficient generator 50 multiplication adder 51 Multiply adder 52 coefficient generator 53 Multiply adder 54 Subtractor 55 Judgment device 56 calculator 57 calculator 58 registers 59 Transversal Equalizer 60 Decision feedback equalizer

Claims (2)

[Claims] 1. A received signal in which a digital M-value signal (M is an integer of 2 or more) has received intersymbol interference due to the transmission path impulse response extending to m (m is an integer of 1 or more) symbols, and the received signal. M ⁿ estimated candidate signals for estimation with respect to n (n is an integer of 1 or more and m or less) symbols including at least a precursor component of the impulse response and (m−
except the first one symbol of the n symbols for performing equalization n) symbols (n-1) consists of the number of states of symbols M ^{n -} M ⁿ for ^one received signal from the equalization candidate signal A branch metric generator that calculates and outputs M ⁿ branch metrics; M ⁿ branch metrics from the branch metric generators are input, Viterbi decoding is performed, and a received estimation signal is used as an equalizer output, and M ^{n -} Viterbi decoder which outputs a ¹ consists single equalization tentative decision sequence and; M ^n-number of said outputs the estimated candidate signal to the branch metric generator estimation candidate signal generator and; M from the Viterbi decoder ^{n -} etc., characterized in that it is composed of a ^single equalization candidate signal generator of the equalization candidate signal output to the branch metric generator ^{- one} inputs the equalization tentative decision sequence M ⁿ Vessel. 2. A received signal in which a digital M-value signal (M is an integer of 2 or more) has received intersymbol interference due to the transmission path impulse response being extended to m (m is an integer of 1 or more) symbols, and the received signal. M ⁿ estimated candidate signals for estimation with respect to n (n is an integer of 1 or more and m or less) symbols including at least a precursor component of the impulse response and (m−
M ⁿ pieces for ^one received signal from the equalized candidate signal ^- the n except the first one symbol of the symbol (n-1) consists of the number of states of symbols M ⁿ that for performing equalization n) symbols A branch metric generator that obtains and outputs a branch metric of a modified signal generator that outputs a modified signal from the received signal, modified estimated signal, and modified equalized signal;
The M ⁿ branch metrics from the branch metric generator are input, Viterbi decoding is performed, a received estimated signal consisting of 1 symbol of M value is used as an output for an equalizer, and M ^{n -1} equalization temporary A Viterbi decoder that outputs a decision sequence; receives m received symbols of the reception estimation signal of the Viterbi decoder, outputs M-valued (m−n) -symbol signals, and outputs M-valued n-symbols. A shift register for outputting a signal; outputting the M ⁿ estimated candidate signals to the branch metric generator, and receiving the signal for the M value n symbols from the shift register to correct the modified estimated signal An estimated candidate signal generator that outputs the corrected signal from the corrected signal generator and inputs the corrected signal from the corrected signal generator to correct the estimated candidate signal; and M ^{n -1 of the} Viterbi decoder. Input the equalization provisional judgment sequence and enter M
^n-1 number of equalization candidate signals are output to the branch metric generator, and the M-value (mn) symbol signals are received from the shift register to generate the modified equalization signal as the modified signal. And an equalization candidate signal generator which receives the correction signal from the correction signal generator and corrects the equalization candidate signal.