JP3266029B2 - Dispatching method, dispatching method, and recording medium recording dispatching program in multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dispatching method in a shared memory multiprocessor system which controls which of a plurality of processor groups in which a plurality of processors constituting a shared memory multiprocessor system are grouped is assigned a job. , A dispatching method and a recording medium on which a dispatching program is recorded.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 2-148188 discloses that a plurality of processor groups each composed of a plurality of processors are arranged in a distributed manner, and an arbitrary processor group receives a memory access request. In this case, there is disclosed a technique for efficiently performing memory access by requesting a memory group from a processor group that can directly access the target memory.

[0003] In this conventional technique, by using a memory distributed in each processor group as a cache memory, the throughput of the entire system can be further improved. That is, one job is composed,
By executing a plurality of tasks for accessing a specific area (hereinafter, referred to as a job-dedicated area) in the same processor group, the cache hit rate of the processor group can be increased, and the throughput of the entire system can be improved. .

[0004]

In the above-mentioned prior art, when a large number of jobs using a job-dedicated area are intensively assigned to a specific processor group, the cache memory is frequently updated in that processor group. And the hit rate of the cache is reduced, which causes a problem that the throughput of the entire system is reduced.

An object of the present invention is to improve the throughput of a shared memory multiprocessor system.

It is another object of the present invention to efficiently execute a job in each processor group of a memory sharing type multiprocessor system.

Another object of the present invention is to monitor a hit rate of a cache memory of each processor group of a memory sharing type multiprocessor system, and replace a job executed in a processor group having a lower hit rate with a processor having a higher hit rate. An object of the present invention is to improve the throughput of a job and memory sharing type multiprocessor system by moving to a group.

[0008]

A dispatching method in a first multiprocessor system according to the present invention includes a plurality of processor groups each including a plurality of processors and a cache memory, and a plurality of processor groups .
In a memory sharing type multiprocessor system including a main memory shared by a loop, if any one of the processors in the processor group has a reduced cache memory hit rate of the processor group to which the own processor belongs, And a job moving unit for moving the job executed in (1) to another processor group having a high cache memory hit rate.

[0009] The dispatching method in the second multiprocessor system of the present invention is the dispatching method in the first multiprocessor system.
Any of the processors in the processor group,
The overloaded processor group selecting means for monitoring a hit rate of the cache memory of the processor group to which the own processor belongs is provided, and the job moving means is configured so that the overloaded processor group selecting means sets the cache memory of the processor group to which the own processor belongs. When it is determined that the hit rate has decreased, the job executed in the processor group to which the own processor belongs is moved to another processor group having a high hit rate in the cache memory.

[0010] The dispatching method in the third multiprocessor system according to the present invention is the dispatching method in the second multiprocessor system.
Any of the processors in the processor group,
In addition, the processor group to which the
A cache hit ratio storage area updating unit that measures the number of memory accesses and the number of hits of the cache memory every fixed time, and stores the cache hit ratio storage area in the main memory , wherein the overloaded processor group selection unit is stored in the main memory. The cache rate of the cache memory of the processor group to which the own processor belongs is calculated based on the number of times of memory access and the number of hits of the cache memory, and the hit rate is compared with a preset threshold value. It is determined whether the memory hit rate has decreased, and the job moving unit determines
When the overloaded processor group selecting means determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased, another processor is selected based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. A hit rate of the cache memory of the processor group is calculated, and the job executed in the processor group to which the own processor belongs is moved to another processor group having a high hit rate of the cache memory.

The dispatching method in the fourth multiprocessor system of the present invention is the dispatching method in the third multiprocessor system, wherein:
Any of the processors in the processor group,
Further, after the job moving means has moved a job, a cache hit rate initializing means for initializing a memory access count and a cache memory hit count of all processor groups stored in the main memory is provided. Features.

A dispatching method in a first multiprocessor system according to the present invention includes a plurality of processor groups each including a plurality of processors and a cache memory, which are shared by the plurality of processor groups.
In a memory sharing type multiprocessor system comprising a main memory and a main memory , if any of the processors in the processor group has a reduced cache memory hit rate of the processor group to which the own processor belongs, the processor is executed by the processor. The job is transferred to another processor group having a high cache memory hit ratio.

According to a second dispatching method for a multiprocessor system of the present invention, in a multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, any of the A cache hit rate monitoring step in which the processor monitors a cache memory hit rate of a processor group to which the own processor belongs; Is reduced in the cache hit rate monitoring step, the job executed in the processor group to which the own processor belongs is replaced with another job having a high cache memory hit rate. Characterized in that it comprises a job moving step of moving the B processor group.

[0014] The dispatching method in the third multiprocessor system according to the present invention is the dispatching method in the second multiprocessor system, wherein:
Further, any one of the processors in the processor group is a processor group to which the own processor belongs.
Measuring the number of memory accesses and the number of hits of the cache memory at regular time intervals, and measuring the cache hit rate stored in the main memory , wherein the cache hit rate monitoring step includes the step of monitoring the memory access stored in the main memory. Calculating the hit rate of the cache memory of the processor group to which the own processor belongs based on the number of hits and the number of hits of the cache memory, and comparing the hit rate with a preset threshold value to obtain the cache memory of the processor group to which the own processor belongs. It is determined whether the hit ratio of the cache memory of the processor group to which the own processor belongs has been reduced in the cache hit ratio monitoring step. The cache memory hit rate of another processor group is calculated based on the memory access count obtained and the cache memory hit count, and jobs executed in the processor group to which the own processor belongs are assigned to other cache groups having higher cache memory hit rates. It is characterized by moving to a processor group.

[0015] The dispatching method in the fourth multiprocessor system according to the present invention is the dispatching method in the third multiprocessor system.
Further, after any one of the processors in the processor group moves the job in the job moving step, the number of memory accesses and the number of hits in the cache memory of all the processor groups stored in the main memory are initialized. A cache hit ratio initialization step is included.

[0016]

[0017]

[0018]

[0019]

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a first embodiment of the present invention is a memory sharing type multi-processor comprising a plurality of processor groups having a plurality of processors and a cache memory which operate by sharing a memory under program control. It is a processor system.

At least one task constituting one job is executed in any one of the processors in a certain processor group.

The memory shared by each processor includes a job information storage area 1 for storing the number of a processor group to be executed in a job unit, and a memory area for each processor group. And a cache hit rate storage area 11 for storing the number of times a cache hit has occurred.

One of the processors belonging to each processor group stores the group input means 2 for inputting the number of the processor group designated at the start of the job and the number of the processor group for starting the job in the job information storage area 1. Job information registration means 3, job information input means 4 for referring to the job information storage area 1 when all tasks are started, and inputting the number of the processor group of the job including the task, and job information input means 4 A processor group setting unit 5 for designating the number of the specified processor group and activating a task, a job information deleting unit 6 for deleting the information of the processor group of the job to be ended from the job information storage area 1 when the job ends, It operates at fixed time intervals, and for all processor groups, Based on the number of memory accesses and the ratio of the cache hits of Shuhitto rate storage area 11,
The cache hit ratio from the previous operation is obtained, and if there is a processor group lower than the preset overload threshold, control is passed to the job moving means 8; An overload processor group selecting unit 7 that transfers control to the converting unit 9, and a job that is being executed by a processor group whose cache hit ratio is lower than the overload threshold by the overload processor group selecting unit 7. 1, the job is moved to another processor group whose cache hit ratio is higher than the overload threshold, and the number of the destination processor group is stored in the job information storage area 1 of the job. A job moving unit 8 that transfers control to the hit ratio initializing unit 9; A cache hit ratio initializing means 9 for setting the number of memory accesses storage areas and 0 in the cache hit count storage area of the hit rate storage area 11, and operates when the reference / update memory, cache hit rate storage area 1
One is added to the value of the memory access count storage area of one, and if the memory contents can be obtained from the cache of the processor group to which the operated processor belongs, one is added to the value of the cache hit number storage area. And a cache hit rate storage area updating means 10.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

The group input means 2 starts the job
The number of the designated processor group is input, and control is passed to the job information registration unit 3.

After executing the group input means 2, the job information registration means 3 stores the processor group number of the job to be started in the job information storage area 1.

The job information input means 4 refers to the job information storage area 1 when all tasks are started, inputs the processor group number of the job including the task, and passes control to the processor group setting means 5.

After executing the job information input means 4, the processor group setting means 5 designates the number of the processor group input by the job information input means 4 and starts a task.

The job information deleting means 6 deletes the processor group information of the job to be ended from the job information storage area 1 when the job ends.

Referring to FIG. 2, the overloaded processor group selecting means 7 determines the ratio between the number of memory accesses and the number of cache hits in the cache hit ratio storage area 11 corresponding to the processor group to which the own processor belongs at regular intervals. Based on this, the cache hit rate from the previous operation is obtained (step 201). The overload processor group selecting means 7 determines whether the cache hit rate of the processor group to which the own processor belongs is lower than a preset overload threshold value (step 20).
2) If it is lower, control is passed to the job moving means 8 (step 203).

Referring to FIG. 3, the job moving means 8
After execution of the overloaded processor group selecting means 7, for other processor groups to which the own processor does not belong, based on the ratio of the number of memory accesses to the cache hit ratio storage area 11 and the number of cache hits, the cache hit ratio from the previous operation. And a processor group whose hit rate is higher than a preset overload threshold is specified (step 301). The job moving unit 8 sets the number of the processor group whose cache hit ratio is higher than the threshold value in the processor group number storage area in the job information storage area 1 corresponding to the job being executed by its own processor (step 302). ). Job moving means 8
Restarts all tasks of the job being executed by its own processor in the set processor group (step 303). The job transfer means 8 transfers control to the cache hit rate initialization means 9 (step 30).
4).

After executing the job moving means 8, the cache hit rate initializing means 9 sets 0 in the memory access count storage area and the cache hit number storage area of the cache hit rate storage areas 11 for all processor groups.

Referring to FIG. 4, the cache hit rate storage area updating means 10 sets the value of the memory access frequency storage area of the cache hit rate storage area 11 corresponding to the processor group to which the own processor belongs at the time of referring / updating the memory. 1 is added (step 401). The cache hit rate storage area updating means 10 determines whether or not the memory contents have been obtained from the cache of the processor group to which the own processor belongs (step 402). The cache hit ratio storage area updating means 10 executes step 40
If the memory contents can be obtained in step 2, 1 is added to the value of the cache hit number storage area of the cache hit rate storage area 11 corresponding to the processor group to which the own processor belongs (step 403).

[0035]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, reference numerals 511, 512, and 513 denote processor group number storage areas of job numbers 1, 2, and 3, respectively, and their initial states are "2", "1", and "0". (Not used). 5
Reference numerals 21 and 522 denote memory access frequency storage areas of the processor group 1 and the processor group 2, respectively, and their initial states are "20" and "3", respectively.
0 ". 531 and 532 are cache hit count storage areas of the processor group 1 and the processor group 2, respectively, and their initial state is" 1 ".
5 "and" 10 ".

In this embodiment, in a shared memory type multiprocessor system composed of two processor groups, jobs of job number 1 and job number 2 have already been executed, and the job of job number 3 is to be executed. And

The operation of the embodiment of the present invention will be described below.

The group input means 2 inputs the number of the designated processor group at the start of the job 3 and passes control to the job information registration means 3. In this embodiment, it is assumed that “2” has been input as the processor group number.

After executing the group input unit 2, the job information registration unit 3 stores the processor group number “2” of the job of job number 3 in the processor group number storage area 512 of the job information storage area 51.

When all the tasks of the job of job number 3 are started, the job information input means 4
And enter the processor group number “2”,
The control is passed to the processor group setting means 5.

After executing the job information input means 4, the processor group setting means 5 designates the processor group number "2" input by the job information input means 4, and starts the task.

When the job of job number 3 ends, the job information deleting means 6 deletes the processor group information 513 of the job 3 to be ended from the job information storage area 1.

The overload processor group selecting means 7 comprises:
At regular time intervals, the cache hit ratio from the previous operation is obtained based on the ratio of the number of memory accesses to the cache hit ratio of the cache hit ratio storage area 11 of the processor group 2 (step 201). For processor group 2, memory access count storage area 5
31 = 30, cache hit count storage area 531
Is = 10, so the cache hit rate = 10/3
0 = 0.33.

The overload processor group selecting means 7 comprises:
It is determined whether the cache hit rate of the processor group 2 is lower than a preset overload threshold (step 202). In this embodiment, if the threshold value is set to 0.5, the cache hit ratio of the processor group 2 is lower than the threshold value, so that the control is passed to the job moving means 8 (step 203).

After executing the overloaded processor group selecting means 7, the job moving means 8 obtains the cache hit rate of the processor group 1 (when the value of the memory access frequency storage area 521 = 20, the cache hit number storage area 53).
Since the value of 1 = 15, the cache hit ratio = 15 /
20 = 0.75. ), And recognizes that the cache hit rate of the processor group 1 is higher than the threshold (step 301). The job moving unit 8 sets the processor group number “1” having a cache hit ratio higher than the threshold value in the processor group number storage area 511 corresponding to the job 1 (Step 302). The job moving means 8 restarts all the tasks of the job 1 in the processor group 1 (step 303).
The job moving means 8 includes a cache hit rate initializing means 9
Control (step 304).

After executing the job moving means 8, the cache hit rate initializing means 9 stores the memory access frequency storage areas 521 and 522 and the cache hit number storage areas 531 and 532 of the cache hit rate storage area 51 for the processor groups 1 and 2. Is set to 0.

Cache hit rate storage area updating means 10
For example, at the time of referring / updating the memory of the processor belonging to the processor group 1, 1 is added to the value of the memory access count storage area of the processor group 1 in the cache hit rate storage area 11 to be "21" (step 4).
01). The cache hit ratio storage area updating means 10
It is determined whether or not the memory contents can be obtained from the cache of the processor group 1 (step 402). Assuming that the memory contents can be acquired, the cache hit ratio storage area updating unit 10
One is added to the value of the cache hit number storage area of one processor group 1 to be "16" (step 40).
3).

Thus, the operation of the embodiment of the present invention is completed.

In the present embodiment, a job being executed in a processor group having a low cache hit rate is moved to a processor group having a cache hit rate higher than another overload threshold, thereby obtaining a cache hit rate. This has the effect of reducing the rate.

Next, another embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, another embodiment of the present invention includes a recording medium 12 on which a dispatching program is recorded, in addition to the first embodiment.

The dispatching program is read from the recording medium 12 by one of the processors in the processor group, and controls the operation of the processor. Under the control of the dispatching program, the processor performs processing by the processor according to the first embodiment, that is, group input means 2, job information registration means 3, job information input means 4, processor group setting means 5, job information deletion means 6, The same processing as the overload processor group selecting means 7, the job moving means 8, the cache hit rate initializing means 9 and the cache hit rate storage area updating means 10 is executed.

With the above, the operation of the other embodiment is completed.

[0055]

As described above, according to the present invention, the hit rate of the cache memory of each processor group of the memory sharing type multiprocessor system is monitored, and the job executed in the processor group having the reduced hit rate is hit. By moving to a processor group having a high rate, the job and the memory sharing type multiprocessor system have the effect of improving the throughput.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a process of an overloaded processor group selecting means 7 according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating processing of a job moving unit 8 according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a process of a cache hit ratio storage area updating unit 10 according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 job information storage area 2 group input means 3 job information registration means 4 job information input means 5 processor group setting means 6 job information deletion means 7 overloaded processor group selection means 8 job movement means 9 cache hit ratio initialization means 10 cache hit Rate storage area updating means 11 cache hit rate storage area 12 recording medium

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI G06F 12/08 565 G06F 12/08 565 15/177 674 15/177 674B (56) References JP-A-2-181844 (JP, A) Japanese Unexamined Patent Publication No. Hei 8-137794 (JP, A) Japanese Unexamined Patent Publication No. Hei 9-81528 (JP, A) Japanese Unexamined Patent Publication No. Hei 7-262090 (JP, A) Naoto Ishikura, 6 others, Infrastructure Architecture, NEC Technical Report, Japan, NEC Creative Inc., September 25, 1995, Vol. 48 No. 9, 112-115 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 12/08-12/12 G06F 9/46 JICST file (JOIS)

Claims (8)

(57) [Claims] 1. A respectively and a plurality of processors and a plurality of processor groups including a cache memory, the double
In a shared memory multiprocessor system including a main memory shared by a number of processor groups, one of the processors in the processor group includes:
A job moving unit configured to move a job executed by the own processor to another processor group having a higher cache memory hit ratio when the hit rate of the cache memory of the processor group to which the own processor belongs decreases. Dispatching method in a multiprocessor system. 2. One of the processors in the processor group further includes an overloaded processor group selecting unit that monitors a hit ratio of a cache memory of the processor group to which the own processor belongs. If the load processor group selecting means determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased, the job executed in the processor group to which the own processor belongs to another processor group having a high hit rate of the cache memory. 2. The dispatching method in the multiprocessor system according to claim 1, wherein the process is moved to. 3. A processor in the processor group further measures the number of memory accesses and the number of cache memory hits of the processor group to which the own processor belongs at regular intervals, and stores the measured number in the main memory. A cache hit ratio storage area updating unit, wherein the overloaded processor group selecting unit determines a hit ratio of a cache memory of a processor group to which the own processor belongs based on a memory access count stored in the main memory and a cache memory hit count. By comparing the hit rate with a preset threshold value, it is determined whether the hit rate of the cache memory of the processor group to which the own processor belongs has been reduced. But own processor If it is determined that the hit rate of the cache memory of the processor group to be executed has decreased, the hit rate of the cache memory of another processor group is calculated based on the number of accesses to the memory and the number of hits of the cache memory stored in the main memory. 3. The dispatching method according to claim 2, wherein the job executed in the processor group to which the own processor belongs is moved to another processor group having a high cache memory hit rate. 4. The method according to claim 1, wherein any of the processors in the processor group further includes a memory access count and a cache memory hit count of all processor groups stored in the main memory after the job moving unit moves the job. 4. A dispatching method in a multiprocessor system according to claim 3, further comprising a cache hit rate initializing means for initializing a cache hit rate. 5. each of a plurality of processor groups and a plurality of processors and a cache memory, the double
In a shared memory multiprocessor system including a main memory shared by a number of processor groups, one of the processors in the processor group includes:
When the hit rate of the cache memory belonging to the processor group to which the own processor belongs decreases, the job executed by the processor is moved to another processor group having a high hit rate of the cache memory. Dispatching method. 6. A multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, wherein one of the processors in the processor group includes:
A cache hit ratio monitoring step of monitoring a hit ratio of a cache memory belonging to a processor group to which the own processor belongs; and one of the processors in the processor group,
When it is determined in the cache hit rate monitoring step that the hit rate of the cache memory belonging to the processor group to which the own processor belongs is reduced, the job executed in the processor group to which the own processor belongs becomes the hit rate of the cache memory. And a job moving step of moving to another high processor group. 7. A processor in the processor group measures the number of memory accesses and the number of hits in the cache memory of the processor group to which the processor belongs at regular intervals, and stores the measured number in the main memory. A cache hit rate measuring step, wherein the cache hit rate monitoring step determines the hit rate of the cache memory of the processor group to which the own processor belongs based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. By calculating and comparing the hit rate with a preset threshold value, it is determined whether or not the hit rate of the cache memory of the processor group to which the own processor belongs has been reduced. Step If it is determined that the hit rate of the cache memory of the processor group to which the processor belongs has decreased, the hit rate of the cache memory of another processor group is determined based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. 7. A dispatching method in a multiprocessor system according to claim 6, wherein the job executed in the processor group to which the own processor belongs is moved to another processor group having a high cache memory hit ratio. 8. A memory access count and a cache memory hit count of all processor groups stored in the main memory after any processor in the processor group moves a job in the job moving step. 8. A cache hit rate initializing step of initializing the following.
A method for dispatching in a multiprocessor system as described.