JPH10207850A - Dispatching system and method for multiprocessor system, and recording medium recorded with dispatching program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of a job and memory sharing type multiprocessor system. SOLUTION: An overload processor group selecting means 7 monitors the hit rates of cache memories of all processor groups at constant intervals of time according to the ratio of the memory access frequency and cache hit rate of a cache hit rate storage area 11, and a job moving means 8 moves a job performed by a processor group having decreased in hit rate to a processor group with a high hit rate to improve the throughput of the job and memory sharing type multiprocessor system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dispatching method in a shared memory type multiprocessor system which controls which of a plurality of processor groups in which a plurality of processors constituting a shared memory type multiprocessor system are grouped is assigned a job. , A dispatching method and a recording medium recording a dispatching program.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 2-148188 discloses that a plurality of processor groups each composed of a plurality of processors are provided with a distributed memory, and an arbitrary processor group receives a memory access request. In this case, there is disclosed a technique for efficiently performing memory access by requesting a memory group from a processor group that can directly access the memory of the memory access request target.

[0003] In this conventional technique, by using a memory distributed in each processor group as a cache memory, the throughput of the entire system can be further improved. That is, one job is composed,
By executing a plurality of tasks that access a specific area (hereinafter, referred to as a job-dedicated area) in the same processor group, the cache hit rate of the processor group can be increased, and the throughput of the entire system can be improved. .

[0004]

In the above-mentioned prior art, when a large number of jobs using a job-dedicated area are intensively allocated to a particular processor group, the cache memory is frequently updated in the particular processor group. In this case, the cache hit rate is reduced, and the throughput of the entire system is reduced.

An object of the present invention is to improve the throughput of a shared memory multiprocessor system.

It is another object of the present invention to efficiently execute a job in each processor group of a memory sharing type multiprocessor system.

Another object of the present invention is to monitor a cache memory hit ratio of each processor group of a memory sharing type multiprocessor system, and replace a job executed in a processor group having a reduced hit ratio with a processor having a high hit ratio. An object of the present invention is to improve the throughput of a job and memory sharing type multiprocessor system by moving to a group.

[0008]

According to a first aspect of the present invention, there is provided a dispatching method for a multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory. If any of the processors in the group decreases the hit rate of the cache memory of the processor group to which the own processor belongs, the job executed in the processor group to which the own processor belongs is replaced by another processor group with a high cache memory hit rate. And a job moving means for moving the job.

[0009] The dispatching method in the second multiprocessor system of the present invention is the dispatching method in the first multiprocessor system.
Any of the processors in the processor group,
The processor further includes an overloaded processor group selecting unit that monitors a hit rate of the cache memory of the processor group to which the own processor belongs. When it is determined that the hit rate has decreased, the job executed in the processor group to which the own processor belongs is moved to another processor group having a high hit rate in the cache memory.

[0010] The dispatching method in the third multiprocessor system of the present invention is the dispatching method in the second multiprocessor system.
Any of the processors in the processor group,
Furthermore, the processor group to which the own processor belongs,
A cache hit ratio storage area updating unit that measures the number of memory accesses and the number of hits of the cache memory at fixed time intervals and stores the same in a main memory shared by all processors; Based on the number of memory accesses stored in the memory and the number of hits of the cache memory, the hit rate of the cache memory of the processor group to which the own processor belongs is calculated, and the hit rate is compared with a preset threshold value. It is determined whether the hit rate of the cache memory of the processor group to which the processor belongs belongs. If the job moving means determines that the hit rate of the cache memory of the processor group to which the own processor belongs has been reduced by the overloaded processor group selecting means, , The main The cache memory hit rate of another processor group is calculated based on the number of memory accesses stored in the memory and the number of cache memory hits, and the jobs executed in the processor group to which the own processor belongs become the cache memory hit rate. It is characterized by moving to another high processor group.

The dispatching method in the fourth multiprocessor system of the present invention is the dispatching method in the third multiprocessor system,
Any of the processors in the processor group,
Further, after the job moving means has moved a job, a cache hit rate initializing means for initializing the number of memory accesses and the number of hits of the cache memory of all processor groups stored in the main memory is provided. Features.

A dispatching method in a first multiprocessor system according to the present invention is directed to a multiprocessor system including a plurality of processor groups each including a plurality of processors and a cache memory. When the hit rate of the cache memory of the processor group to which the own processor belongs decreases, the processor moves the job executed in the processor group to another processor group having a high hit rate of the cache memory. .

According to a second dispatching method for a multiprocessor system of the present invention, in a multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, any of the A cache hit ratio monitoring step in which a processor monitors a cache memory hit ratio of a processor group to which the own processor belongs; and a cache rate of a cache memory belonging to the processor group to which any of the processors in the processor group belongs. Is reduced in the cache hit ratio monitoring step, the job executed in the processor group to which the own processor belongs is replaced with another job having a high cache memory hit ratio. Characterized in that it comprises a job moving step of moving the B processor group.

[0014] The dispatching method in the third multiprocessor system according to the present invention is the dispatching method in the second multiprocessor system, wherein:
Further, any one of the processors in the processor group is a processor group to which the own processor belongs.
Measuring the number of memory accesses and the number of hits of the cache memory at regular time intervals, and storing the cache hit rate in a main memory shared by all processors; Based on the stored number of memory accesses and the number of hits of the cache memory, the hit ratio of the cache memory of the processor group to which the own processor belongs is calculated, and the hit ratio is compared with a preset threshold value, whereby the own processor belongs. It is determined whether or not the hit rate of the cache memory of the processor group has decreased, and if the job moving step determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased in the cache hit rate monitoring step. A cache memory hit ratio of another processor group is calculated based on the number of memory accesses stored in the main memory and the number of cache memory hits, and the job executed in the processor group to which the own processor belongs is determined by the cache memory hit ratio. It is characterized by moving to another processor group with a high rate.

A fourth dispatching method in a multiprocessor system according to the present invention is the dispatching method in the third multiprocessor system, wherein:
Further, after any one of the processors in the processor group moves the job in the job moving step, the number of memory accesses and the number of hits in the cache memory of all the processor groups stored in the main memory are initialized. The method includes a cache hit rate initialization step.

According to a first recording medium of the present invention, in a multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, one of the processors in the processor group is provided with its own processor. If the hit rate of the cache memory of the processor group to which the
A program for causing a job executed in the processor group to be moved to another processor group having a high hit rate of the cache memory is recorded.

According to a second recording medium of the present invention, in a multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, one of the processors in the processor group is provided with its own processor. The cache hit rate monitoring process for monitoring the cache memory hit rate of the processor group to which the processor group belongs, and the cache hit rate monitoring process determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased. In addition, a program for causing a job that has been executed in the processor group to which the own processor belongs to be moved to another processor group having a high hit rate of the cache memory is recorded.

A third recording medium according to the present invention, in the second recording medium, further comprises: for any one of the processors in the processor group, A program for measuring the number of hits of the cache memory and performing a cache hit ratio measurement process stored in the main memory shared by all processors, wherein the cache hit ratio monitoring process is stored in the main memory. The cache memory hit ratio of the processor group to which the own processor belongs is calculated based on the memory access frequency and the cache memory hit frequency, and the hit ratio is compared with a preset threshold value, whereby the processor group to which the own processor belongs is calculated. Cache memory hit rate If the job migration process determines in the cache hit ratio monitoring process that the hit ratio of the cache memory of the processor group to which the own processor belongs has decreased, the memory access stored in the main memory is determined. The cache memory hit ratio of another processor group is calculated based on the number of times and the cache memory hit frequency, and the job executed in the processor group to which the own processor belongs is moved to another processor group having a high cache memory hit ratio. It is characterized by doing.

The fourth recording medium of the present invention is the third recording medium, wherein the job is transferred to any one of the processors in the processor group in the job transfer process and then stored in the main memory. And a program for performing a cache hit ratio initialization process for initializing the number of memory accesses and the number of cache memory hits of all processor groups.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a first embodiment of the present invention is a memory sharing type multi-processor comprising a plurality of processor groups having a plurality of processors and a cache memory which operate by sharing a memory under program control. It is a processor system.

At least one task constituting one job is executed in any one of the processors of a certain processor group.

The memory shared by each processor includes a job information storage area 1 for storing the number of a processor group to be executed in a job unit and a memory area for each processor group. And a cache hit rate storage area 11 for storing the number of hits to the cache.

One of the processors belonging to each processor group stores the group input means 2 for inputting the number of the processor group designated at the start of the job and the number of the processor group for starting the job in the job information storage area 1. Job information registration means 3, job information input means 4 for referencing the job information storage area 1 when all tasks are started, and inputting the number of the processor group of the job containing the task, and job information input means 4 A processor group setting unit 5 for designating the number of the specified processor group and activating the task; a job information deleting unit 6 for deleting the information of the processor group of the job to be ended from the job information storage area 1 when the job ends; It runs at regular intervals, and for all processor groups, Based on the number of memory accesses and the ratio of the cache hits of Shuhitto rate storage area 11,
The cache hit ratio from the previous operation is obtained, and if there is a processor group lower than the preset overload threshold, control is passed to the job moving unit 8; An overload processor group selection unit 7 that transfers control to the conversion unit 9, and a job that is being executed by a processor group whose cache hit ratio is lower than the overload threshold by the overload processor group selection unit 7. 1, the job is moved to another processor group in which the cache hit ratio is higher than the overload threshold, the number of the destination processor group is stored in the job information storage area 1 of the job, A job moving unit 8 for transferring control to the hit ratio initializing unit 9; A cache hit ratio initializing means 9 for setting the number of memory accesses storage areas and 0 in the cache hit count storage area of the hit rate storage area 11, and operates when the reference / update memory, cache hit rate storage area 1
One is added to the value of the memory access count storage area of one, and when the memory contents can be obtained from the cache of the processor group to which the processor that has performed the operation is added, one is added to the value of the cache hit number storage area. And a cache hit rate storage area updating means 10.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

The group input means 2 starts the job
The number of the designated processor group is input, and control is passed to the job information registration unit 3.

After executing the group input means 2, the job information registration means 3 stores the processor group number of the job to be started in the job information storage area 1.

The job information input means 4 refers to the job information storage area 1 when all tasks are started, inputs the processor group number of the job including the task, and passes control to the processor group setting means 5.

After executing the job information input means 4, the processor group setting means 5 designates the number of the processor group input by the job information input means 4 and starts a task.

The job information deleting means 6 deletes the processor group information of the job to be ended from the job information storage area 1 when the job ends.

Referring to FIG. 2, the overloaded processor group selecting means 7 calculates the ratio between the number of memory accesses and the number of cache hits in the cache hit ratio storage area 11 corresponding to the processor group to which the own processor belongs at regular intervals. Based on this, the cache hit ratio from the previous operation is obtained (step 201). The overload processor group selecting means 7 determines whether the cache hit ratio of the processor group to which the own processor belongs is lower than a preset overload threshold value (step 20).
2) If it is lower, control is passed to the job moving means 8 (step 203).

Referring to FIG. 3, the job moving means 8 comprises:
After the execution of the overloaded processor group selecting means 7, for other processor groups to which the own processor does not belong, based on the ratio of the number of memory accesses to the cache hit rate storage area 11 and the number of cache hits, the cache hit ratio from the previous operation. And a processor group whose hit ratio is higher than a preset overload threshold is specified (step 301). The job moving means 8 sets the number of the processor group whose cache hit ratio is higher than the threshold value in the processor group number storage area in the job information storage area 1 corresponding to the job being executed by its own processor (step 302). ). Job moving means 8
Restarts all tasks of the job being executed by its own processor in the set processor group (step 303). The job transfer means 8 transfers control to the cache hit rate initialization means 9 (step 30).
4).

After executing the job moving means 8, the cache hit rate initializing means 9 sets 0 to the memory access count storage area and the cache hit number storage area of the cache hit rate storage areas 11 for all processor groups.

Referring to FIG. 4, the cache hit rate storage area updating means 10 updates the value of the memory access count storage area of the cache hit rate storage area 11 corresponding to the processor group to which the own processor belongs when the memory is referenced / updated. 1 is added (step 401). The cache hit ratio storage area updating means 10 determines whether or not the memory contents can be obtained from the cache of the processor group to which the own processor belongs (step 402). The cache hit rate storage area updating means 10 executes step 40
If the memory contents can be obtained in step 2, 1 is added to the value of the cache hit number storage area of the cache hit rate storage area 11 corresponding to the processor group to which the own processor belongs (step 403).

[0035]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, reference numerals 511, 512, and 513 denote processor group number storage areas of job numbers 1, 2, and 3, respectively, and their initial states are "2", "1", and "0". (Not used). 5
21 and 522 are memory access count storage areas of the processor group 1 and the processor group 2, respectively, and their initial states are “20” and “3”, respectively.
0 ". 531 and 532 are cache hit count storage areas of the processor group 1 and the processor group 2, respectively, and their initial state is" 1 ".
5 "and" 10 ".

In this embodiment, in a shared memory type multiprocessor system comprising two processor groups, the job of job number 1 and job number 2 has already been executed, and the job of job number 3 is to be executed. And

The operation of the embodiment of the present invention will be described below.

When the job 3 starts, the group input unit 2 inputs the number of the designated processor group, and passes control to the job information registration unit 3. In this embodiment, it is assumed that “2” has been input as the processor group number.

After executing the group input unit 2, the job information registration unit 3 stores the processor group number “2” of the job of job number 3 in the processor group number storage area 512 of the job information storage area 51.

When all the tasks of the job of job number 3 are started, the job information input means 4
And enter the processor group number “2”,
The control is passed to the processor group setting means 5.

After executing the job information input means 4, the processor group setting means 5 designates the processor group number "2" input by the job information input means 4, and starts the task.

When the job of job number 3 ends, the job information deleting means 6 deletes the processor group information 513 of the job 3 to be ended from the job information storage area 1.

The overload processor group selecting means 7 comprises:
At regular time intervals, the cache hit ratio from the previous operation is obtained based on the ratio of the number of memory accesses to the cache hit ratio storage area 11 of the processor group 2 and the number of cache hits (step 201). For processor group 2, memory access count storage area 5
31 = 30, the cache hit number storage area 531
Is = 10, so the cache hit rate = 10/3
0 = 0.33.

The overload processor group selecting means 7 comprises:
It is determined whether the cache hit rate of the processor group 2 is lower than a preset overload threshold (step 202). In this embodiment, if the threshold value is 0.5, the cache hit ratio of the processor group 2 is lower than the threshold value, so that the control is passed to the job moving means 8 (step 203).

After executing the overloaded processor group selecting means 7, the job moving means 8 acquires the cache hit rate of the processor group 1 (when the value of the memory access frequency storage area 521 is 20, the cache hit number storage area 53 is obtained).
Since the value of 1 = 15, the cache hit ratio = 15 /
20 = 0.75. ), And recognizes that the cache hit ratio of the processor group 1 is higher than the threshold (step 301). The job moving means 8 sets a processor group number “1” having a cache hit rate higher than a threshold value in the processor group number storage area 511 corresponding to the job 1 (step 302). The job moving means 8 restarts all the tasks of the job 1 in the processor group 1 (step 303).
The job moving means 8 includes a cache hit rate initializing means 9
Control (step 304).

After executing the job moving means 8, the cache hit rate initializing means 9 stores the memory access count storage areas 521 and 522 and the cache hit number storage areas 531 and 532 of the cache hit rate storage area 51 for the processor groups 1 and 2. Is set to 0.

Cache hit rate storage area updating means 10
For example, at the time of referring / updating the memory of the processor belonging to the processor group 1, 1 is added to the value of the memory access count storage area of the processor group 1 in the cache hit rate storage area 11 to be "21" (step 4).
01). The cache hit ratio storage area updating means 10
It is determined whether or not the memory contents can be obtained from the cache of the processor group 1 (step 402). Assuming that the memory contents can be obtained, the cache hit ratio storage area updating unit 10
One is added to the value of the cache hit number storage area of one processor group 1 to be "16" (step 40).
3).

Thus, the operation of the embodiment of the present invention is completed.

In the present embodiment, a job being executed in a processor group having a low cache hit rate is moved to a processor group having a cache hit rate higher than another overload threshold, so that the cache hit rate is reduced. It has the effect of correcting the drop in rate.

Next, another embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, another embodiment of the present invention includes, in addition to the first embodiment, a recording medium 12 on which a dispatching program is recorded.

The dispatching program is read from the recording medium 12 by one of the processors in the processor group, and controls the operation of the processor. Under the control of the dispatching program, the processor performs processing by the processor according to the first embodiment, that is, the group input unit 2, the job information registration unit 3, the job information input unit 4, the processor group setting unit 5, the job information deletion unit 6. The same processing as the overload processor group selecting means 7, the job moving means 8, the cache hit rate initializing means 9, and the cache hit rate storage area updating means 10 is executed.

With the above, the operation of the other embodiment is completed.

[0055]

As described above, according to the present invention, the hit rate of the cache memory of each processor group of the memory sharing type multiprocessor system is monitored, and the job executed in the processor group having the reduced hit rate is hit. By moving to a processor group having a higher rate, the job and memory sharing type multiprocessor system has an effect of improving the throughput.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a process of an overloaded processor group selecting means 7 according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating processing of a job moving unit 8 according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a process of a cache hit ratio storage area updating means 10 according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 1 Job information storage area 2 Group input means 3 Job information registration means 4 Job information input means 5 Processor group setting means 6 Job information deletion means 7 Overload processor group selection means 8 Job movement means 9 Cache hit ratio initialization means 10 Cache hit Rate storage area updating means 11 cache hit rate storage area 12 recording medium

Claims (12)

[Claims] 1. In a multiprocessor system including a plurality of processor groups each including a plurality of processors and a cache memory, any one of the processors in the processor group is a cache memory of a processor group to which the own processor belongs. Dispatching in a multiprocessor system, comprising: a job moving unit that moves a job executed in a processor group to which the own processor belongs to another processor group having a high hit rate in a cache memory when the hit rate decreases. Method. 2. One of the processors in the processor group further includes an overloaded processor group selecting unit that monitors a hit ratio of a cache memory of the processor group to which the own processor belongs. If the load processor group selecting means determines that the cache memory hit rate of the processor group to which the own processor belongs has decreased, the job executed in the processor group to which the own processor belongs is replaced by another processor group having a high cache memory hit rate. 2. The dispatching method in the multiprocessor system according to claim 1, wherein the process is moved to. 3. A processor in the processor group further measures the number of memory accesses and the number of cache memory hits of the processor group to which the own processor belongs at regular intervals, and is shared by all processors. A cache hit ratio storage area updating unit for storing in a main memory, wherein the overloaded processor group selecting unit is configured to determine a processor group to which the own processor belongs based on a memory access count stored in the main memory and a cache memory hit count. The hit ratio of the cache memory is calculated, and the hit ratio is compared with a preset threshold value to determine whether the hit ratio of the cache memory of the processor group to which the own processor belongs has decreased. Load processor group When the selecting means determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased, the cache memory of another processor group is determined based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. Calculate the hit rate of
3. The job executed in the processor group to which the own processor belongs is moved to another processor group having a high hit rate of the cache memory.
A dispatching method in the multiprocessor system described. 4. A processor in the processor group further comprising: a memory access count and a cache memory hit count of all processor groups stored in the main memory after the job moving unit moves a job. 4. A dispatching method in a multiprocessor system according to claim 3, further comprising a cache hit rate initializing means for initializing a cache hit rate. 5. A multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, wherein any one of the processors in the processor group includes:
When the hit rate of the cache memory of the processor group to which the own processor belongs is reduced, the job executed in the processor group is moved to another processor group having a high hit rate of the cache memory. Dispatching method. 6. A multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, wherein one of the processors in the processor group includes:
A cache hit rate monitoring step of monitoring a hit rate of a cache memory belonging to a processor group to which the own processor belongs; and one of the processors in the processor group,
If it is determined in the cache hit rate monitoring step that the hit rate of the cache memory belonging to the processor group to which the own processor belongs is reduced, the job executed in the processor group to which the own processor belongs is reduced to the hit rate of the cache memory. A job moving step of moving to another high processor group. 7. A processor in one of the processor groups measures the number of memory accesses and the number of hits of the cache memory of the processor group to which the processor belongs at regular intervals, and is shared by all processors. Measuring the cache hit ratio stored in the main memory, wherein the cache hit ratio monitoring step is performed based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. The hit ratio of the memory is calculated, and the hit ratio is compared with a preset threshold value to determine whether the hit ratio of the cache memory of the processor group to which the own processor belongs has decreased. rate When it is determined in the viewing step that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased, the cache of another processor group is determined based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. 7. The dispatch in the multiprocessor system according to claim 6, wherein a memory hit ratio is calculated, and the job executed in the processor group to which the own processor belongs is moved to another processor group having a high cache memory hit ratio. Method. 8. A memory access count and a cache memory hit count of all processor groups stored in the main memory after any processor in the processor group moves a job in the job moving step. 8. A cache hit rate initializing step for initializing a cache hit rate.
A dispatching method in the multiprocessor system described in the above. 9. A multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, wherein any of the processors in the processor group includes:
When the hit rate of the cache memory of the processor group to which the own processor belongs is reduced, a program for performing a process of moving a job executed in the processor group to another processor group having a high hit rate of the cache memory is executed. A recording medium characterized by being recorded. 10. A multiprocessor system comprising a plurality of processor groups each including a plurality of processors and a cache memory, wherein any of the processors in the processor group includes:
It is determined in the cache hit ratio monitoring process that monitors the hit ratio of the cache memory belonging to the processor group to which the own processor belongs, and that the hit ratio of the cache memory belonging to the processor group to which the own processor belongs decreases. Recording a program for causing a job executed in the processor group to which the own processor belongs to to be transferred to another processor group having a high hit rate of the cache memory in the case where the job has been executed. Medium. 11. The processor group of any one of the processor groups measures the number of memory accesses and the number of hits of the cache memory of the processor group to which the processor belongs at regular intervals, and is shared by all processors. A program for performing a cache hit ratio measurement process stored in the main memory, wherein the cache hit ratio monitoring process is performed by the own processor based on the number of memory accesses stored in the main memory and the number of hits of the cache memory. Calculating a hit ratio of the cache memory of the processor group to which the processor group belongs;
By comparing the hit rate with a preset threshold,
It is determined whether the hit rate of the cache memory of the processor group to which the own processor belongs has decreased. The job migration process determines that the hit rate of the cache memory of the processor group to which the own processor belongs has decreased in the cache hit ratio monitoring process. In this case, the hit rate of the cache memory of another processor group is calculated based on the number of memory accesses stored in the main memory and the number of hits of the cache memory, and the job executed in the processor group to which the own processor belongs is calculated. 11. The recording medium according to claim 10, wherein the cache medium is moved to another processor group having a high hit rate. 12. A memory access count and a cache memory hit count of all processor groups stored in the main memory after a job is moved to any of the processors in the processor group in the job moving process. 12. The recording medium according to claim 11, further comprising a program for performing a cache hit ratio initialization process for initializing a cache hit ratio.