JP2682746B2 - Virtual computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual computer system, and more particularly to a virtual computer system that operates a virtual computer using a service processor.

[0002]

2. Description of the Related Art A virtual computer is realized by allocating and simulating processor resources by a virtual computer control program (hereinafter simply referred to as a control program).
In the case of operating such a virtual computer, conventionally, the virtual computer was controlled by communicating with the control program using the input / output device connected to the input / output channel of the processing device.

A known document related to this type of technique is, for example, Japanese Patent Laid-Open No. 63-142424, "Screen division method for virtual computer console device".

[0004]

In the above prior art, it is necessary to prepare an input / output device for a control program and define the input / output device for the control program. There is a problem that you cannot operate.

An object of the present invention is to eliminate the need to prepare an input / output device specially for a control program and to allow a user to easily operate a virtual computer.

Another object of the present invention is to enable a virtual computer to be used without the user being aware of the program when the system is started up.

[0007]

In order to achieve the above object, according to the present invention, a logic is provided between a control program for controlling a virtual computer operating on a processing device and a service processor for performing maintenance operation of the processing device. Specific instruction that specifies an operation request to the service processor that is effective only in the virtual machine mode by providing a dynamic communication means (hereinafter, for virtual machine
Call it an instruction) .

[0008]

The service processor is provided with a non-volatile storage device such as a console device or a disk device, and these devices are used instead of the conventional input / output device.

The control program gives an operation request to the service processor by a virtual computer instruction only in the virtual computer mode. The virtual machine instruction is for causing the service processor to activate an operation equivalent to that of an input / output channel. The reason why the virtual machine instruction is valid only in the virtual machine mode is to prevent the program from using the service processor for purposes other than the use of the virtual machine.

The service processor instructed to perform the operation reads or writes information between the main memory of the processing device and the console device or the non-volatile memory device of the service processor in accordance with the instruction for the virtual computer (in other words, control). The service processor controls the information prepared by the program in the main memory by accessing the main memory),
Completion of the operation is notified to the control program by a completion interrupt. Upon completion of this operation, the service processor also stores completion status information in the main memory. The control program can know the operation completion of the virtual machine instruction by the completion interrupt, and the status can be known by reading the completion status information in the main memory.

Further, the service processor transmits a command to the control program from the console device by the user to the control program by an asynchronous interrupt, and at the same time stores the requested content in the main memory. The control program accesses the main memory to know the content of the request, issues a virtual machine instruction, and the service processor executes the instruction to display a message from the control program on the screen of the console device of the service processor. can do.

Further, when the reset operation is executed for the processing device, the service processor loads the control program previously stored in the non-volatile storage device into the main memory, and then a part of the program is stored in the program state of the processing device. Word (PS
W) to start the control program. As a result, the virtual computer can be used by loading and activating the control program without operator intervention such as when the system is started up.

[0013]

1 is a schematic block diagram of an embodiment of a virtual computer system to which the present invention is applied. In the figure, 101 is an information processing device (CPU), 102 is a service processor (SVP), 103 is a console display device (CD) of the SVP 102, and 104 is a nonvolatile storage device (HD) of the SVP 102. 105-11
Reference numeral 0 is a component in the CPU 101, 105 is an instruction processor (IP), 106 is a local storage (LS) in the IP 106, 107 is a service processor communication unit (SVU), and 108 is a main storage controller (S).
C), 109 are main memories (MS), and 110 is an input / output processing unit (IOP).

In the present embodiment, the IP10 is stored in the CPU 101.
5 shows one and the SVP 102 also has one CD 103, but of course, the present invention is not limited to this.
An input / output device (I / O) is connected to the IOP 110, but it is omitted here.

The LS 106 is an internal memory used by hardware and microprograms that cannot be accessed by programs. SVU107 is SVP102 and IP
The SVP 102 is a device connecting between 105 and the SVU 10
It is possible to generate a completion interrupt and an asynchronous interrupt as the service signal external interrupt to the IP 105 via the IP address 7, and to write data to the LS 106, and the LS 10
It is possible to read data from 6. further,
The SVP 102 can access the MS 109 via the SVU 107 and the SC 108.

The SVP 102 is a CD 103 and an HD 10
4 is directly controlled, and it is possible to write screen data to the CD 103, read screen data from the CD 103, write data to the HD 104, and read data from the HD 104. The HD 104 is, for example, a disk device, and the inside thereof is divided to realize a plurality of nonvolatile files.

FIG. 2 shows a format example of a virtual computer instruction (hereinafter referred to as HVACTL) and its operand (hereinafter referred to as HCW) newly added according to the present invention. Reference numeral 201 is an HVACT instruction format, the instruction code is (8350) ₁₆ , the base register field B ₂ and the displacement D ₂ indicate the head absolute address of the HCW 202 which is the operand. Here, the operand address is an absolute address because the SVP 102 is the HC on the MS 109.
Since the W202 is accessed, the SVP 102 can access the MS 109 only with the absolute address. 202 is an HCW format, 203 is a sub-operation code (SOP), 204 is a device identifier (HDID), 205 is a command (CMD), 206 is a transfer data amount (CNT), and 207 is a transfer data MS1.
The absolute address on 09 is shown.

The HVACTL 201 is an instruction for requesting an operation to the SVP 102, and details of the operation are the HCW 20.
Indicated by 2. In the HCW 202, the SOP 203 indicates the target of the requested operation. Here, (000
1) ₁₆ is a request for CD 103, (0002) ₁₆ is H
It means that it is an operation request to D104. HDID204 is a serial number starting from 0,
It is used as an identifier when there are a plurality of CDs 103 or HDs 104. In the present embodiment, the HD 104 is divided into one physical unit, but logically appears to be a plurality. The CMD 205 indicates the type of operation. Here, (02) ₁₆ is from the SVP 102 to the MS 10
Data transfer to 9, (01) ₁₆ from MS109 to SVP
Data transfer to 102 is meant. CNT2
06 designates the amount of data to be transferred in bytes.
DADR 207 indicates the start address of MS 109 from which data should be read when CMD 205 is (02) ₁₆ .
When the CMD 205 is (01) ₁₆ , it indicates the start address of the MS 109 in which the data to be transferred to the SVP 102 is stored.

FIG. 3 shows the format and use of the LS 106. Here, LS106 is 2 of 4 bytes each.
It is assumed that each entry is provided with a unique number consisting of 56 entries, each of which starts from 0, and each entry is addressed in units of 4 bytes.
In this embodiment, the entries 0 to 3 of the LS 106 are used for the present invention.

Reference numeral 301 denotes the 0th entry of the LS 106, and when its bit 0 (hereinafter referred to as H bit 301) is 1, it means that it is in the virtual computer mode. The H bit 301 is set by the SVP 102. That is, SV
P102 is L via SVU107 when the virtual computer mode is specified by the operator through CD103.
The S bit is accessed and the H bit 301 is set to 1.

An entry 302 stores the head absolute address of the HCW 202 specified by the HVACTL 201, which is set by the microprogram during the instruction processing of the HVACTL 201, and the SVP 102 is set by the HVACTL.
When the request of 201 is accepted, the content is read by the SVP 102. That is, the SVP 102 can know the address on the MS 109 of the HCW 202 from the HCW address 302.

Reference numeral 303 denotes a virtual machine instruction completion status word (H
This is an entry for storing SW) and is set by the SVP 102 after the requested operation by the HVACTL 201 is completed. The reason why the SVP 102 temporarily stores the HSW 303 in the LS 106 without directly storing it in the MS 109 is in consideration of the case where there are a plurality of IPs 105.
Even if a service signal external interrupt is generated in an IP other than the IP 105 that issued the VACTL 201, the IP1
This is because 05 reads the HSW 303 and writes it in the prefix area of the MS 109 with the real address so that the HSW 303 can be stored in the real address address common to all IPs.

304 in HSW303 is HCW2
02 is the same as that designated by the SOP 203. However, (FFFF) ₁₆ is stored at the time of an asynchronous service signal external interrupt from the SVP 102 that is not related to the requested operation of the HVACTL 201. 305 is the same as that designated by the HDID 204 of the HCW 202. 306
Indicates the operation completion status byte (HSTA). Here, (0400) ₁₆ means normal termination, (8000) ₁₆ means attention interrupt from the CD 103, and other means abnormal termination. 307 is HCW202
Indicates the remaining number of bytes (RCNT) when the number of bytes of the data actually transferred is smaller than the transfer byte designated by the CNT 206.

FIG. 4 shows a virtual machine instruction (HVACTL).
And the processing flow of the completion interrupt and the asynchronous interrupt of the SVP 102 are collectively shown.

401a is an instruction for the virtual computer, that is, HV
This is the starting point of the microprogram in the IP 105 when the ACTL 201 is issued. 405a is SVP10
2 is the starting point of the processing request by the HVACTL 201, and 405b is the starting point of the processing by the asynchronous attention from the CD 103. Reference numeral 412a is the starting point of the microprogram in the IP 105 due to the service signal external interrupt from the SVP 102. In this embodiment, HVA
Both the SVP 102 completion interrupt for the CTL operation request and the asynchronous interrupt from the CD 103 are served by the service signal external interrupt.
It is done by OP304.

When the HVACTL 201 is issued, the IP 105 determines the H bit 301 of the LS 106 (step 401), and when the H bit 301 is 0, that is, in the virtual computer mode, the HVACTL 201 is an instruction exception. This is the HVA other than the virtual machine mode.
The purpose is to guard the use of CTL 201. When the H bit 301 is 1, that is, in the virtual computer mode, IP
Reference numeral 105 denotes fields B2 and D of the HVACT 201.
After the HCW address 302 is generated by 2 and set in the LS 106 (step 402), a processing request signal is sent to the SVP 102 via the SVU 107 (step 40).
4). This completes the processing of the HVACTL 201 in the IP 105.

When the SVP 102 receives the processing request from the IP 105, the SVP 102 sends the HC request from the LS 106 via the SVU 107.
The W address 302 is read and the HCW address 302 is read.
Is determined to be 0 (step 405). And H
If the CW address 302 is 0, another SVP process that has been conventionally used is executed. That is, the HCW address 302 of the LS 106 is guaranteed to be 0, except for that by the HVACTL 201. HCW address 302 is 0
Otherwise, SVP 102 is SVU 107, SC10.
MS10 indicated by the HCW address 302 via
Fetch the HCW 202 in 9 (step 406),
The processing indicated by the HCW 202 is performed by the MS 109 and the CD 10.
3 or HD 104 (step 40)
7). Then, the HCW address 302 of the LS 106 is 0
Clear (step 408). This step 408
Indicates that the next SVP processing request is HVACT201.
This is to prevent the determination in step 405 from malfunctioning except in the case of. SVP102 is HC
When the process indicated by W202 is executed, the execution result state is set in the HSW 303 of the LS 106 (step 40
9), a completion interrupt of HVACT 201 is generated as a service signal external interrupt for the IP 105 (step 411). With this, SVP by HVACTL201
The operation of 102 is completed.

On the other hand, when there is an attention request from the CD 103, the SVP 102 makes the SOP 304 (FFF) of the HSW 303 identify the asynchronous interrupt.
F) ₁₆ is set (step 410) and a service signal external interrupt to the IP 105 is generated (step 41).
1). At this time, (8000) ₁₆ is simultaneously set in the HSTA 306 of the HSW 303. This is because the asynchronous interrupt is only the attention request from the CD 103 in the present embodiment, but if another one is needed in the future, H
A value other than (8000) ₁₆ is set in the STA 306 to discriminate.

The IP 105 transmits the SVU1 from the SVP 102.
When a service signal external interrupt is received via 07, LS
The state of the H bit 301 of 106 is determined (step 41
2) When the H bit 301 is 0, normal service signal external interrupt processing is executed (step 416). LS1
If the H bit 301 of 06 is 1, the contents of the HSW 303 are checked (step 413), and if it is 0, the routine also branches to normal service signal external interrupt processing. this is,
It is also intended to process a service signal external interrupt other than the completion interrupt and the attention request asynchronous interrupt by the HVACT 201 without malfunction.

When the H bit 301 of LS 106 is 1, HS
If the content of W303 is not 0, IP105 is LS10
The HSW 303 is read from 6 and stored in a fixed address (prefix area) on the MS 109 (step 41).
4). Then, the HSW 303 of the LS 106 is cleared to 0 (step 415). This is to prevent the determination in step 413 from malfunctioning when a subsequent service signal external interrupt occurs.

Next, the processing method of the control program (hereinafter referred to as the hypervisor) in this embodiment will be described with reference to FIG.

In FIG. 5, reference numeral 501 denotes a monitor of a hypervisor, which manages hardware and controls other parts. A frame 502 manages an instruction from the CD 103 to the hypervisor by the operator and a message display on the CD 103 of the hypervisor. Reference numeral 503 is a virtual computer on which a guest operating system operates. The monitor 501, the frame 502, and the virtual computer 503 are placed on the MS 109.

Reference numeral 501a denotes HVACT from the monitor 501.
L201 shows the activation of the SVP 102, 501b shows the dispatch of the frame 502 by the LPSW instruction of the monitor 501, and 501c shows the dispatch of the virtual machine 503 by the SIE instruction of the monitor 501. 50
2a is a monitor 501 according to the SVC command of the frame 502
503a indicates an interception of a SIE instruction for simulation by the monitor 501. Reference numeral 503b indicates a timer interrupt for time slice processing, and 504a indicates a service signal external interrupt. Where 501a and 504
a is added in place of the conventional input / output device processing by the present invention.

Now, when the operator inputs a command to the hypervisor on the CD 103, the SVP 102 sends 50
It is reported to the monitor 501 by 4a (asynchronous interrupt). The monitor 501 issues HVACT 201 to the monitor 501, requests the SVP 102 to read the input information from the CD 103 by 501a, and completes the operation 504.
When it is known by a (completion interrupt), the frame 502 is dispatched by 501b, and the frame 502 is made to perform processing according to the input instruction. When the frame 502 needs to output a message to the CD 103 as a result, the frame 502 notifies the monitor 501 of the message output. The monitor 501 issues the HVACTL 201, requests the SVP 102 to output a message to the CD 103 by 501a, and reports the operation completion by 504a.
The frame 502 is again dispatched by 01b, and the message output completion is reported to the frame 502.

When data is to be saved when a failure occurs, the saved data is written to the HD 104 in the same manner as above.

Incidentally, 501c, 503a and 503b are S
Since it is the same as the processing method of the conventional virtual machine using the IE instruction, its explanation is omitted.

FIG. 6 shows the HD 104 file and the MS 10
9 shows the correspondence at the time of loading to 9 above. 601-
Reference numeral 604 denotes a non-volatile file in which the HD 104 is divided. Reference numeral 601 denotes a file in which the initial loader of the hypervisor is stored (HYLOAD), and 602 is a file in which the normal processing unit of the hypervisor is stored (HYCO).
A), 603 is a file for saving control information of the hypervisor (HYCTL), and 604 is a file for collecting a failure analysis dump of the hypervisor (HYDUMP). In this embodiment, an operating system including address constant relocation parameters is used. It is a load module format.

Reference numerals 605 to 608 show the structure of the MS 109 after the hypervisor is loaded. Reference numeral 605 denotes a PSW (starting PSW) for transferring control to the hypervisor first.
HYLOAD 601 is loaded up to 8 bytes from the absolute address 0 of MS109. An area (SUA) 606 is for a virtual computer such as a guest operating system. That is, the startup PSW 605 is the SUA.
It is placed at the beginning of 606. An area (EHSA) 607 is composed of an area in which the HYCOA 602 is loaded and a work area used by the hypervisor. The guarding of access from the program on the SUA 606 of the EHSA 607 is performed by the hypervisor by software using the function of the SIE instruction. Therefore, the EHSA 607 looks like an unusable area to the guest operating system. Reference numeral 608 denotes an area (HSA) used by hardware, and the hypervisor cannot use the HSA 608.

According to the present invention, the initial loader of the HYLOAD 601 in the HD 104 is automatically loaded into the MS 109 by the SVP 102, and the EHSA 607 is loaded into the HVAC by the initial loader.
It is automatically loaded by HYCOA 603 using TL201. Therefore, the operator cannot see the existence of the hypervisor, but only the unusable area of the program is increased by the amount of EHSA607.

FIG. 7 shows a processing flow for activating the hypervisor when the reset operation is performed on the CPU 101. Reference numerals 701 to 703 are conventional reset operations, and reference numerals 704 to 712 are processings added by the present invention.

The SVP 102 is composed of the SVU 107 and the IP10.
5. Reset operation such as loading a microprogram to the IOP 110, sending a hardware reset signal, etc. (step 701), clearing the contents of the MS 109 to 0 (step 702), and initializing the HSA 608 (step 703). . After that, the virtual computer mode is determined (step 704), and only in the virtual computer mode, the additional processing of the present invention after step 705 is performed. Here, the virtual computer mode is designated by the operator.

In the virtual machine mode, the SVP 101
First, the H bit 301 of the LS 106 is set via the SVU 107 (step 705). By setting the H bit 301, the microprogram can also determine the virtual computer mode thereafter. Next, SVP101 is SVU107, SC108
HYLOAD601 of HD104 to MS10 via
Load from absolute address 0 of 9 (step 70)
6). Then, the startup PSW 605 in the loaded HYLOAD 601 is set to the PSW of the IP 105 (step 707), and the IP 10 is set by the set PSW.
The instruction execution process of No. 5 is started (step 708). This starts the initial loader of the hypervisor.

The initial loader of the hypervisor is HV
The ACTL 201 instructs the SVP 102 to perform an operation request, and loads the HYCOA 602 of the HD 104 into the EHSA 607 of the MS 109 (step 709). Next, the address constants of the EHSA 607 are rearranged according to the address constant rearrangement parameters included in the HYCOA 602 (step 710). This is HYCO in the same format as a program on a normal operating system.
This is so that the A602 can be programmed. Next, HYCOA60 loaded in step 709.
Control is passed to the normal processing unit of the hypervisor in step 2 (step 711), and the SUA 606 is cleared to 0 to erase the initial loader in the SUA 606 that is no longer needed (step 712). After this, the hypervisor is shown in Figure 5.
The normal processing is as described in.

[0044]

As described above, according to the present invention , a logical communication means is provided between the control program (hypervisor) and the service processor , and the control program is assigned a specific instruction.
More like an I / O channel to the service processor
Request the operation of the service processor, and the service processor follows the instruction.
It is possible to operate the virtual machine by using the console device and non-volatile storage device provided in the service processor by performing the specified input / output operation. Therefore , special input / output for controlling the control program etc. Prepare the equipment,
It is possible to realize a virtual computer system that does not need to be defined in the control program.

[0045] In the present invention, it is possible to automatically start the control program by a service processor, an operator can be realized a virtual computer system of easy operations need not be aware of the hypervisor.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment of a virtual computer system to which the present invention is applied.

FIG. 2 is a diagram showing the format of a virtual machine instruction used in the present invention.

FIG. 3 is a diagram showing a format and usage of a local storage.

FIG. 4 is a diagram showing a processing flow of instructions for a virtual computer and a service processor.

FIG. 5 is a diagram showing a processing method of a control program (hypervisor) according to the present invention.

FIG. 6 is a diagram showing correspondence between files in a nonvolatile storage device and main storage.

FIG. 7 is a diagram showing a processing flow when the processing device is reset.

[Explanation of symbols]

 1 Central Processing Unit 102 Service Processor 103 Console Device of Service Processor 104 Nonvolatile Storage Device of Service Processor 105 Instruction Processing Processor 106 Local Storage 107 Service Processor Communication Unit 108 Main Storage Controller 109 Main Storage 110 I / O Processing Unit 201 For Virtual Machine Instruction 501 Monitor 502 Frame 503 Virtual machine

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayuki Sano, 1 Horiyamashita, Hadano City, Kanagawa Prefecture, Hitachi Computer Engineering Co., Ltd. (56) References JP 63-268035 (JP, A) JP 61- 288231 (JP, A) JP-A-1-204167 (JP, A) JP-A-1-103745 (JP, A) JP-A-2-109148 (JP, A) JP-A-3-6739 (JP, A) Yamatani, Akiyama, co-author, "Virtual Machine", Kyoritsu Shuppan Co., Ltd. (first edition in 1978), p. 34 to 39

Claims (3)

(57) [Claims] 1. A virtual computer system comprising a processing device and a service processor for performing maintenance operations of the processing device, wherein a virtual computer operates on the processing device under the control of a control program. Rutotomo provided logical communication means between the service processor
The control program to the service processor.
A virtual computer instruction requesting an operation is provided , and the control program instructs the virtual computer to operate under the condition of the virtual computer mode.
Instructing an operation request to the service processor by an order ,
In response to the instruction, the service processor performs the virtual calculation.
A virtual computer system having a function of executing a process based on a machine instruction and notifying the control program of an operation completion by an interrupt. 2. The service processor is provided by itself.
Command from the console device to the control program
To the virtual total from the control program
Based on the computer instructions, the main memory of the processor and the console
By transferring the information between the storage units,
Display these messages on the screen of the console device
The virtual computer system according to claim 1, characterized in that . 3. A reset operation is performed on the processing device.
Service processor, the service processor
Mainly describes the control programs stored in advance in the volatile storage device.
After loading it into memory, a part of it is stored in the processor program.
Set the status word (PSW) and start the control program
The virtual computer system according to claim 1, characterized in that
M