JPH11161523A - Fault information gathering device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently gather and analyze fault information by starting an interruption in response to a report on the lapse of a specified time by a counter and copying data in an image memory to a backup area of a main memory by the interruption. SOLUTION: The connection of a reset/interruption changeover switch 108 is initialized to the side of an interruption control circuit 107. If some fault is detected in hardware or software during operation, a fault interruption is initiated to an interruption control circuit 107, which once receiving the fault interruption, issues a low-level interruption(INTA) to a processor 102 through a system bus 104 and makes a timer 116 to start counting. Then a fault information gathering program corresponding to the INTA process is started on the OS and the information in the image memory 113 is saved in two image memory backup areas of the main memory 103. Then the said timer 116 having started counting counts up, the interruption control 107 issues an unmasked interruption NMI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to collecting fault information of a computer system having a graphical user interface, and more particularly to collecting screen information when a fault occurs.

[0002]

2. Description of the Related Art In a computer system requiring high reliability and operation rate, when it becomes difficult to continue processing due to some failure, main memory and main register information are stored as log information, and the cause is promptly investigated. It is used as analysis data to make it possible. Generally, output information to a display device connected to the computer system is also stored in a log file as a display history. When this display device is a system having only a character (character) display function, the amount of information displayed on a screen is limited, but a recent graphical user interface (Graphical User Interface) is used.
With the development of ce (hereinafter, referred to as GUI), display devices have been replaced with those having a high-definition graphic display function from conventional character-based devices, and the amount of information output to the display device has become extremely large. ing. In addition, since the output information is not only text information, logging of the display history alone is becoming insufficient as analysis information.

Therefore, as a technique for directly collecting screen display information, there are techniques described in Japanese Patent Application Laid-Open Nos. 1-241638 and 7-182208. These output the screen data output to the console to the video tape recorder, record the screen image displayed on the CRT of the console as it is, and reproduce the video tape later to display the entire console screen. Can be confirmed. According to these techniques, since the image actually displayed on the screen is stored as it is, it is an excellent method in that the operation state of the apparatus can be easily grasped. However, in actual operation, it is necessary to extract necessary information from a vast amount of constantly changing recording information, and a video tape recorder that is not involved in the original operation of the computer system is required Becomes

Therefore, a method of collecting the last display screen on the image memory in the form of image memory information when collecting the fault information when a fault occurs is conceivable. According to this method, a screen image can be collected without adding a device such as a video tape recorder.

[0005]

When a display screen at the time of failure occurrence is collected in the form of image memory information at the time of collecting the failure information at the time of the failure occurrence, the screen image that can be collected is the instantaneous image at the time of the failure information collection. Since there is only one screen, it is difficult to grasp the operation state immediately after the occurrence of the failure, and it is not possible to analyze a temporal change in the operation state of the processing device. Furthermore, it may not be possible to collect images depending on the progress of the obstacle.

An object of the present invention is to provide a means for efficiently collecting a change in fault screen information effective for fault analysis when a fault occurs.

[0007]

An object of the present invention is to provide two image memory save areas on a main memory and to generate a low-level interrupt and a high-level interrupt for a target processing device. This is achieved by providing a timer for managing the timing of the interrupt at predetermined intervals, and copying the data in the image display memory to the main memory by the low-level interrupt and the high-level interrupt.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an electronic computer according to an embodiment of the present invention. In the computer housing 101, a processor 102, a main memory 103, an input / output adapter 110, and a magnetic disk device 1 connected under the input / output adapter
11 and the like, and a system bus 10
4. The processor 102 can control the reset / interrupt changeover switch 106 by accessing the reset / interrupt changeover control register 105. Thus, when the forcible reset switch 109 is operated, which of the interrupt control circuit 107 and the reset control circuit 108 is activated is determined.
The interrupt control circuit 107 arbitrates an interrupt request from the processor 102, the input / output adapter 110, or the like, and transmits an interrupt signal to the processor 102. When the reset / interrupt switch 106 is set to the interrupt control side by the reset / interrupt switch control register 105, the signal from the forced reset switch 109 is input to the interrupt control circuit 107. The interrupt control circuit 107 is connected to the system bus 104
Through the low-level interrupt to the processor 102 (hereinafter, referred to as
INTA) and requests the timer 116 to start counting. When detecting an expiration of the timer 106, the interrupt control circuit 107 issues a non-maskable interrupt (NMI), which is the highest priority interrupt. On the other hand, if the reset / interrupt switch 106 is set to the reset control side by the reset / interrupt control register 105, a signal from the forced reset switch 109 becomes a reset request, and the reset control circuit 108 operates. A reset signal is issued to each device including the processor 102.

The CRT display 114 displays various information for the user who uses the computer. In particular, when a GUI is used, the amount of information displayed on a CRT display is enormous, and high-speed display is required. Therefore, display control is performed by a CRT controller 112 independent of the processor 102. Further, since a large amount of memory is required for this image processing, an image memory 113 dedicated to image display is prepared independently of the main memory 103.

FIG. 2 is an explanatory diagram of the interrupt processing in the configuration of FIG. The interrupt request generated in the processing device includes not only a fault but also a general interrupt requesting the processor 102 to perform processing at a specific time or event. In the present embodiment, a severe fault requiring collection of fault information is performed. Target interrupts. These fault interrupts are ORed and then input to the interrupt level determination circuit 211 (20
1).

Upon receiving a failure interrupt, the interruption level determination circuit 211 turns on an interrupt request (IRQ) signal connected to the processor 102 (202), and also issues a low-level failure interrupt (here, Then IN
The interrupt number defined as TA)
02 is notified (203). Note that the INTA process needs to be an interrupt not involving the OS in order to prevent the OS from initializing the screen or switching to the error message screen and to collect information on the state immediately before the failure. At the same time, it instructs the timer 116 to start counting (204). Processor 102 is INT
When the issuance of A is confirmed, the execution of the program is started by referring to the execution start address of the processing program corresponding to INTA from the interrupt vector table 212 arranged on the main memory 103 (205).

Next, when the count-up interrupt of the timer 116 is input to the interrupt level judgment circuit 211 (206),
The interrupt level determination circuit 211 unconditionally issues an NMI to the processor 102 (207). Processor 102 is N
When the MI is received, the execution of the program is started with reference to the execution start address of the processing program corresponding to the NMI from the interrupt vector table 212 (208).

FIG. 3 is a time chart showing the processing of FIG. 2 in chronological order. Here, in the INTA process, the first image memory storage process executes
Via the T controller 112, the image data is saved in the save space on the main memory 103, and the second image memory saving process is similarly performed in the NMI process. Therefore, as shown in the figure, the timer count time of the timer 116 from the INTA to the generation of the NMI due to the failure interrupt is INTA.
In order to suspend the processing and not execute the NMI processing, IN
It can be seen that the execution time of the interrupt program process executed by the TA needs to be sufficiently longer than the execution time.

In this manner, by issuing the information collection trigger in two stages, the screen image at the time of detection of the failure and the screen image after a while from the occurrence of the failure are saved,
By comparing these, it is possible to confirm a change in the screen display at the time of failure. Further, even in the worst case, even if a situation occurs in which the screen information is changed by the NMI due to a failure, the screen information is saved by the first trigger.
A screen image near the failure occurrence can be reproduced.

FIG. 4 is a flowchart showing a procedure for collecting information when a failure occurs in this embodiment. This flowchart is divided into three parts, namely, processing by hardware, processing by the OS, and processing by the operator for each part that handles the processing.

When the power of the computer is turned on, first, a hardware diagnosis and initialization are performed (step 40).
1). In an initial state immediately after the power is turned on, the reset / interruption switch 106 is always initialized to the reset control circuit 108 side. This is because the OS is not operating at this stage, and the failure information collection (auto save program) cannot be executed. It is checked whether a diagnostic error has occurred during this diagnosis (step 402), and if any failure is detected, the system stops processing. When performing the hardware diagnosis / initialization again from this state, the operator performs a forced reset by operating the forced reset switch 109 (step 405). On the other hand, if the hardware diagnosis / initialization is successful, the OS boot process is executed (step 403). It is checked whether or not the OS boot has succeeded (step 404). If the boot of the OS has failed, the system stops the processing in the same manner as the failure detection during the hardware diagnosis. If it is desired to start the system again from this state, a forced reset by the operator is also performed (step 405).

When booting the OS, the memory / register auto-save program is executed to collect fault information.
Is loaded onto the main memory 103. After recognizing the completion of the loading of the program, the OS accesses the reset / interrupt switching control register 105,
The connection of the interrupt switch 106 is initialized to the interrupt control circuit 107 (step 406). Thereafter, the system enters a normal operation state.

If any fault is detected in the hardware or software during operation, a fault interrupt occurs in the interrupt control circuit 107. When the interrupt control circuit 107 receives this fault interrupt, the interrupt control circuit 107 Issues a low-level interrupt (INTA),
At the same time, the timer 116 starts counting (step 407).

In the OS, a failure information collection program corresponding to the INTA process is started, and information in the image memory 113 is stored in the main memory 103 (step 40).
8).

Next, when the timer 116 which has started counting in step 407 counts up, the interrupt control circuit 107 issues an NMI (step 410).

When the processor 102 detects the NMI,
As processing corresponding to the NMI, the execution of the auto save program of the memory / register loaded on the main memory together with the OS is started. The auto save program reads the image memory area in the same manner as in step 408, and further saves all the main memory / register areas that can be referred to by the processor 102 in the magnetic disk device 111 (step 411). After completing the processing by the auto save program, the OS accesses the reset / interrupt switching control register 105, changes the connection of the reset / interrupt switch 106 to the reset control circuit 108 side, and restarts the system. Is performed (step 412).

As a means for coping with a case where a failure cannot be detected by the processing apparatus itself, there is a method of operating the forced reset switch 109 at the discretion of the operator.
By operating the forced reset switch 109,
The processing after step 407 is executed in the same manner as when a failure is detected by the processing apparatus itself (step 409).

FIG. 5 shows that the main memory 1 is stored in the image memory 113.
FIG. 11 is an explanatory diagram of a method of saving data to 03. The computer has a main memory 103 of several kilobytes to several hundreds of megabytes depending on its use. On the other hand, the image memory 113 is equipped with several megabytes independently of the main memory in accordance with the recent trend toward higher definition of CRT display and advanced GUI.
In this figure, it is assumed that the main memory is 32 MB and the image memory is 2 MB. In the main memory, a free area of 4 megabytes is reserved in advance as two work areas for storing image memory information (image memory copy area A501 and image memory copy area B502). In this embodiment, it is assumed that two image memory copy areas are allocated to the uppermost space of the main memory. The image memory copy area A501 is used for the processing of step 408 in FIG. 4, and the image memory copy area B502 is used for the processing of step 41 in FIG.
1 is used for image memory copy processing in the auto save program.

The image memory 11 is located in the main memory space.
An image memory image space 503 is secured as a window for accessing the image memory 3. In this image memory image space, the processor 102 can be accessed similarly to the main memory. In the present embodiment, this image memory image space is mapped to one page in the image memory space. Which area in the image memory is to be referenced from the image memory image space is determined by the value of the page control register 504 of the CRT controller 112. The CRT controller 112 manages the image memory 113 as pages in units of 128 kilobytes.
The address of the image memory 113 that can be referred to from the image memory image space is converted in accordance with the value set to “04”. In the fault information collection program, by switching the page control register 504, pages mapped to the image memory image space are sequentially switched, and information of the entire image memory space is collected by referring to the image memory image space.

It should be noted that all the image memories 113 are stored in the main memory 10.
3 saves the screen display information in the image memory 1.
In the case of a system in which a plurality of screens are held on the screen 13 and switched and displayed as needed, back screen information that is not actually displayed on the screen can also be collected.

FIG. 6 is a flowchart showing the contents of the primary image memory storage processing in step 408 of FIG. When the primary image memory storage process is started, the CR
Initialize the page control register 504 of the T controller 112 so that the image memory space page 0 can be referenced from the image memory image space 503. Also, the copy destination address pointer of the image memory is initialized to point to the head of the image memory copy area A501 (step 60).
1). Then, the image memory space 128 kB which can be referred to from the image memory image space 503 is copied to the image memory copy area A501 (step 602). At this time,
The copy destination address pointer is also incremented by 128 kB. Then, it is determined whether the page copied in step 602 is the last page of the image memory 113 (step 603). If it is the last page, the interrupt program processing ends. If the copied page is not the last page, the page control register 50
4 is incremented (step 604), and step 6 is performed.
02 and the process is repeated.

FIG. 7 is a flowchart showing the processing contents of the secondary image memory storage and the auto save program in step 411 in FIG. When the processing of the auto save program is started, first, all registers in the processor 102 and information in the cache memory 115 are saved in the main memory (step 701).

Subsequently, the register values of the main peripheral hardware in the computer are read and saved in the magnetic disk device 111 (step 702). The value of the reset / interrupt switching control register 105 is also included in the save data.

In steps 703 to 706, data is copied from the image memory space to the main memory space in the same manner as in the primary image memory storage process of FIG. However, in this case, the copy destination address pointer is specified in the area of the image memory copy area B502 and executed.
If it is determined in step 705 that the copying of the last page has been completed, the auto save program saves the entire area of the main memory space in the magnetic disk device 111 and ends the processing (step 707).

FIG. 8 is an explanatory diagram of an interrupt process in another embodiment of the present invention based on the configuration of FIG.

The hardware configuration is basically the same as that of the previous embodiment. However, in the previous embodiment, the counting of the timer 116 was started by the input of the failure interrupt as a trigger, whereas in the present embodiment, a periodic timer 816 is provided instead of the timer 116, and does not depend on the failure interrupt.
When the processing device starts operation, the cycle timer 816 periodically issues a count-up interrupt to the interrupt level determination circuit 211 (601). Upon receiving the count-up interrupt from the cycle timer 816, the interrupt level determination circuit 211 turns on an interrupt request (IRQ) to the processor 102 (602) and simultaneously executes the system bus 1
The low-level fault interrupt (INTA) interrupt number is notified to the processor 102 via the server 04 (603). Processor 1
02 confirms the issuance of the INTA, refers to the execution start address of the processing program corresponding to the INTA from the interrupt vector table 212 arranged on the main memory 103, and starts the execution of the program (604). Here, the interrupt generation cycle from the cycle timer 816 is set to INT as in the example of FIG.
It is necessary to make the time sufficiently longer than the execution time of the A processing program.

Next, when a failure interrupt occurs during the operation of the processing device (605), the interrupt level determination circuit 211 unconditionally issues an NMI to the processor 102 (606). Upon receiving the NMI, the processor 102 also refers to the execution start address of the processing program corresponding to the NMI from the interrupt vector table 212 and starts executing the program (607).

FIG. 9 is a flowchart showing the processing of another embodiment according to FIG.

Steps 901 to 906 are performed in steps 401 to 406 in FIG.
Is the same as the processing of Next, in this embodiment, the period timer 8
Initialization is performed so that the 16 operation modes become the period timer (step 907).

During the subsequent operation of the processing apparatus, the period timer 81
Every time the 6 count-up interrupt occurs (step 9
08), the interrupt level determination circuit 211 outputs the low level interrupt (IN
TA) (step 909).

A failure information collection program corresponding to the INTA processing is started, and information in the image memory 113 is stored in the main memory 1.
03. At this time, the image memory copy area A501 in FIG. 5 is used as an image memory copy area A501 in FIG. 5 as a copy destination on the main memory 103, and every time image memory copy processing by INTA is started, the image memory copy area A501 is used. Is overwritten with new data (step 910).

Next, when a failure interrupt that requires collection of failure information occurs during the operation of the processing device, the interrupt level determination circuit 211 unconditionally issues an NMI (step 91).
2). When detecting the NMI, the processor 102 starts the execution of the auto-save program of the memory / register loaded on the main memory together with the OS as a process corresponding to the NMI as in step 411 in FIG. In the processing of the auto save program, the image memory copy area B502 is used as a copy destination of the image memory, as in FIG. 4 (step 913).

According to the above processing, in this embodiment, the image memory information collected last during the normal operation and the image memory information immediately after the occurrence of the failure are stored in the magnetic disk device 111.

The processing in step 914 is the same as the processing in step 412 in FIG.

As means for coping with a failure that cannot be detected by the processing apparatus itself, as in step 409 of FIG.
09 is also provided. By operating the forced reset switch 109, step 912 is executed.
Subsequent processing is executed in the same manner as when a failure is detected (step 911).

Further, by installing a dedicated processor called a service processor (hereinafter referred to as SVP) for monitoring a system fault instead of the main processor and collecting fault information when a fault is detected, more reliably. Image memory information can be collected.

FIG. 10 is a block diagram of an electronic computer according to another embodiment of the present invention. In this embodiment, the configuration of FIG.
A VP (Ser Vice Processor) board 1001 is added. The SVP board 1001 includes a reset / interrupt switch control register 105, a reset / interrupt switch 1
06, which is controlled by the SVP 1002. The SVP 1002 is a processor that executes fault monitoring and fault information collection in place of the processor 102. FIG.
In the embodiment shown in FIG. 7, when the system is started, the reset / interrupt changeover switch 106 is connected to the interrupt control circuit 107, and the interrupt control circuit 107
2. Interruption for starting fault information collection (INTA,
Or NMI) has been issued, but the SVP board 10
01, the connection destination of the reset / interruption switch 106 is the SVP 1002 itself, and the SVP 1002 periodically accesses the processor 102 and the main memory 103,
Monitor whether the system is working properly. If the SVP1002 determines that a failure has occurred during monitoring,
The fault information is collected by the fault information collection program stored in 003.

In the case of this embodiment equipped with SVP1002,
Even when a failure occurs such that the processor 102 cannot operate, the SVP 1002 controls the CRT controller 112 to copy the contents of the image memory 113 to the main memory 103, so that it is possible to collect screen information when a failure occurs. .

[0045]

As described above, according to the present invention, it is possible to extract only parts that are considered significant in failure analysis from image memory information in two types of interrupts managed by a timer, and to collect and analyze failure information. There is an effect that can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an electronic computer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an interrupt processing operation according to an embodiment of the present invention.

FIG. 3 is a time chart of an interrupt processing operation according to an embodiment of the present invention.

FIG. 4 is a flowchart of a failure information collecting procedure according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram of a data exchange method between a main memory and an image memory according to an embodiment of the present invention.

FIG. 6 is a flowchart of a primary image memory storage process in one embodiment of the present invention.

FIG. 7 is a flowchart of a detailed execution procedure of an auto save program according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating an interrupt processing operation according to another embodiment of the present invention.

FIG. 9 is a flowchart of a failure information collecting procedure according to another embodiment of the present invention.

FIG. 10 is a configuration diagram of an electronic computer according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 ... Computer housing, 102 ... Processor, 103 ... Main memory, 104 ... System bus, 105 ... Reset / interrupt switch control register, 106 ... Reset / interrupt switch, 107 ... Interrupt control circuit, 108 ... Reset control circuit 109, forced reset switch, 111, magnetic disk drive, 112, CRT controller, 113, image memory, 114, CRT display, 116, timer, 211, interrupt level determination circuit, 212, interrupt vector table, 501, image Memory copy area A, 502
... image memory copy area B, 503 ... image memory image space, 504 ... page control register, 1001 ... S
VP board, 1002 ... SVP.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihisa Nakamura 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor ▲ Yoshihiro Numa Masahiro Numa, Ibaraki Prefecture 5-2-1, Hitachi, Ltd., Omika Plant, Hitachi, Ltd. (72) Inventor Shigenori Kaneko 5-2-1, Omika-cho, Hitachi, Ibaraki, Japan Omika Plant, Hitachi, Ltd.

Claims (4)

[Claims] 1. A failure information collecting apparatus for an information processing apparatus, comprising: a processor, a main memory, an image display device, and an image control means for transmitting the contents of the image memory to the image display device as an image signal; And interrupt control means for generating a second interrupt, and a counter for measuring a predetermined time, and the main memory is provided with at least two save areas for saving the contents of the image memory. The interrupt control means generates a second interrupt by a notification of a lapse of a predetermined time by the counter after the first interrupt is generated upon detecting a failure of the information processing device, and each interrupt causes data of the image memory to be stored in the main memory. A failure information collection device, which is copied to a save area. 2. The fault information collecting apparatus according to claim 1, wherein said timer generates said first interrupt at a predetermined fixed cycle, and said content of said image memory is periodically generated by said first interrupt during normal operation. Is copied to a save area of the main memory, and when a failure occurs, the contents of the image memory after the failure is copied to the save area of the main memory by the second interrupt. 3. The fault information collecting apparatus according to claim 1, wherein the contents of said image memory by said first interrupt and said second interrupt are copied to a save area of said main memory on behalf of said processor. A fault information collecting device comprising another processor dedicated to processing. 4. The fault information collecting apparatus according to claim 1, wherein said first interrupt is a low-level interrupt, said second interrupt is a high-level interrupt, and is measured by said timer. The failure information collecting apparatus according to claim 1, wherein the predetermined time is longer than a time required for a process of copying the contents of the image memory to the save area of the main memory by the first interrupt.