JPH06222985A - Memory controller - Google Patents

Abstract

PURPOSE:To perform access from a host to a memory part in a short period of time. CONSTITUTION:A table part 19 is provided with a valid bit part 192 for showing relation between an instructed address from a host and a logical address of each memory block in a memory part 16 and identifying whether data are written in each memory block or not. An access control means 14a controls access from the host to the memory part 16 by converting the instructed address from the host to the logical address of the memory part while referring to the table part 19 when there is an access request from the host to the memory part 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device using a flash memory, and more particularly to rewriting control and garbage collection control thereof.

[0002]

2. Description of the Related Art A semiconductor disk device is a device which can be controlled at the same speed as a magnetic disk device or the like from the viewpoint of a host, and has no mechanical operation part, and therefore can be accessed at high speed. Conventionally, such a semiconductor disk device has been composed of a volatile memory chip and a battery for backing it up. However, since such a configuration is not completely non-volatile, the content of data cannot be guaranteed when the power is turned off for a long period of time.

However, in recent years, a flash memory, that is, a flash EEPROM, has been used as a nonvolatile memory chip.
(Hereinafter referred to as FEEPROM) has been put into practical use, and a semiconductor disk device using this chip has been actively developed. This FEEPROM is EE
PROM (electrically erasable, rewritable read-only
Memory), which can be electrically erased, can be program-written byte by byte, does not require a power supply, and can guarantee the contents of memory.

On the other hand, contrary to the above advantages, it has the following disadvantages. That is, since overwriting cannot be performed when writing to the memory, it is necessary to erase (write) data byte by byte (rewrite data). The unit to be erased here differs depending on the chip, but the mainstream is to erase on a chip-by-chip basis.

Next, a conventional nonvolatile memory device using FEEPROM will be described. FIG. 9 is a block diagram showing the configuration of a non-volatile semiconductor disk device as a conventional memory control device. In FIG. 9, reference numeral 1 is a non-volatile memory device (non-volatile semiconductor disk device), and 2 is a system bus for connecting the non-volatile memory device 1 to a host (not shown). The non-volatile storage device 1 is composed of a host interface unit 3, a processor unit 4, a processor memory unit 5, a memory unit 6, a buffer unit 7, and an internal bus 8. The host for the non-volatile storage device 1 refers to a host device such as a microcomputer.

The host interface section 3 is a section for performing interface control with the host, and is a processor section 4
Is a part that interprets a command from the host and controls the non-volatile storage device 1 to appear as a disk device. The processor memory unit 5 is a memory in which a program for controlling the operation of the processor unit 4 is stored. The memory unit 6 is a flash memory configured by FEEPROM and storing data and the like. Buffer section 7
Is a memory for temporarily saving the contents of the memory unit 6 before erasing the memory unit 6 when the memory unit 6 is overwritten with data. The internal bus 8 is a bus for connecting the constituent elements in the nonvolatile memory device 1.

FIG. 10 is an explanatory diagram logically showing the format of the data stored in the memory section 6. That is,
The format of the memory unit 6 includes a valid bit 91, a pointer unit 92, and a data unit 93, and these are collectively referred to as one frame. The valid bit 91 is a bit indicating whether or not data is written in this frame. For example, when the valid bit 91 is “1”, data writing is performed, and when the valid bit 91 is “0”, data writing is not performed.

The pointer section 92 is a pointer for storing the start address of the frame in which the new version of the data written in this frame is written. That is, when the head address of another frame is written in the pointer section 92, the data written in this frame is the old version, and the new version is written in the address indicated by the pointer section 92. Will be there. Further, the data section 93 is a data section in which write data from the host is stored.

Next, the operation of the non-volatile storage device 1 executing the overwrite process in response to a write request from the host will be described. FIG. 11 is an explanatory diagram showing a conventional memory configuration example at the time of rewriting. First, it is assumed that data is written in addresses (A, a) (B, a) to (A, m) of the memory section 6 as shown in (a) in the figure. Then, in this state, it is assumed that the host makes a write request for rewriting the data on (A, a). In this case, (A, a) cannot be overwritten (as described above, FEEPR
When the OM is overwritten, it is necessary to erase the data in the FEEPROM once), and a frame in which no data is written is searched based on the valid bit 91.

In the illustrated example, data is not written after the address (B, m), so data is written at the address (B, m). That is, the valid bit 91 of the frame of the address (B, m) is set to "1", and the data portion 93
Write the data to. At the same time, "m" is written in the pointer portion 92 of the address (A, a). This is the state of (b) in the figure.

Next, the operation of garbage collection executed when data is stored in all the memory units 6 of the non-volatile memory device 1 will be described. FIG. 12 is an explanatory diagram thereof. Now, let us consider a link relationship as shown in FIG. 4A as a process until data is stored in all of the memory section 6.
First, the data D is written in the address (A, a) of the memory unit 6 based on the write request from the host. afterwards,
The host again makes a write request to the frame at address (A, a). In this case, since the valid bit 91 is "1" as described above, a frame in which no data is written is searched for, and this is the address. (B, m). Therefore, the valid bit of the frame of the address (B, m) becomes "1", and the data D-1 which is a new version of the data D is written in the data section 93. Further, "B, m" is written as the link destination address in the pointer portion 92 of the address (A, a).

After that, the address (A,
When there is a write request in a), as in the above case, a frame in which no data has been written is searched for and the (C,
n). Therefore, the valid bit 91 of the address (C, n) is "1", the data D-2 is written in the data part 93, and at the same time, the pointer part 92 of the address (B, m) is written.
"C, n" is written as its link destination.

When garbage collection is performed in such a state, the frame of address (B, m) merely indicates a link relationship and has no meaning as data. Therefore, garbage collection erases this (B, m) frame.

As this processing, first, the address (A,
The data of the frame of a) is saved in the buffer unit 7,
On the buffer unit 7, the pointer unit 92 is rewritten as "C, n". At the same time, the address (B,
The data of the frame of m) and the frame of the address (A, a) are erased. After that, the data of the frame of the address (A, a) in which the pointer section 92 is rewritten is stored in the memory section 6
Write to the same address of. As a result, the link destination of the frame of the address (A, a) becomes the direct address (C, n) and the address (B, m) as shown in FIG.
Is a frame in which data can be written (the valid bit 91 is "0" in which nothing is written).

[0015]

However, the above-described conventional memory control device has the following problems. Since the rewrite control is executed in accordance with the pointer section 92 in the memory section 6, it is necessary to follow the link destination for the write request or read request from the host, and therefore the data in the memory section 6 for the request. It took me a while to get to. When performing the garbage collection, since it was executed after the data was written in all the frames (areas) of the memory unit 6, it is necessary to execute the garbage collection while executing the write request from the host. In that case, the end notification to the host was delayed.

The present invention has been made in order to solve the above-mentioned conventional problems, and shortens the time for rewriting data to the memory unit and can promptly notify the end of the write request from the host memory. An object is to provide a control device.

[0017]

According to a first aspect of the present invention, there is provided a memory control device comprising: a memory section composed of a flash memory including a plurality of memory blocks; and a host for making an access request to the memory section. A table unit having a valid bit unit for indicating the relationship between the instruction address and the logical address of each memory block and for identifying whether or not data is written in the memory block, and the memory unit from the host. Access control means for referencing the table section, converting an instruction address from the host into a logical address of the memory section and controlling access to the memory section when there is an access request to the memory section. It is characterized by that.

The memory control device according to the second aspect of the present invention has a memory section composed of a flash memory composed of a plurality of memory blocks, a table section indicating whether or not data is written in each memory block in the memory section, and preset. A threshold value, monitoring the data writing state of each memory block by referring to the table section, and when the number of data written blocks of the memory block exceeds the threshold value, the garbage of the memory section is It is characterized by comprising a garbage collection control means for performing collection.

A memory control device according to a third aspect of the present invention is provided in a memory section composed of a flash memory composed of a plurality of memory blocks and a host for making an access request to the memory section, and each memory block in the memory section. Table portion indicating whether or not the data is written, the number of memory blocks provided in the host for executing the write request of the host by referring to the table portion, and the data in the memory portion is not written. The number of memory blocks for executing the write request is compared with the number of remaining memory blocks, and if the number of memory blocks exceeds the number of remaining memory blocks, write processing is performed after garbage collection, and the write request is issued. The number of memory blocks for execution does not exceed the number of remaining memory blocks, and the memory unit When the added value of the number of data written blocks and the number of memory blocks for executing the write request exceeds a preset threshold value, write control means for performing garbage collection after performing write processing is provided. It is characterized by having.

The memory control device according to the fourth aspect of the present invention has a memory section composed of a flash memory composed of a plurality of memory blocks, a table section indicating whether or not data has been written to each memory block in the memory section, and is preset. A threshold value and a timer, monitoring the data write state of the plurality of memory blocks by referring to the table section, and if the number of data writes of the memory block does not exceed the threshold value, When the number of data writes in the plurality of memory blocks exceeds the threshold value, the timer is set and the timer is reset. However, if the timer is in the set state and the timer has elapsed a predetermined time, the garbage collection It is characterized in that it comprises a garbage collection control means for performing.

[0021]

In the memory control device of the first aspect of the present invention, when the host makes a read or write request to the memory section, the access control means refers to the table section and responds to the instruction address from the host. The logical address of the memory block to be fetched. Then, the access request process from the host is performed for the memory block of this logical address.

In the memory control device according to the second aspect of the present invention, when a write request is issued from the host, the garbage collection control means refers to the table section and executes the number of data written blocks of the memory block and the write request. It is determined whether the added value with the number of memory blocks exceeds the threshold value. If the added value exceeds the threshold value, garbage collection of the memory unit is performed.

In the memory control device of the third aspect of the present invention, the write control means of the host refers to the table section at a constant cycle or when a write request is issued. Then, the number of memory blocks for executing the write request of the host is compared with the number of remaining memory blocks in which the data of the memory section is not written, and the number of memory blocks for executing the write request is calculated as the remaining memory. If the number of blocks exceeds the limit, write processing is performed after garbage collection. In addition, the number of memory blocks for executing the write request is
If the number of remaining memory blocks is not exceeded, and the added value of the number of data written blocks in the memory section and the number of memory blocks for executing the write request exceeds the preset threshold value, Garbage collection is performed after write processing.

In the memory control device of the fourth aspect of the invention, when a write request is issued from the host, the garbage collection control means refers to the table part to check the data write state of each memory block. If the added value of the number of data written blocks of the memory block and the number of memory blocks for executing the write request from the host does not exceed the threshold value, the corresponding memory block is written and Set the timer.
On the other hand, when the added value exceeds the threshold value, the memory is garbage collected and the timer is reset. Further, the garbage collection is executed after the timer is in the set state and the predetermined time by the timer has elapsed.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a memory control device of the present invention. In the figure, 11 is a non-volatile memory device (non-volatile semiconductor disk device), and 12 is a system bus for connecting the non-volatile memory device 11 to a host (not shown). The non-volatile storage device 11 is
Host interface unit 13, processor unit 14, processor memory unit 15, memory unit 16, buffer unit 17,
It is composed of an internal bus 18 and a table section 19.
In the present embodiment as well, the host refers to a host device such as a microcomputer.

Here, the host interface unit 13 is
This is a part that controls the interface with the host as in the conventional case. The processor unit 14 is a unit that interprets a command from the host and controls the non-volatile storage device 11 to appear as a disk device, and includes an access control unit 14a. The access control means 14
A will be described later.

The processor memory unit 15 is a memory for storing a program for controlling the operation of the processor unit 14. The memory unit 16 is composed of FEEPROM,
As in the conventional case, it is for storing data. Further, the buffer unit 17 has, as its function, the memory unit 16
On the other hand, when the data is overwritten, the contents are temporarily saved before the memory section 16 is erased, and it is composed of a volatile memory chip such as a RAM. The internal bus 18 is a bus for connecting the constituent elements in the non-volatile memory device 11, as in the conventional case.

The table section 19 includes an EEPROM and an NVR.
It is composed of a rewritable nonvolatile memory such as AM, and is composed of an instruction address part 191, a valid bit part 192, and a logical address part 193. Instruction address part 19
Reference numeral 1 is a part indicating an address designated by the host when the host accesses data to the nonvolatile memory device 11. The valid bit unit 192 is similar to the conventional valid bit unit in that the corresponding memory unit 16
Is a portion indicating whether or not the data is stored in the memory block of No. 2, the data is written when the valid bit portion 192 is “1”, and the data is written when the valid bit portion 192 is “0”. It shows that there is no. The logical address unit 193 is a unit that logically converts the address designated by the host and determines the address of the memory block of the memory unit 16.

Further, the memory section 16 sets the access size (for example, sector unit) from the host as one block,
The table unit 19 has one word for one block of the memory unit 16. The memory section 16 is composed of an accessible area which is an area visible from the host and an alternative area which cannot be directly accessed from the host.

FIG. 2 shows the relationship between the structure of the memory section 16 and the table section 19. That is, the blocks of the memory unit 16 are
It consists of an accessible area and an alternative area.
Addresses "0" to "m-1" are set as accessible areas, and addresses "m" to "n" are set as alternative areas. In the table section 19 as well, table items are set corresponding to the number of memory blocks in the memory section 16.

Next, the operation of the non-volatile memory device 11 for executing the rewriting process in response to a write request from the host will be described. FIG. 3 is an explanatory diagram of the rewriting operation in the memory unit 16. In the illustrated example, from the host to the nonvolatile storage device 11
7 shows an operation description when a write access is performed a plurality of times to the area of address = 0. First, the host specifies address = 0 for the nonvolatile memory device 11. Thereby, the access control means 14a of the processor unit 14
Refers to the table section 19, the instruction address section 191 accesses one word "0", and inspects the corresponding valid bit section 192. Here, it is assumed that the valid bit is "0", and therefore the logical address portion 193
According to the address "0" of the memory section 16, the data is written in the block of the address "0" of the memory section 16 (indicated by the hatched portion in the figure). Then, the ballit bit portion 19 of the table portion 19
Set 2 to “1”. This state is the state shown in the figure.

Next, when the host makes a second write access request to the address = 0 of the nonvolatile memory device 11, the access control means 14a refers to the table section 19 as in the above write access. Then, the designated address portion 191 accesses one word of "0" and checks the valid bit portion 192. In this case, since the valid bit is set to "1" by the first write access, a block in which data is not written in the alternative area is searched. That is, in the table section 19, the designated address section 191 searches for a block in which the valid bit after "m" is "0".

Assuming now that the valid address of the "m" in the designated address section 191 is "0", the processor section 1
4 stores new data in the memory unit 16 according to the address of the logical address unit 193 (in this case, “m”).
The block is written in the block of the address "m" of the substitute area (indicated by the double-hatched line). And the access control means 14a
Rewrites the value of the logical address part 193 in the table part 19 with the address “m” which is the link destination. This state is shown in the figure.

Further, when there is a third write access request from the host to the address = 0 of the non-volatile memory device 11, the access control means 14a similarly performs the table unit 19a.
First, the instruction address portion 191 accesses one word of "0". This block, as described above,
Since the valid bit is "1", a block in which data is not written in the alternative area is searched for, as in the second write access. Now, assuming that the valid bit of "m + 1" in the designated address part 191 is "0", the access control means 14a determines the logical address part 1
According to the address of 93 (in this case, "m + 2"),
New data is written in the block (double shaded portion in the figure) at the address “m + 2” in the alternative area of the memory unit 16.

Then, the access control means 14a rewrites the value of the logical address part 193 in the table part 19 with the address "m + 2" which is the link destination. This state is shown in the figure.

When a read access request is issued from the host to the address = 0 of the nonvolatile memory device 11, the access control means 14a refers to the table section 19 and accesses the address of the logical address section 193. To do. For example, taking the state of FIG. 3 described above as an example, since the logical address of the address = 0 of the instruction address part 191 is “m + 2”, the access control means 14a uses the data of the address “m + 2” of the memory part 16. Read access. Therefore, it is not necessary to follow the link destination chain as in the conventional case, and the response time to the host can be shortened.

Next, the operation of garbage collection is shown in FIG.
Will be explained. First, considering the state of FIG. 3,
The data at addresses "0" and "m" in the memory section 16 are meaningless data. That is, the data at the addresses “0” and “m” are old data, and only the data at the address “m + 2” in the memory unit 16 is required as the data at the designated address = 0 from the host.

Therefore, when performing garbage collection, first, the addresses "0", "m", and
The data of “m + 2” is temporarily saved in the buffer unit 17. Then, while erasing the data of these addresses in the memory unit 16, erasing the data of the addresses “0” and “m” among the data saved in the buffer unit 17, the data of “m + 2” is stored in the memory unit 16 Write to the block of the address "0" in. At the same time, the address of the instruction address part 191 in the table part 19 =
The logical address of 0 is rewritten as “0”, and the valid bits of the address = m and m + 2 of the instruction address portion 191 are set to “0”. As a result, the memory unit 16
The data in the alternative area in is erased and the memory block in the alternative area becomes usable.

Next, second to fourth embodiments for performing garbage collection control will be described. FIG. 4 is a diagram showing the configuration of the second embodiment. In the illustrated apparatus, the processor section 14 is provided with a garbage collection control means 14b.
This garbage collection control means 14b has a preset threshold value, and when there is a write request from the host, it refers to the table section 19 and refers to the number of blocks in which data has been written and a memory for executing the write request. It is determined whether the added value of the number of blocks exceeds the threshold value. If the added value exceeds the threshold value, the memory unit 16
It has a function to execute garbage collection of.
The threshold value is set to an appropriate value, such as a value indicating 90% of the alternative area of the memory unit 16.

The garbage collection control means 14b is composed of a program stored in the processor memory unit 15, and the processor unit 14 reads these from the processor memory unit 15 and executes them.

Next, the operation of garbage collection according to the second embodiment will be described. FIG. 5 is a flowchart showing the control operation of the garbage collection control means 14b according to the second embodiment. Now, it is assumed that a write request is generated from the host and the non-volatile storage device 11 performs the write request process. In this case, first, the garbage collection control means 1
4b refers to the table unit 19 and indicates the number of written blocks in the alternative area of the memory unit 16 and the number of write request blocks from the host (the block of the overwrite request, that is, the number of blocks of data written in the alternative area). And add
It is determined whether or not the value is greater than or equal to the threshold value (step S
1). The number of written blocks in the memory unit 16 means the valid bit unit 192 in the table unit 19.
Indicates a block whose value is "1".

In step S1, if the added value is smaller than the threshold value, writing is performed on the block requesting the write to the alternative area (step S2). If the added value is larger than the threshold value, writing is performed. The possible block number (remaining block number) is compared with the write request block number (step S3). When the number of writable blocks is larger in step S3, the writing process is performed (step S4), and then the garbage collection process is performed (step S5). On the other hand, if the number of writable blocks is smaller in step S3,
First, a garbage collection process is performed (step S
6) After that, write processing is performed (step S7).

As described above, in the second embodiment, since the garbage collection control means 14b performs the garbage collection process based on the threshold value, the garbage collection process is executed while the write request from the host is being executed. You can avoid having to do it.

Next, a third embodiment in which the host side instructs the non-volatile memory device 11 to perform garbage collection will be described. FIG. 6 shows the configuration. In the figure, the configurations of the non-volatile memory device 11 and the system bus 12 are the same as those in the second embodiment except that the processor unit 14 of the non-volatile memory device 11 does not include the garbage collection control means 14b. The description is omitted.

In the figure, reference numeral 20 denotes a host which issues a read / write request to the non-volatile memory device 11 via the system bus 12, and has a write control means 21, a table section 22, and a write request queue 23. The writing control means 21
It is composed of a dedicated processor or program, has a predetermined threshold value, manages the table unit 22 and the write request queue 23, and when a write request is issued from the host 20, these table unit 22 and the write request queue 23. It has a function of controlling a garbage collection instruction and the like based on the number of write requests stored in.
The table unit 22 has the same configuration as the table unit 19 of the nonvolatile storage device 11 described in the first and second embodiments, and is a table showing the storage state of the memory unit 16 in the nonvolatile storage device 11. Also, the write request queue 23 is
When a write request is made to the non-volatile storage device 11, it has a function of storing the write request.

Next, the operation of the third embodiment will be described.
FIG. 7 shows a flowchart of the write request process of the host 20. First, the write control means 21 inspects the total number of blocks of write requests stored in the write request queue 23 at regular intervals or when a write request is generated. Further, the write block state of the alternative area in the memory unit 16 is checked with reference to the table unit 22. Then, the sum of the total number of blocks of these write requests and the number of written blocks is obtained, and it is determined whether or not the sum exceeds a threshold value (step S1).

In step S1, if the sum of the total number of blocks for executing the write request and the number of written blocks is smaller than the threshold value, the write processing is performed on the nonvolatile memory device 11 as it is (step S
2) If the sum is larger than the threshold value, the number of writable blocks (the number of remaining blocks) is compared with the total number of blocks for write requests (step S3).

In step S3, when the total number of blocks for executing the write request is smaller than the number of writable blocks, the write control means 21 first performs the write processing (step S4), and the nonvolatile memory device 11 side When the write end notification is received (step S5), next, a garbage collection process instruction is given (step S5).
6). On the other hand, in step S3, when the total number of blocks for the write request is larger than the number of writable blocks, the garbage collection process is first instructed (step S7), and the non-volatile storage device 11 notifies the end of the garbage collection. After receiving (step S
8) The writing process is performed (step S9).

As described above, in the third embodiment, since the host 20 side issues the garbage collection instruction of the memory section 16, the write operation is issued before the write request is issued to the memory section 16. It is possible to know whether the memory unit 16 can execute the request. Therefore, even if the write request is for many memory blocks, it is possible to prevent a situation in which the memory unit 16 has to perform garbage collection while executing the write request from the host 20. can do.

Next, a fourth embodiment in which the non-volatile memory device 11 periodically performs garbage collection will be described.
The fourth embodiment has the same structure as that of the second embodiment shown in FIG. 4, and therefore the illustration thereof is omitted, but the function of the garbage collection control means 14b is different. That is, the garbage collection control means 14b of this embodiment has the same threshold value as that of the second and third embodiments described above, and also has the timer function. Also, the usage status of the memory block in the memory unit 16 is monitored by referring to the table unit 19, and if the usage status of the memory block does not exceed the threshold value, the memory block is written and the timer is set. If the memory block usage exceeds the threshold,
Garbage collection of the memory unit 16 is performed and the timer is reset. Further, it has a function of executing garbage collection after the timer has been set and a predetermined time has elapsed.

Next, the operation of the fourth embodiment will be described. FIG. 8 shows a flowchart of the write request process in the fourth embodiment. First, when a write request comes from the host, the processor unit 14 adds the number of blocks writable in the memory unit 16 and the number of blocks of the write request, and determines whether or not this sum is equal to or more than a threshold value ( Step S
1). In step S1, if the sum is smaller than the threshold value, write processing is performed on the write request block (step S2), and then the timer for starting the garbage collection processing is set (step S3). . If the timer has already been set, the timer is reset (measurement is started from the initial value).

On the other hand, if the sum is greater than or equal to the threshold value in step S1, it is determined whether or not all the write request blocks can be written in the memory section 16 (step S4). If all the blocks can be written in the memory unit 16, write processing is performed (step S5), garbage collection is performed (step S6), and then the timer is reset (step S).
7). If all blocks cannot be written in the memory unit 16 in step S4, garbage collection is first performed (step S8), then write processing is performed (step S9), and then a timer is set. Reset (step S10).

Further, the garbage collection control means 14
b monitors the timer as described above, and when the timer counts the specified value, an interrupt (not shown) occurs, and the garbage collection control means 14b executes the garbage collection.

As described above, in the fourth embodiment, since the garbage collection of the memory section 16 is periodically performed, the end notification for the write request from the host can be performed with the same performance as that of the third embodiment. it can.

In each of the above embodiments, the threshold-based garbage collection is executed for the alternative area of the memory section 16, but the present invention is not limited to this, and it may be executed for the access area of the memory section 16. You may comprise.

[0056]

As described above, according to the memory control device of the first aspect of the present invention, the table section for indicating the relationship between the instruction address from the host and the logical address of the memory block is provided so that the host can control the memory section. When there is an access request from the host, the table part is referred to, the instruction address from the host is converted into the logical address of the memory part, and the access control to the memory part is performed. It is possible to promptly respond to the access request.

According to the memory control device of the second aspect of the present invention, the table indicating the presence / absence of data writing in each memory block in the memory unit is provided, and a predetermined threshold value is set in advance, and the data written block of the memory block is set. When the number exceeds this threshold, the memory part is garbage collected. Therefore, it is possible to prevent the garbage collection from being performed while the write request from the host is being executed. can do.

According to the memory control device of the third aspect of the invention, the host side is provided with a table section indicating whether or not data is written in each memory block in the memory section, and the host side refers to this table section to perform garbage collection in the memory section. Since the instruction is given, it is possible to know whether the memory unit can execute the write request before the host issues the write request to the memory unit. Therefore, the memory unit requests the write request from the host. It is possible to further prevent that garbage collection must be performed during execution of.

According to the memory control device of the fourth aspect of the invention, since the garbage collection of the memory part is periodically performed, the memory part executes the write request from the host to the same extent as the third invention. It is possible to prevent having to perform garbage collection during the operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory control device of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a memory unit and a table unit in the memory control device of the present invention.

FIG. 3 is an explanatory diagram of a data rewriting operation in the first embodiment of the memory control device of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the memory control device of the present invention.

FIG. 5 is a flowchart showing the operation of the second embodiment of the memory control device of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the memory control device of the present invention.

FIG. 7 is a flowchart showing an operation of a third embodiment of the memory control device of the present invention.

FIG. 8 is a flowchart showing the operation of the fourth embodiment of the memory control device of the present invention.

FIG. 9 is a block diagram of a conventional memory control device.

FIG. 10 is an explanatory diagram of a format of a memory unit in a conventional memory control device.

FIG. 11 is an explanatory diagram at the time of rewriting data in the conventional memory control device.

FIG. 12 is an operation explanatory diagram of garbage collection in the conventional memory control device.

[Explanation of symbols]

 11 non-volatile storage device 14a access control means 14b garbage collection control means 16 memory unit 19 table unit 20 host 21 write control unit 22 table unit

Claims (4)

[Claims] 1. A relationship between a memory unit configured by a flash memory including a plurality of memory blocks, an instruction address from a host that makes an access request to the memory unit, and a logical address of each memory block is shown. At the same time, a table unit having a valid bit unit for identifying whether or not data is written in the memory block, and when the host makes an access request to the memory unit, the table unit is referred to. A memory control device, comprising: an access control unit that converts an instruction address from the host into a logical address of the memory unit to control access to the memory unit. 2. A memory unit configured by a flash memory including a plurality of memory blocks, a table unit indicating whether or not data is written in each memory block in the memory unit, and a preset threshold value, A garbage collection control means for monitoring the data writing state of each memory block with reference to the table portion and performing a garbage collection of the memory portion when the number of data written blocks of the memory block exceeds the threshold value. A memory control device comprising: 3. A memory unit composed of a flash memory composed of a plurality of memory blocks, and a host that makes an access request to the memory unit and indicates whether or not data is written to each memory block in the memory unit. A table unit, the number of memory blocks that are provided in the host and refer to the table unit for executing the write request of the host, and the number of remaining memory blocks in which the data of the memory unit is not written. In comparison, if the number of memory blocks for executing the write request exceeds the number of remaining memory blocks, the number of memory blocks for executing the write process after performing garbage collection and executing the write request. Does not exceed the number of remaining memory blocks, and the data written block of the memory section And the number of memory blocks for executing the write request exceeds a preset threshold, a write control means is provided for performing garbage collection after performing write processing. And a memory control device. 4. A memory unit comprising a flash memory composed of a plurality of memory blocks, a table unit indicating whether or not data is written to each memory block in the memory unit, a preset threshold value and a timer. Then, referring to the table section, the data write states of the plurality of memory blocks are monitored, and when the number of data writes of the memory block does not exceed the threshold value, the write is performed to the plurality of memory blocks. Together with the timer in a set state, when the number of data writes of the plurality of memory blocks exceeds the threshold value, while performing garbage collection of the memory unit, reset the timer,
A memory control device comprising: garbage collection control means for executing garbage collection after the timer is in a set state and a predetermined time has elapsed by the timer.