JP3256116B2 - Smear correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a magnetic recording / reproducing apparatus, such as a VTR (video tape recorder), which emphasizes a high frequency range of a signal before magnetic recording and attenuates the high frequency range after reproduction. The present invention relates to a smear correction circuit suitable for application to

[0002]

2. Description of the Related Art When recording and reproducing a video signal with a VTR, the video signal is generally FM-modulated and recorded on a magnetic tape, and FM-demodulated during reproduction. At this time, the noise of the FM-modulated signal becomes triangular noise having a higher noise level as the frequency becomes higher in the video signal after the FM demodulation.

For this reason, conventionally, in order to reduce the triangular noise, a video signal is emphasized in a high frequency range (pre-emphasis), then FM-modulated and recorded on a magnetic tape.
After the M demodulation, high frequency attenuation (de-emphasis), that is, emphasis has been performed.

In this emphasis, the level is amplified in a portion including a high frequency component of a video signal in order to emphasize a high frequency range. If the level is too high, an overmodulation occurs when performing FM modulation, or a sideband of the FM-modulated signal spreads or becomes large, causing a failure.

[0005] In order to reduce this obstacle, clipping for limiting the amplitude of the pre-emphasized video signal is performed before FM-modulating the pre-emphasized video signal.
FIG. 3 shows a conventional analog clipping circuit. When the level of the input signal exceeds the voltage E, the diode D turns on and the level of the input signal is clipped to the voltage E.

However, if the clipped signal is FM-demodulated and FM-demodulated and then de-emphasized, the clipped signal does not return to its original waveform. This is observed as a phenomenon that the waveform becomes dull, and is called smear.

The generation of the smear will be described with reference to FIG. FIG. 4A shows a luminance signal which is a source for recording and shows about one horizontal period including a square wave.

FIG. 4B shows a waveform in which the waveform of FIG. 4A is pre-emphasized and an overshoot occurs. The upper and lower dotted lines indicate the level to be clipped,
When processed by the clipping circuit, the portion beyond the dotted line is clipped and disappears. FIG. 4C shows a waveform in which the area beyond the dotted line is clipped.

If deemphasis is performed without clipping, the waveform returns to the original waveform shown in FIG. 4A. However, if the clipped waveform shown in FIG. 4C is deemphasized, FIG.
And the smear occurs.

Japanese Patent Application Laid-Open Nos. Sho 62-36991 and 56-87778 disclose techniques for correcting the dullness of the waveform due to the smear during reproduction.

[0011]

However, when performing smear correction at the time of reproduction, it is not possible to determine whether the reproduced waveform is a dull waveform originally or a dull waveform due to clipping. Therefore, there is a problem in the reproducibility of the waveform in recording and reproduction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. At the time of recording, the energy of the waveform portion of the signal cut off by the clip is accumulated, and the signal level falls below the clip level. An object of the present invention is to provide a smear correction circuit for correcting the energy of a signal by adding energy previously stored to the signal.

[0013]

In order to solve the above-mentioned problems, a smear correction circuit according to the first aspect of the present invention emphasizes a high-frequency signal for recording on a magnetic tape and reproduces the signal from the magnetic tape. In the digital signal processing circuit of the magnetic recording / reproducing apparatus, which attenuates the high-frequency signal, the magnitude of the reference value is subtracted from the magnitude of the signal to be clipped, which is emphasized for recording on the magnetic tape, and the difference value And an integrating adder, a first switch, and a D flip-flop. The integrating adder adds the difference value and the output value of the D flip-flop, and 1 switch and integrating circuit for receiving the output value and zero value of the integrating adder selects and outputs either one to the flip-flop for the integrating outputs the output value of the D flip-flop, the object click < br /> lip signal and before An adder that adds the output value of the integration circuit, a second switch that receives the output value of the adder and the reference value, and selectively outputs one of the output value of the adder and the reference value; has a switch control circuit for controlling the first switch and the second switch, the switch control circuit, when (a) the smaller than the size of the magnitude reference value of the clip signal The first switch selects the zero value, the second switch selects the output value of the adder, and (b) the magnitude of the signal to be clipped is greater than the magnitude of a reference value. (C) the first switch selects the output value of the integrating adder, the second switch selects the reference value,
Wherein a case where the size of the clip signal is reduced from a larger state than the size of the reference value, and, if the difference value is input to the integrating adder is less than the output value of the D flip-flop , said first switch selects the output value of the integrating adder, said second switch selects said reference value, (d) the size than the size of the reference value of the clip signal In the case where the value has decreased from the large state and the difference value input to the integrating adder is larger than the output value of the D flip-flop, the first switch selects the zero value. , The second switch selects an output value of the adder.

According to a second aspect of the present invention, in the smear correction circuit, the switch control circuit inverts the sign of the output value of the first comparator for comparing the signal to be clipped with the reference value and the output value of the subtractor. A sign inverter to be output, a second comparator for comparing an output signal of the sign inverter with an output signal of the D flip-flop, and a NOR circuit which receives output signals of the first and second comparators as inputs. And switching of the first and second switches is controlled based on an output signal of the NOR circuit.

[0015] With the above configuration, smear correction circuit according to claim 1 of the present invention, when the size of the clip signal is less than the magnitude of the reference value, the clip signal is output. If the magnitude of the signal to be clipped is larger than the magnitude of the reference value, the reference value is output as the clip output, and the difference value during the clip output period is integrated into the D flip-flop. If the magnitude of the signal to be clipped is reduced from a state larger than the reference value and the input difference value is smaller than the output value of the D flip-flop, the reference value is still obtained. Is output. Then, it decreases from a larger state than the size of the magnitude reference value of the clip signal, and, if the difference value input is greater than the output value of the D flip-flop, of the clip signal and the D flip-flop The value obtained by adding the output values is output. Therefore, the difference value during the clip output period is integrated into the D flip-flop,
The clipped signal is complemented in the time axis direction after the end of the clip period, so that the waveform after de-emphasis is less blunt and smear is improved.

The smear correction circuit according to the second aspect of the present invention can realize the operation of the switch control circuit according to the first aspect.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, using the waveform of an analog signal (video signal) before A / D conversion shown in FIG. 2, how the smear correction circuit of the present invention performs waveform processing will be described.

FIG. 2A is the same waveform as FIG. 4B, and is a waveform in which the waveform of FIG. 4A is pre-emphasized and an overshoot occurs.

FIG. 2B is an enlarged view of an overshoot portion b of the waveform of FIG. 2A. A waveform 1-2-3 (-indicates a line segment) in the drawing is a waveform before being clipped by the clipping circuit. This waveform 1-2
In No. 3, the portion of the waveform 4-2-5 is cut off by the clipping circuit to obtain a waveform 1-4-4-5-3, and the recording / reproducing process is performed. This waveform 1-4-5-3 corresponds to waveform 4-
Since the energy of the portion 2-5 is lost, when de-emphasis is performed, the waveform does not return to the original waveform, but becomes the waveform shown in FIG. 4D, and smear occurs. Therefore, in the smear correction circuit of the present invention, a portion corresponding to the waveform 4-2-5 is integrated and complemented in the time axis direction. That is, the recording / reproducing process is performed by adding the waveform 5-6-7 to obtain the waveform 1-4-5-6-7-3. This reduces the dullness of the waveform after de-emphasis and improves smear.
In the integration of the above-mentioned waveform 4-2-5, in the embodiment of the present invention, integration is performed with the same value and complement is performed, but in other embodiments, integration is performed by multiplying by a predetermined coefficient, and the coefficient is integrated. Complement by multiplying by the corresponding coefficient.

FIG. 1 is a block diagram of a smear correction circuit according to an embodiment of the present invention. In this embodiment, processing is performed using a digital signal obtained by A / D converting a video signal. The smear correction circuit of the present embodiment has a clock frequency of 14 MHz.
Operates at z. Although the smear correction circuit according to the present embodiment performs clipping and correction in the positive direction, clipping and correction in the negative direction can be performed with a similar circuit configuration. Clip voltage data serving as a reference value for clipping is set and input by a clip voltage data setting unit such as a dip switch.

The clipped data obtained by A / D converting the video signal is inputted from an input A, and the clip voltage data is inputted from an input B.
Is entered from The comparator com1 outputs a result of comparing the clipped data with the clip voltage data. The subtractor sub1 outputs a result obtained by subtracting the clip voltage data from the clipped data. The D flip-flop dff1 latches the input data at the rising edge of the clock ck14 and outputs it as output data. The output of the subtractor sub1 is multiplied by -1 in the sign inverter mul1, and input to the comparator com2 together with the output of the D flip-flop dff1. The output of the subtractor sub1 is input to the adder add2 together with the output of the D flip-flop dff1. The adder add2 incorporates a circuit that sets 0 when the addition result is smaller than 0 and sets 511 when the addition result is larger than 511. The output of the adder add2 is supplied to the D flip-flop d via the switch sw1.
ff1. The adder add2 and the D flip-flop dff1 form an integrating circuit. D
The output of the flip-flop dff1 is added to the clipped data by the adder add1, and is output from the output C via the switch sw2. The NOR circuit NOR inverts and outputs the logical sum of the comparators com1 and com2, and outputs the output of the NOR circuit NOR to the inverter circuit N.
It is inverted by OT to control the switch sw2. In addition,
In the figure, the numbers attached to the connection lines represent the bit width of each line, those with a suffix to the number are represented by two's complement, and those with only the numbers are omitted by omitting the bits representing the positive and negative signs. Represents numbers only.

Next, the operation of the smear correction circuit will be described. Note that, as an initial state, the D flip-flop dff1
Is '0'. First, when the clip data is smaller than the clip voltage data, i.e. when the input x ₁ comparator com1 is smaller than the input y _1, the output z ₁ of the comparator com1 has a '0'. The output of the subtractor sub1 has a negative value. The output of the subtractor sub1 is a sign inverter mul1
Is multiplied by -1 to a positive value, and the comparator com2
Is input to the input x _2. D flip-flop dff1
(The output in the initial state is “0”)
It is input to the input y ₂ of om2. Output z ₂ at this time comparator com2 becomes '0'. Since the output z ₁ of the comparator com1 is '0', the NOR circuit NO
Both inputs of R become “0”, and as a result, the NOR circuit NO
The output of R becomes '1'. When the output of the NOR circuit NOR is "1", the switch sw1 is connected to the H side, and the output is always "0". The output of the NOR circuit NOR is inverted to '0' by the inverter circuit NOT, and
The switch sw2 is connected to the L side. As a result, the output of the D flip-flop dff1 and the clipped data are
The result added by the adder add1 is the result of the switch sw2
Via the output C. In this case, since the output of the D flip-flop dff1 is “0”, the clipped data is output from the output C as it is.

Next, when the data to be clipped is larger than the clip voltage data, that is, the comparator com1
If the input x ₁ is greater than the input y _1, the output z ₁ of the comparator com1 becomes '1'. Subtractor sub1
Outputs the difference between the clipped data and the clip voltage data (ie, the value cut off by the clip).
The output of the subtracter sub1 is a negative value is -1 times at sign inverter MUL1, is inputted to the input x ₂ comparators com2. The output of the subtractor sub1 is D
The output from the flip-flop dff1 is input to the adder 2. The output of the D flip-flop dff1 is input to the input y ₂ of the comparator com2. Output z ₂ at this time comparator com2 becomes '1'. Since the output of the comparator com1 is "1", the inputs of the NOR circuit NOR both become "1", and as a result, the output of the NOR circuit NOR becomes "0". When the output of the NOR circuit NOR is “0”, the switch sw1 is connected to the L side, and the output of the adder add2 is the D flip-flop dff
Connected to 1. As a result, the D flip-flop dff
The output of 1 is input again to the adder add2. That is, while the data to be clipped exceeds the clip voltage data, the excess value is integrated. NOR circuit NOR
Is inverted by the inverter circuit NOT to become "1", and the switch sw2 is connected to the H side. as a result,
Clip voltage data is output from the output C via the switch sw2.

Next, after which the clip data exceeds the clipping voltage data, if the clip data is smaller than the clip voltage data, output z ₁ of the comparator com1 again becomes '0'. Then, the value P of the difference between the clipped data and the clip voltage data is calculated by the comparator com.
Is input to the second input x _2. The value Q integrated by the D flip-flop dff1 while the clipped data exceeds the clip voltage data is calculated by the comparator com2.
It is input to the input y _2. When the value P is smaller than the value Q,
Output z ₂ of the comparator com2 is '1', and the so output z ₁ of the comparator com1 is '1', the output of the NOR circuit becomes "0". As a result, the switch sw
1 is connected to the L side, and the output of the adder add2 is connected to the D flip-flop dff1. Then, the value Q integrated by the D flip-flop dff1 decreases at the rate of the value P. During this time, the output of the inverter circuit NOT becomes “1”, and the switch sw2 is connected to the H side. As a result, the clip voltage data is output from the output C via the switch sw2.

When the value Q decreases and becomes smaller than the value P, the output z2 of the comparator com2 becomes '0',
Since the output z1 of the comparator com1 is '0',
The output of the NOR circuit NOR becomes '1'. Then, the output of the inverter circuit NOT becomes “ 0 ” and the switch sw2
Is connected to the L side, and the result of adding the output of the D flip-flop dff1 and the data to be clipped by the adder add1 is output from the output C via the switch sw2. Then, at the next clock input of clock ck14,
The value of the D flip-flop dff1 becomes '0' and returns to the initial state.

With the above operation, the portion of the waveform removed in the positive direction is complemented in the time axis direction. Further, with the same circuit configuration, similar clipping, integration, and complementing processing are performed on the waveform in the negative direction. This reduces the dullness of the waveform after de-emphasis and improves smear.

In this embodiment, the smear correction circuit is constituted by a digital circuit. In other embodiments, the smear correction circuit of the present invention is constituted by an analog clip circuit, an integration circuit and an addition circuit. .

[0028]

As described above, according to the present invention, the smear correction circuit according to claim 1 of the present invention accumulates the result scraped portions to clip the pre-emphasized signal, the portion of the stored signal Is the time axis after the clip period ends
Since the waveform is complemented in the opposite direction, the waveform after de-emphasis is less blunt and smear is improved.

The smear correction circuit according to the second aspect of the present invention can realize the operation of the switch control circuit according to the first aspect .

[Brief description of the drawings]

FIG. 1 is a block diagram of a smear correction circuit according to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams illustrating waveform processing of a smear correction circuit according to the present invention, in which FIG. 2A illustrates a waveform in which an overshoot has occurred, and FIG. 2B illustrates an enlargement of an overshoot portion b.

FIG. 3 is a diagram showing a conventional analog clip circuit.

4A and 4B are diagrams illustrating generation of smear, wherein FIG. 4A shows an original luminance signal, FIG. 4B shows a waveform in which an overshoot has occurred, FIG. 4C shows a clipped waveform,
(D) is a diagram illustrating a waveform in which smear has occurred.

[Explanation of symbols]

 com1 comparator com2 comparator sub1 subtracter add1 adder add2 adder dff1 D flip-flop mul1 sign inverter sw1 switch sw2 switch NOR NOR circuit NOT inverter circuit

Claims (2)

(57) [Claims] 1. A digital signal processing circuit of a magnetic recording / reproducing device for emphasizing a signal in a high frequency range for recording on a magnetic tape and attenuating a signal reproduced from the magnetic tape in a high frequency range, for recording on a magnetic tape. to subtract the magnitude of the reference value from the magnitude of the high enhanced the clip signal, comprising: a subtractor for outputting a difference value, the integrating adder, a first switch, and a D flip-flop, The integration adder adds the difference value and the output value of the D flip-flop, and the first switch receives the output value of the integration adder and a zero value as inputs and outputs one of the integration flip-flop. select output flop, an integrating circuit for outputting an output value of the D flip-flop, said an adder for adding the output value of the clip signal and said integration circuit, and said reference value and the output value of the adder Input and before A second switch that selectively outputs one of the output value of the adder and the reference value; and a switch control circuit that controls the first switch and the second switch. , wherein when the size of the clip signal is less than the magnitude of the reference value, the first switch selects the zero value, the second switch selects the output value of the adder, the When the magnitude of the signal to be clipped is greater than the magnitude of the reference value, the first switch selects the output value of the integrating adder, and the second switch selects the reference value. If the magnitude of the signal to be clipped has decreased from a state greater than the magnitude of the reference value, and if the difference value input to the integrating adder is smaller than the output value of the D flip-flop, The said If the switch selects the output value of the integrating adder, said second switch selects said reference value, said reduced from a larger state than the size of the magnitude reference value of the clip signal If the difference value input to the integrating adder is larger than the output value of the D flip-flop, the first switch selects the zero value, and the second switch selects the zero value. A smear correction circuit for selecting an output value of an adder. 2. A switch control circuit comprising: a first comparator for comparing a signal to be clipped with the reference value; a sign inverter for inverting a sign of an output value of the subtractor; A second comparator for comparing an output signal with an output signal of the D flip-flop, and a NO that receives output signals of the first and second comparators as inputs
The smear correction circuit according to claim 1, further comprising an R circuit, wherein switching of the first and second switches is controlled based on an output signal of the NOR circuit.