JP3254947B2 - Method for preventing destruction of internal diode of MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, in a high-frequency inverter, and uses MOSFETs as switching elements for upper and lower arms, and the output current to a load is always operated with a phase delay with respect to the output voltage. And a method for preventing breakdown of the internal diode of the MOSFET.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit diagram of a conventional inverter device. In FIG. 4, 6 is a DC power supply, 11 to 14 are MOSFETs, and 11a to 14a are MOSFETs 11 to 1.
Reference numeral 4 denotes a parasitic diode (hereinafter referred to as an internal diode), 10 is a control circuit, 7 is a current detector, 8 is a load having a configuration in which a reactor and a capacitor are connected in series, and 21 to 24 are backflow prevention diodes. , 31-34
Is a commutation diode.

The operation of the MOSFETs 11 to 14 is controlled by a gate signal from the control circuit 10, and the operation thereof will be described with reference to an operation waveform diagram of FIG. In FIG. 5, I _O indicates an output current of the inverter device flowing through the load 8, and V _O indicates an output voltage of the inverter device applied to the load 8. In FIG. 5, in section 51, MOS
The FETs 11 and 14 are in the ON state, and the current I _O is supplied from the DC power supply 6 → backflow prevention diode 21 → MOSFET11 → current detector 7 → load 8 → backflow prevention diode 24 → MOS
Flow on the route from FET 14 to DC power supply 6,
Gate signals to OSFETs 11 and 14 are off, MOSF
When the ETs 12 and 13 are turned on, the current _IO is applied to the DC power supply 6.
→ commutation diode 32 → current detector 7 → load 8 → commutation diode 33 → flows in the route of DC power supply 6 (current flowing through commutation diode is also called commutation current), and flows through commutation diodes 32 and 33. The current I _O attenuates to zero. In the next section 53, the current flows through the route of DC power supply 6 → backflow prevention diode 23 → MOSFET 13 → load 8 → current detector 7 → backflow prevention diode 22 → MOSFET 12 → DC power supply 6. In section 54, the gate signal to MOSFETs 12 and 13 flows. When the MOSFETs 11 and 14 are turned on, the current I _O is changed from the DC power supply 6 to the commutation diode 34 →
The current I _O flowing through the route of the load 8 → the current detector 7 → the commutation diode 31 → the DC power supply 6, and the current I _O flowing through the commutation diodes 31 and 34 attenuates to zero.

In a normal operation, by repeating the above sections 51 to 54, AC power having a cycle of section 50 is supplied to the load 8, and the control circuit 10 detects the load 8 based on a detection signal of the current detector 7. current I _O to the way is always phase lag with respect to the voltage V _O, and outputs a gate signal to the MOSFET11～14.

[0005]

In the above configuration, for example, a short circuit occurs over a part or all of the reactor constituting the load 8, the circuit constant of the load 8 changes suddenly, and the frequency of the current _IO is controlled. If the circuit 10 rises rapidly beyond the corresponding range, the following problem occurs.

[0006] current I when the frequency of the _O rises rapidly, the current I relationship _O and the voltage V _O is as shown in section 55 and 56 of FIG. 5, the current in the interval 55 I _O is the DC power supply 6 →
Backflow prevention diode 21 → MOSFET 11 → Current detector 7 → Load 8 → Backflow prevention diode 24 → MOSFET
14 → flow along the route of the DC power supply 6, and in the section 56, the DC power supply 6 → commutation diode 34 → load 8 → current detector 7
→ flows through the route of the commutation diode 31 → the DC power supply 6.

However, in the section 56, the switching of the MOSFET cannot respond to the sudden change in the frequency of the current I _O , so that the gate signal output from the control device 10 at a normal timing, that is, at a timing at which the commutation diode does not reversely recover, is used. 14 off, MOSFE
When T12 and T13 are turned on, commutation diode 31 → backflow prevention diode 32 → MOSFET for DC power supply 6
Twelve short circuits are formed, a steep reverse recovery current flows through the commutation diode 31, and a steep reverse recovery current also flows through the commutation diode 34, and the on / off timing is reversed. However, there is a problem that a steep reverse recovery current flows through the commutation diodes 32 and 33.

Therefore, conventionally, commutation diodes 31 to 34 are used.
In this case, an element having a structure robust against a steep reverse recovery current is used, and reverse current prevention diodes 21 to 24 are connected to the MOSFETs 11 to 14 so that an internal diode 1 of the MOSFET is connected.
1a to 14a were prevented from being destroyed by the steep reverse recovery current. According to the above configuration, M
Although the internal diodes 11a to 14a of the OSFET can be protected from destruction, it is necessary to connect two diodes to one MOSFET, and there has been a problem that the cost is increased and the configuration is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and when an inverter device is constituted by a MOSFET, an internal diode is connected to the commutation diode without connecting a diode outside the MOSFET. An object of the present invention is to provide a method for preventing the internal diode of a MOSFET from being destroyed so as to prevent the internal diode of the MOSFET from being destroyed.

[0010]

In order to solve the above-mentioned problems, in the first invention, an upper and lower arm composed of a MOSFET is connected to a DC power supply, and a load is connected to a connection point between the upper and lower arms. And the MOSFET is connected to this load.
A method for preventing the destruction of the internal diode of the MOSFET of the full-bridge or half-bridge inverter device, wherein the on-time of the full-bridge or half-bridge inverter device constantly outputs an alternating current having a phase delayed from the voltage to the load. The gate signal of the MOSFET is cut off when it is detected that the frequency becomes higher than a predetermined frequency.

According to a second aspect of the present invention, in the method for preventing destruction of an internal diode of a MOSFET, a zero-cross point of the output current is detected, and when the zero-cross point is detected earlier than a predetermined time, the gate of the MOSFET is detected. Cut off the signal. According to a third aspect, in the method for preventing destruction of the internal diode of the MOSFET, n times (n = 1, 2, 3,...) A half cycle of the operation of the inverter device.
Measuring the zero-cross point of the output current by one or more counters reset at any time each time,
The gate signal of the MOSFET is cut off when at least one measured value of the counter reaches n + 1 times during a period from the start of counting to resetting.

According to a fourth aspect of the present invention, in the method for preventing destruction of the internal diode of the MOSFET, at an arbitrary time point every n times (n = 1, 2, 3,...) A half cycle of the operation of the inverter device. The zero cross point of the output current is measured by a plurality of counters that are reset and reset timings are different from each other, and at least one of the counters reaches n + 1 times during a period from the start of counting to the reset. Sometimes, the gate signal of the MOSFET is cut off.

According to a fifth aspect of the present invention, in the method for preventing destruction of the internal diode of the MOSFET, the instantaneous value of the absolute value of the output current of the inverter device is set at a period sufficiently longer than the cycle of the frequency of the output current. Proportional to the peak value,
When it is detected that the comparison value to be followed has been exceeded, the MO
Cut off the gate signal of the SFET. In a sixth aspect of the present invention, in the method for preventing destruction of the internal diode of the MOSFET, the absolute value of the slope of the tangent of the output current of the inverter device is larger than the absolute value of the inverter device half a cycle before the switching operation. When the MOS is detected
Cut off the gate signal of the FET.

According to a seventh aspect of the present invention, in the method for preventing destruction of the internal diode of the MOSFET, the peak value of the absolute value of the output current of the inverter device is held at a period sufficiently longer than the period of the frequency of the output current. The absolute value is charged to a value obtained by subtracting the absolute value from the peak value, and the maximum value of the charged value is output to a zero value during a half period of the frequency of the output current. The gate signal of the MOSFET is cut off when it is detected that the added value exceeds a comparison value proportional to and following the peak value of the absolute value in a cycle sufficiently longer than the cycle of the frequency of the output current.

[0015]

According to the first to fourth aspects of the present invention, the gate signal of the MOSFET is turned on / off from the control circuit so that the output current to the load always has a phase delayed from the output voltage in the normal operation. The steep reverse recovery current does not flow through the internal diode of the MOSFET, and the circuit constant of the load changes abruptly, for example, when part or all of the reactor constituting the load is short-circuited, and the frequency of the output current decreases. In the case of a sharp rise, this is detected and the gate signals of all MOSFETs are immediately cut off.
Even if a reverse current prevention diode and a commutation diode are not added to the outside of the MOSFET as in the conventional example, a steep reverse recovery current does not flow and the inverter device stops and the MOSFET stops.
Is prevented from being destroyed by a steep reverse recovery current.

According to the fifth aspect of the present invention, the circuit constant of the load changes abruptly when a part or all of the reactor constituting the load is short-circuited, and the absolute value of the output current sharply changes. When the voltage rises, this is detected and the gate signals of all MOSFETs are immediately cut off. Therefore, even if a reverse current prevention diode and a commutation diode are not added to the outside of the MOSFET as in the conventional example, the temperature rises sharply. Inverter device stops without flowing reverse recovery current
Destruction of the FET due to a steep reverse recovery current is prevented.

Further, according to the sixth and seventh aspects,
When a part or all of the reactor constituting the load is short-circuited, the circuit constant of the load changes suddenly, and when the frequency or the absolute value of the output current rises sharply, this is detected. Since the gate signals of all MOSFETs are immediately cut off, the MOSFE
Even without adding a backflow prevention diode and a commutation diode to the outside of T, a steep reverse recovery current does not flow and the inverter device stops, thereby preventing the MOSFET from being damaged by the steep reverse recovery current.

[0018]

1 is a circuit diagram of an inverter device showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram showing the operation of FIG. In the following, components having the same functions as those in FIG. 4 are denoted by the same reference numerals, description thereof will be omitted, and components having different functions will be mainly described. Here, in FIG. 1, reference numeral 9 denotes a control circuit for controlling the inverter device.
Has a function of generating a zero-cross point signal (FIG. 2 (f)) indicating a zero-cross point of the inverter output current I _O shown in FIG. 2 (a), and one or more counters.

First, as a first embodiment of the present invention, a case will be described in which the control circuit 9 is provided with two counters A and B which are reset every half cycle of the inverter operation and have different reset timings from each other. The counters A and B convert the zero-cross point signal into the signals shown in FIGS.
Since the counters A and B are reset every half cycle of the inverter operation, they are normally reset by counting one zero-crossing point signal (count value 1), and the count value is "1". No 2 ".

Here, an abnormality such as a short circuit of a part or all of the reactor constituting the load 8 occurs, and the load 8
When the circuit constant changes suddenly and the frequency of the output current _IO sharply rises, the time from the zero crossing point immediately before the occurrence of the abnormality to the zero crossing point immediately after the occurrence of the abnormality becomes short, so that at least one of the counters A and B is used. The counter counts the second zero-cross point signal before the reset timing comes, and the count value becomes “2”.

When the count value of any one of the counters A and B becomes "2", the control circuit 9
All gate signal cutoffs (OF
F) to prevent a steep reverse recovery current from flowing through the internal diodes of the MOSFETs 11 to 14. According to the present invention, even when an abnormality occurs in the load 8 at the timing shown in FIG. 5, all gate signals to the MOSFETs 11 to 14 are cut off when the zero-cross point at the end of the section 55 is detected. , MOSFET11
Prevents a steep reverse recovery current from flowing through the internal diodes .about.14.

Next, as a second embodiment of the present invention, the control circuit 9 is reset every n times the half cycle of the inverter operation (here, when n = 2) and resets at two reset timings different from each other. The case where the counters C and D are provided will be described. FIG. 3 is an operation waveform diagram similar to FIG. 2, but the reset timing of the counter is different.
The waveforms of FIGS. 3 (i) and (j) are different from those of FIGS. 2 (g) and 2 (h). Since the counters C and D are reset at twice the half cycle of the inverter operation, the zero-cross point signal (FIG. 3 (f)) in the counters C and D is as shown in FIG.
As shown in (j), counting is performed up to “2” (up to n).

Here, an abnormality such as a short circuit of a part or all of the reactor constituting the load 8 occurs, and the load 8
When the frequency of the output current _IO rapidly increases due to a sudden change in the circuit constant of the above, the time from the zero-cross point immediately before the occurrence of the abnormality to the zero-cross point immediately after the occurrence of the abnormality becomes short, and at least one of the counters C and D is used. The counter counts the third zero-cross point signal before the reset timing comes, and the count value becomes "3", that is, "n + 1".

When the count value of one of the counters C and D becomes "3", the control circuit 9 sets the MOS
All gate signal cutoffs (OF
F) to prevent a steep reverse recovery current from flowing through the internal diodes of the MOSFETs 11 to 14. As described above, one or a plurality of counters that are reset at any time every n times a half cycle of the inverter operation are provided;
By providing one or a plurality of counters that are reset at any time every n times the half cycle of the inverter operation and have different reset timings, an abnormality such as a sudden increase in the frequency of the output current _IO can be prevented. MOS can be detected quickly regardless of the timing of the operation.
A steep reverse recovery current can be prevented from flowing through the internal diodes of the FETs 12 to 14.

FIG. 7 shows a third embodiment of the present invention in which the control circuit 9 includes an absolute value conversion circuit 91, a comparison value generation circuit 92 and a comparator 93 shown in FIG. This will be described below with reference to the operation waveform diagram of the circuit of FIG. That circuit in FIG. 6, the output of the absolute value conversion circuit 91 which converts the absolute value shown in FIG. 7 (b) the output current I _O shown in FIG. 7 (a), than the period of the frequency of the output current I _O A comparator 93 for comparing the output of a comparison value generating circuit 92 for generating a comparison value shown in FIG. 7C which is proportional to and follows the peak value of the absolute value of I _{O in} a sufficiently long cycle.

[0026] In the normal operation (FIG. 7 (c), the section (A)), the instantaneous value of the absolute value of the output current I _O, a sufficiently longer period than the period of the frequency of the output current I _O of the I _O The absolute value does not exceed the comparison value proportional to and following the change in the peak value of the absolute value. Here, when an abnormality such as a short circuit of a part or all of the reactor constituting the load 8 occurs, the circuit constant of the load 8 changes suddenly, and the output current _IO rapidly increases (FIG. 7A). , at the instantaneous value of the absolute value of the output current I _O is the abrupt change of output current I _O proportionality, exceeding the comparison value does not follow (FIG. 7 (c), the section (B)), the comparator 93 operates (FIG. 7D), and the MOSFETs 11 to 1
4 all gate signals are cut off (OFF) and MOS
This prevents a steep reverse recovery current from flowing through the internal diodes of the FETs 11 to 14.

Further, as a fourth embodiment of the present invention,
FIG. 9 shows a case where the control circuit 9 includes the absolute value conversion circuit 91, the peak hold circuit 94, the charge / discharge circuit 95, the adder 96, the comparison value generation circuit 97, and the comparator 98 shown in FIG. 8 with reference to the operation waveform diagram of the circuit of FIG.
This will be described below. That is, the circuit of FIG. 8 includes an output of the absolute value conversion circuit 91 for converting the output current I _O shown in FIG. 9A into an absolute value shown in FIG. 9B, and a peak of the absolute value of the output current I _O. A peak hold circuit 94 for holding the value in a cycle sufficiently longer than the cycle of the frequency of the output current; charging with a value obtained by subtracting the absolute value from the held hold value (FIG. 9C); Charging / discharging circuit 9 which discharges the maximum value to zero during a half period of the frequency cycle of the output current
5, an adder 96 for adding the absolute value of I _O to the output value (FIG. 9 (c)) of the charge / discharge circuit 95, and the absolute value with a period sufficiently longer than the period of the frequency of the output current I _O. , A comparison value generation circuit 97 for generating a comparison value proportional to and following the peak value of the comparison value, an output value of the adder 96 (FIG. 9D) and an output value of the comparison value generation circuit 97 (FIG. 9D). And a comparator 98 for comparing.

In a normal operation state (FIG. 9 (e), section (C)), the output value of the adder (FIG. 9 (d)) has a period sufficiently larger than the period of the frequency of the output current _IO. The I
_The comparison value (FIG. 9D) does not exceed the comparison value proportional to and following the change in the peak value of the absolute value of _O. Here, when an abnormality such as short-circuiting of a part or all of the reactor constituting the load 8 occurs, the circuit constant of the load 8 changes abruptly, and the frequency of the output current _IO sharply increases (see FIG. 9A )), The charge / discharge circuit 95 performs the next charge before the above-mentioned discharge is completed (FIG. 9 (c)), and the charge / discharge circuit 95 adds the output value and the absolute value of the I _O. The output value of the adder 96 (FIG. 9D) increases, and when the increased value exceeds the comparison value (FIG. 9E, section (D)), the comparator 98 operates. (FIG. 9 (e)), and the MOSFETs 11-
14 all gate signals are turned off (OFF), and MO
This prevents a sudden reverse recovery current from flowing through the internal diodes of the SFETs 11 to 14.

[0029]

According to the present invention, the circuit constant of the load suddenly changes, for example, when a part or all of the reactor constituting the load of the inverter device is short-circuited. If the value rises sharply, this is detected and all MOSF
Since the gate signal of ET is cut off, the MOS
Even without adding a backflow prevention diode and a commutation diode outside the FET, the inverter device stops without a steep reverse recovery current flowing, and the MOSFET is prevented from being destroyed by the steep reverse recovery current. Equipment miniaturization,
Cost can be reduced.

Further, since the upper and lower arms can be constituted only by MOSFETs, the conduction loss of the power semiconductor element of the inverter device is reduced and the conversion efficiency of the inverter device is improved as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an inverter device showing an embodiment of the present invention.

FIG. 2 is a waveform chart illustrating the operation of FIG.

FIG. 3 is a waveform chart for explaining the operation of FIG. 1;

FIG. 4 is a circuit configuration diagram of an inverter device showing a conventional example.

FIG. 5 is a waveform chart for explaining the operation of FIG. 4;

FIG. 6 is a circuit diagram illustrating a third embodiment of the present invention.

FIG. 7 is a waveform chart for explaining the operation of FIG. 6;

FIG. 8 is a circuit diagram illustrating a fourth embodiment of the present invention.

9 is a waveform chart illustrating the operation of FIG.

[Explanation of symbols]

6 DC power supply 7 Current detector 8 Load 9 and 10
Control circuit, 11 to 14 MOSFET, 11a to 14a
... MOSFET internal diodes, 21 to 24 backflow prevention diodes, 31 to 34 commutation diodes, I _0, output current, V _0, output voltage, 91, absolute value conversion circuit, 9
2, 97: comparison value generating circuit, 93, 98: comparator, 94
... peak hold circuit, 95 ... charge / discharge circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Seiwa Nakamura 1-1, Tanabe-Shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (56) References JP-A-3-212163 (JP, A) JP-A JP-A-4-296495 (JP, A) JP-A-5-316749 (JP, A) JP-A-61-147780 (JP, A) JP-A-1-126172 (JP, A) (58) Fields studied (Int) .Cl. ⁷ , DB name) H02M 7/537 H02M 1/00 H02M 7/5387

Claims (7)

(57) [Claims] An upper and lower arm composed of a MOSFET is connected to a DC power supply, a load is connected to a connection point between the upper arm and the lower arm, and an on-time of the MOSFET is adjusted to the load so that the load is connected to the load. In the method for preventing destruction of the internal diode of the MOSFET of a full-bridge or half-bridge inverter device that always outputs an alternating current having a phase delayed from the voltage, the frequency of the output current of the inverter device becomes higher than a predetermined frequency. When the MOSF is detected,
MOSF characterized by blocking a gate signal of ET
How to prevent breakdown of internal diode of ET. 2. An upper and lower arm composed of a MOSFET is connected to a DC power supply. A load is connected to a connection point between the upper arm and the lower arm. In a method for preventing destruction of the internal diode of the MOSFET of a full-bridge or half-bridge inverter device that always outputs an alternating current having a phase delayed from a voltage, a zero-cross point of the output current is detected, and the zero-cross point is determined at a predetermined time. When the MOS is detected earlier,
MOS that cuts off the gate signal of FET
A method to prevent the destruction of the internal diode of the FET. 3. The method for preventing destruction of an internal diode of a MOSFET according to claim 2, wherein n is a half cycle (n = 1, 1) of an operation of the inverter device.
The zero-crossing point of the output current is measured by one or a plurality of counters that are reset at any time every 2, 3,... A method for preventing breakdown of an internal diode of a MOSFET, wherein the gate signal of the MOSFET is cut off when one measured value reaches n + 1 times. 4. The method for preventing destruction of an internal diode of a MOSFET according to claim 2, wherein n times a half cycle of the operation of the inverter device (n = 1, 2).
Each of the counters is reset at an arbitrary point in time, and reset timings are different from each other. The zero-cross point of the output current is measured by a plurality of counters. A method for preventing breakdown of an internal diode of a MOSFET, wherein the gate signal of the MOSFET is cut off when at least one measured value of the counter reaches n + 1 times. 5. An upper and lower arm composed of a MOSFET is connected to a DC power supply, a load is connected to a connection point between the upper arm and the lower arm, and an on-time of the MOSFET is adjusted to the load so that the load is connected to the load. In the method for preventing destruction of the internal diode of the MOSFET of a full-bridge or half-bridge inverter device which always outputs an AC current delayed in phase from the voltage, the instantaneous value of the absolute value of the output current of the inverter device is A gate signal of the MOSFET is cut off when it is detected that a comparison value that is proportional to and follows a peak value of the absolute value is detected in a period sufficiently longer than a frequency period. Method. 6. An upper and lower arm composed of a MOSFET is connected to a DC power supply, a load is connected to a connection point between the upper arm and the lower arm, and an on-time of the MOSFET is adjusted to the load so that the load is connected to the load. In the method for preventing destruction of the internal diode of the MOSFET of a full-bridge or half-bridge inverter device which always outputs an alternating current having a phase delayed from the voltage, the absolute value of the slope of the tangent of the output current of the inverter device is determined by the absolute value of the inverter device. When it is detected that the absolute value has increased from the same absolute value one half cycle before the switching operation, the MOSFE
MOSFE characterized by blocking a gate signal of T
How to prevent breakdown of the internal diode of T. 7. The method for preventing destruction of an internal diode of a MOSFET according to claim 6, wherein a peak value of an absolute value of an output current of the inverter device is held at a period sufficiently longer than a frequency period of the output current. The absolute value is added to the output value of the charge / discharge circuit which charges the battery with a value obtained by subtracting the absolute value from the held peak value and discharges the maximum value of the charged value to zero in a half period of the frequency of the output current. When it is detected that the value obtained by adding the comparison value exceeds a comparison value proportional to and following the peak value of the absolute value in a cycle sufficiently longer than the cycle of the frequency of the output current,
MOS that cuts off the gate signal of FET
A method to prevent the destruction of the internal diode of the FET.