JPH08251938A - Inverter - Google Patents

Abstract

PURPOSE: To obtain a small-sized, lightweight high frequency inverter. CONSTITUTION: When an overcurrent flows through the reactor 6 and the output capacitor 7 in a filter circuit 46 due to overload, for example, the overcurrent is detected, in the form of a corresponding voltage, by means of first and second current detection resistors 51, 52 connected in series with first and second MOS- FETs 2, 3. When the detected voltage exceeds a predetermined level, first or second overcurrent protective means 53, 54 interrupts the ON/OFF operation of first or second MOS-FET 2, 3. Since the first or second overcurrent protective means 53, 54 has high response rate, a high frequency inverter can be realized easily. Furthermore, the size and weight of inverter can be reduced because a small-sized, lightweight first or second current detection resistor 51, 52 can be employed as a current detection means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device for converting DC power into AC power, and more particularly to an inverter device having an overcurrent protection function.

[0002]

2. Description of the Related Art Inverter devices for converting DC power supplied from a DC power source such as a battery or dry cell into single-phase AC power or multi-phase AC power of three or more phases have been widely used in the field of electronic equipment and electric equipment. It is used. For example, in FIG.
The inverter device shown in FIG. 1 includes a DC power source 1, first and second MOS-FETs 2 and 3 as first and second switching elements connected in series to an output terminal of the DC power source 1,
Third and fourth MOS-FETs 4 and 5 as third and fourth switching elements connected in series at both ends of the first and second MOS-FETs 2 and 3, and first and second MO-FETs.
Connection point of S-FETs 2 and 3 and third and fourth MOS-FE
The filter circuit 46 including the reactor 6 and the output capacitor 7 connected between the connection point of T4 and T5;
Via the fourth drive circuits 8 to 11, the first to fourth MOS-
A control circuit 12 for applying a drive signal to each gate terminal (control terminal) of the FETs 2 to 5 to turn on / off the first to fourth MOS-FETs 2 to 5. Further, a commercial frequency current transformer 13 for detecting the AC output current I _OUT is provided between the output capacitor 7 and the connection point of the third and fourth MOS-FETs 4, 5. As shown in FIG. 11, in the control circuit 12, the commercial frequency transformer 1
4, an output voltage detection circuit 20 including a diode bridge 15, an integrating circuit 16, a first reference power supply 17, an error amplifier 18, and a diode 19, and a diode bridge 21,
Backflow prevention diode 22, capacitor 23, resistance 2
4, 25, a second reference power supply 26, an error amplifier 27 and a diode 28, and a commercial frequency current transformer 13
An output current detection circuit 29 for detecting the AC output current I _OUT detected by the sine wave signal as a voltage corresponding to the current, a sine wave signal having a commercial frequency (50 to 60 Hz), and a rectangular wave having a frequency synchronized with the frequency of the sine wave signal. Amplitude control for controlling the amplitude of the sine wave signal of the oscillator 30 according to the feedback signal output from the output voltage detection circuit 20 and the output current detection signal output from the output current detection circuit 29. A circuit 31, a full-wave rectification circuit 32 for full-wave rectifying the sine wave signal whose amplitude is controlled by the amplitude control circuit 31, and a DC bias level of the sine wave signal full-wave rectified by the full-wave rectification circuit 32 are adjusted. A potential converter 33 that generates a reference sine wave signal, a triangular wave oscillator 34 that generates a triangular wave signal for PWM modulation (pulse width modulation), and a potential converter The PWM comparator 35 that PWM-modulates the reference sine wave signal by comparing the voltage of the reference sine wave signal of 3 with the voltage of the triangular wave signal of the triangle wave oscillator 34, the PWM modulation output signal of the PWM comparator 35, and the rectangular wave of the oscillator 30. An exclusive OR gate 36 that outputs an exclusive OR with a signal, an inverting amplifier 37 that outputs an inverted signal of the rectangular wave signal of the oscillator 30, and an inverting amplifier 38 that outputs an inverted signal of the output signal of the exclusive OR gate 36. Is provided. Also, the first
As shown in FIG. 12, the third and fourth drive circuits 8 and 10 are each composed of a potential converter 39 (for example, IR2112 manufactured by IR Co., Ltd.) and an amplifier 40, and the second and fourth drive circuits 9 and 11 are shown in FIG. It comprises an amplifier 41 as shown.

The operation of the control circuit 12 shown in FIG. 11 is as follows. The rectangular wave signal of the commercial frequency output from the oscillator 30 is output as it is to the fourth drive circuit 11 as the drive signal V _G4 of the fourth MOS-FET 5, and also inverted by the inverting amplifier 37 to generate the third MOS-FET 4. _Is output to the third drive circuit 10 as the drive signal V _G3 .
Voltage waveforms at points E and F of the drive signals V _G3 and V _G4 at this time are shown in FIGS. 14D and 14E, respectively. On the other hand, the sine wave signal V _M (M point) of the commercial frequency shown in FIG. 15 (E) output from the oscillator 30 is input to the amplitude control circuit 31 and the feedback signal output from the output voltage detection circuit 20 The amplitude of the sinusoidal signal is controlled. As the feedback signal, the AC output voltage V _OUT is detected by the commercial frequency transformer 14, the detected output of the commercial frequency transformer 14 is rectified by the diode bridge 15, and the rectified output of the diode bridge 15 is converted into a DC voltage by the integrating circuit 16, It is formed by comparing the DC voltage of the integrating circuit 16 with the reference voltage V _R1 of the first reference power source 17 by the error amplifier 18 and outputting the comparison output through the diode 19. Output signal V _I of the integrating circuit 16 at this time
Voltage waveforms of the output signal V _J (point _J ) of the error amplifier 18 (point I) are shown in FIGS. 15 (A) and 15 (B), respectively. The sine wave signal whose amplitude is controlled by the amplitude control circuit 31 is full-wave rectified by the full-wave rectification circuit 32, the DC bias level is adjusted by the potential converter 33, and the inverted input terminal of the PWM comparator 35 is used as the reference sine wave signal. Entered in. The voltage waveform of the reference sine wave signal V _B (point B) at this time is shown in FIG. From the triangular wave oscillator 34, FIG.
As shown in (A), a triangular wave signal V _A (point A) having a frequency extremely higher than the frequency of the reference sine wave signal V _B is output, and P
It is input to the non-inverting input terminal of the WM comparator 35.
The PWM comparator 35 compares the voltage of the reference sine wave signal V _B input to the inverting input terminal with the voltage of the triangular wave signal V _A input to the non-inverting input terminal to PWM-modulate the reference sine wave signal V _B. . The voltage waveform of the PWM modulation output signal V _PWM (point G) of the PWM comparator 35 at this time is shown in FIG. The PWM modulation output signal V _PWM of the PWM comparator 35 is input to the exclusive OR gate 36 together with the rectangular wave signal (point F ′) of the oscillator 30 shown in FIG. 14 (E), and the exclusive OR of both signals is output. .
This output signal is output as it is to the first drive circuit 8 as the drive signal V _G1 for the first MOS-FET 2 and is inverted by the inverting amplifier 38 to generate the second MOS-FET 3.
_Is output to the second drive circuit 9 as the drive signal V _G2 .
The voltage waveforms at points C and D of the drive signals V _G1 and V _G2 at this time are shown in FIGS. 14B and 14C, respectively.

The operation of the main circuit of the inverter device shown in FIG. 10 is as follows. The drive signals V _{G1 to} V _G4 shown in FIGS. 14B to 14E output from the control circuit 12 pass through the first to fourth drive circuits 8 to 11, respectively, and the first to fourth MOS-FETs 2 to 2 respectively. 5 to each gate terminal. At this time, in the first and third drive circuits 8 and 10, the first and third MOS-FETs having greatly different potentials are provided.
The DC bias levels of the drive signals V _G1 and V _G3 are adjusted by the potential converter 39 to drive 2 and 4, respectively.
The first and third MOS-FETs 2 and 4 are provided by the amplifier 40.
Is amplified to sufficient power to drive the. Meanwhile, the second
In the fourth and fourth drive circuits 9 and 11, the drive signals V _G2 and V _G4 are amplified by the amplifier 41 to a sufficient electric power to drive the second and fourth MOS-FETs 3 and 5. As a result, the first and second MOS-FETs 2 and 3 are alternately turned on / off at a PWM-modulated frequency extremely higher than the commercial frequency, and the third and fourth MOS-FETs 4 and 5 are turned on and off.
Are alternately turned on and off at the commercial frequency. Between the connection point of the first and second MOS-FETs 2 and 3 and the connection point of the third and fourth MOS-FETs 4 and 5 by the on / off operation of the first to fourth MOS-FETs 2 to 5. In the PW
An M-modulated sinusoidal AC voltage having a commercial frequency is generated.
The PWM-modulated sine wave AC voltage is applied to the filter circuit 46.
A smooth sine wave AC output having a smooth commercial frequency, which is smoothed by the reactor 6 and the output capacitor 7 and has the ripple component removed at both ends of the output capacitor 7, is generated. The waveform of the sine wave AC output voltage V _OUT and the output current I at this time
Waveforms of _OUT are shown in FIGS. 15 (F) and (G), respectively. FIG.
The AC output current I _OUT shown at 5 (G) is detected by the commercial frequency current transformer 13 as a voltage corresponding to the AC output current I _OUT . Further, this detection voltage is full-wave rectified by the diode bridge 21 of the output current detection circuit 29 in the control circuit 12 shown in FIG.
It is converted into a DC voltage V _L (point _L ) as shown in (D).
This DC voltage V _L causes the capacitor 23 to be peak-charged through the backflow prevention diode 22 with a time constant determined by the capacitance of the capacitor 23 and the resistance value of the resistor 25, as shown in FIG. DC level voltage V _K (K
Points). The DC level voltage V _K is compared with the reference voltage V _R2 of the second reference power supply 26 by the error amplifier 27, and the comparison output of the error amplifier 27 is output as an output current detection signal to the amplitude control circuit 31 through the diode 28. .

Here, when an overcurrent flows through the reactor 6 and the output capacitor 7 of the filter circuit 46 due to an overload, an output short circuit, or the like, the detection voltage of the commercial frequency current transformer 13 rises, so that the output current detection circuit 29 Resistance 24
Across the DC voltage V _L increases, the DC level voltage V _K is greater than the reference voltage V _R2 of the second reference power supply 26. At this time, the overcurrent detection signal is output from the error amplifier 27 through the diode 28, and the amplitude control circuit 31 limits the amplitude of the sine wave signal V _M from the oscillator 30 according to the overcurrent detection signal. This limits the amplitude of the reference sine wave signal V _B , so that the first and second switching elements 2,
The ON / OFF operation of 3 is controlled, the AC output voltage V _OUT drops, and the AC output current I _OUT is held constant.

[0006]

In the conventional inverter device, the commercial frequency current transformer 13 is used as the current detecting means because it is necessary to insulate the output side of the main circuit from the control circuit 12. Particularly, in the inverter device shown in FIG. 10, it is necessary to use a large and heavy current transformer in order to detect the AC output current I _OUT of the commercial frequency (50 to 60 Hz). For this reason, there is a drawback that the inverter device becomes large and the weight increases. In addition, since a large number of circuits in the control circuit 12 are used until the commercial frequency current transformer 13 detects the overcurrent and controls the on / off operations of the switching elements 2 and 3, the response speed is extremely high. There is a drawback that it becomes slow and it is difficult to increase the frequency of the inverter device.

[0007] Therefore, an object of the present invention is to provide an inverter device which is small in size, light in weight and easy to operate at high frequencies.

[0008]

An inverter device of the invention according to claim 1 is a direct current power source, first and second switching elements connected in series to an output terminal of the direct current power source, and the first switching element. And third and fourth switching elements connected in series at both ends of the first and second switching elements, and the first switching element.
And a filter circuit connected in series between the connection point of the second switching element and the connection point of the third and fourth switching elements, and a drive signal to each control terminal of the first to fourth switching elements. And a control circuit for turning on and off each of the switching elements.
~ By the on / off operation of the fourth switching element, an AC output is generated from the filter circuit. In this inverter device, the current flowing through the first switching element is detected as a voltage corresponding to the current, and the current flowing through the second switching element is detected as a voltage corresponding to the current. A second current detection means is connected in series with the first and second switching elements, respectively, and the first switching element is provided when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage. First overcurrent protection means for stopping the on / off operation of
Second overcurrent protection means for stopping the on / off operation of the second switching element when the detection voltage of the second current detection means becomes equal to or higher than a predetermined voltage is provided. In the inverter device of the invention according to "claim 2", the first overcurrent protection means outputs an overcurrent detection signal when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage. A set state is set according to the output signal of the first overcurrent detection unit and the first overcurrent detection unit, and a reset state is set according to a drive signal applied from the control circuit to the first switching element. A first flip-flop, and a first cut-off unit that cuts off a drive signal to the first switching element by a signal output when the first flip-flop is in a set state,
The second overcurrent protection means includes a second overcurrent detection means that outputs an overcurrent detection signal when the detection voltage of the second current detection means exceeds a predetermined voltage, and the second overcurrent detection means. A second flip-flop which is set according to an output signal of the overcurrent detecting means and is reset according to a drive signal applied from the control circuit to the second switching element; and the second flip-flop. And a second cutoff unit that cuts off the drive signal to the second switching element by a signal output when the set state is set. In the inverter device of the invention according to claim 3, the first flip-flop is in a reset state when the drive signal of the first switching element falls, and when the drive signal of the second switching element falls, The second flip-flop is in the reset state.

Further, in the inverter device of the invention according to "claim 4", the first current detecting means for detecting the current flowing through the first or second switching element as a voltage corresponding to the current is provided in the first current detecting means. Or a second switching element connected in series to detect a current flowing through the third or fourth switching element as a voltage corresponding to the current.
Is connected in series with the third or fourth switching element, and when the detected voltage of the first current detecting means becomes equal to or higher than a predetermined voltage, the first or second switching element of First overcurrent protection means for stopping the on / off operation, and on / off operation of the third or fourth switching element when the detection voltage of the second current detection means exceeds a predetermined voltage. And a second overcurrent protection means for stopping. In the inverter device of the invention according to claim 5, the first overcurrent protection means outputs the overcurrent detection signal when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage. A first overcurrent detection means and a reset state in response to a drive signal applied to the first or second switching element from the control circuit in a set state according to an output signal of the first overcurrent detection means A first flip-flop that is in a state, and a first cut-off unit that cuts off a drive signal to the first or second switching element by a signal output when the first flip-flop is in a set state The second overcurrent protection means includes a second overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the second current detection means exceeds a predetermined voltage, The second overcurrent detection A second flip-flop which is set according to the output signal of the means and which is reset according to the drive signal applied from the control circuit to the third or fourth switching element; and the second flip-flop. And a second cutoff unit that cuts off the drive signal to the third or fourth switching element by a signal output when the switch is in the set state. In the inverter device of the invention according to claim 6,
When the drive signal of the first or second switching element falls, the first flip-flop is in a reset state, and when the drive signal of the third or fourth switching element falls, the second flip-flop is It goes into a reset state.

Further, in the inverter device of the invention according to "claim 7", the DC power supply, the first and second switching elements connected in series to the output terminal of the DC power supply, and the first
First and second half-bridge capacitors connected in series at both ends of the first and second switching elements;
And a filter circuit connected between a connection point of the second switching element and a connection point of the first and second half-bridge capacitors, and driving to each control terminal of the first and second switching elements. A control circuit for applying a signal to turn on / off each of the switching elements,
An AC output is generated from the filter circuit by the ON / OFF operation of the first and second switching elements. In this inverter device, the first current that flows in the first switching element is detected as a voltage corresponding to the first current.
Current detecting means and second current detecting means for detecting a current flowing through the second switching element as a voltage corresponding to the current are connected in series with the first and second switching elements, respectively, and A first overcurrent protection means for stopping the on / off operation of the first switching element when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage, and a detection by the second current detection means. Second overcurrent protection means for stopping the on / off operation of the second switching element when the voltage becomes equal to or higher than a predetermined voltage is provided. In the inverter device of the invention according to "claim 8", the first overcurrent protection means outputs an overcurrent detection signal when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage. A first overcurrent detection means and the first
A first flip-flop that is set according to the output signal of the overcurrent detection means and that is reset according to the drive signal applied from the control circuit to the first switching element; and the first flip-flop. A first shut-off means for shutting off the drive signal to the first switching element by a signal output when the drive circuit is in the set state, and the second overcurrent protection means includes the second overcurrent protection means. Second overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the current detection means becomes equal to or higher than a predetermined voltage; and a set state according to the output signal of the second overcurrent detection means, and A second flip-flop which is in a reset state in response to a drive signal applied from the control circuit to the second switching element, and the second flip-flop is in a set state. And a second blocking means for blocking the drive signal to the second switching element by a signal to be output to. In the inverter device of the invention according to claim 9, the first flip-flop is in a reset state when the drive signal of the first switching element falls, and when the drive signal of the second switching element falls, The second flip-flop is in the reset state.

Further, in the inverter device of the invention according to "claim 10", the direct current power source, the first and second switching elements connected in series to the output terminal of the direct current power source, and the first and second switching elements. Third and fourth switching elements connected in series to both ends of the switching element and fifth and sixth switching elements connected in series to both ends of the third and fourth switching elements
No. 1 to No. 3 connected to the connection point of the first and second switching elements, the connection point of the third and fourth switching elements, and the connection point of the fifth and sixth switching elements, respectively. Drive circuits are applied to the first to third filter circuits including the reactor and the first to third output capacitors, and the control terminals of the first to sixth switching elements to turn on the switching elements. A control circuit for performing an off operation, and by the on / off operation of the first to sixth switching elements, a three-phase alternating current output is generated from the three connection points via the first to third filter circuits. . In this inverter device, the first or second
Connecting a first current detecting means for detecting a current flowing through the switching element as a voltage corresponding to the current in series with the first or second switching element, and flowing a current through the third or fourth switching element. Is connected in series with the third or fourth switching element, and the current flowing through the fifth or sixth switching element corresponds to the current. A third current detecting means for detecting a voltage is connected in series with the fifth or sixth switching element, and when the detected voltage of the first current detecting means exceeds a predetermined voltage, the first or The first overcurrent protection means for stopping the on / off operation of the second switching element, and the third or fourth when the detection voltage of the second current detection means becomes equal to or higher than a predetermined voltage. Second overcurrent protection means for stopping ON / OFF operation of the switching element, and ON of the fifth or sixth switching element when the detection voltage of the third current detection means becomes equal to or higher than a predetermined voltage. A third overcurrent protection means for stopping the off operation is provided. In the inverter device of the invention according to “claim 11”, the first
Means for outputting an overcurrent detection signal when the detection voltage of the first current detection means exceeds a predetermined voltage, and the first overcurrent detection means. A first flip-flop which is set according to an output signal of the means and is reset according to a drive signal applied from the control circuit to the first or second switching element; and the first flip-flop. And a second cutoff means for cutting off the drive signal to the first or second switching element by a signal output when the second overcurrent protection means is in the set state. Second overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the second current detection means becomes equal to or higher than a predetermined voltage, and a set state according to the output signal of the second overcurrent detection means And control A second flip-flop that is in a reset state in response to a drive signal applied to the third or fourth switching element from a path, and a signal that is output when the second flip-flop is in the set state. A second cutoff means for cutting off a drive signal to the third or fourth switching element, wherein the third overcurrent protection means has a detection voltage of the third current detection means equal to or higher than a predetermined voltage. The third overcurrent detection means for outputting an overcurrent detection signal when the above condition occurs, and a set state is set in accordance with the output signal of the third overcurrent detection means, and the control circuit outputs the fifth signal.
Alternatively, the third or fifth flip-flop that is in a reset state according to the drive signal applied to the sixth switching element and the signal output when the third flip-flop is in the set state causes the fifth or sixth And a third cutoff unit that cuts off a drive signal to the switching element.
In the inverter device of the invention according to claim 12, the first flip-flop is in a reset state when the drive signal of the first or second switching element falls, and the third or fourth switching element The second flip-flop is in a reset state when the drive signal falls, and the third flip-flop is in a reset state when the drive signal for the fifth or sixth switching element falls.

[0012]

When an overcurrent flows through the filter circuit due to an overload or the like, the first current detection means connected in series with the first switching element or the second current detection connected in series with the second switching element. The overcurrent is detected by the means as a voltage corresponding to the current. When the detected voltage becomes equal to or higher than a predetermined voltage, the first or second overcurrent protection means stops the on / off operation of the first or second switching element. Therefore, the response speed of the first or second overcurrent protection means is fast, and when the overcurrent flows to the output side, the on / off operation of the first or second switching element can be instantaneously stopped. . Therefore, it is easy to increase the frequency of the inverter device. Further, since the first and second current detecting means detect the intermittent switching current,
Small and lightweight can be used. Therefore, it is possible to reduce the size and weight of the inverter device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the inverter device according to the present invention will be described below with reference to FIGS. However, in these drawings, the portions substantially the same as the portions shown in FIGS. 10 to 15 are denoted by the same reference numerals, and the description thereof will be omitted. The inverter device of the present embodiment, as shown in FIG.
-A first current detecting resistor 51 as a first current detecting means for detecting a current flowing through the FET2 as a voltage corresponding to the current is connected in series with the first MOS-FET2, and a second MOS-FET3 is connected. A second current detecting resistor 52 as a second current detecting means for detecting the current flowing through the second current detecting circuit as a voltage corresponding to the current, is connected in series with the second MOS-FET 3, and the first current detecting resistor 51 is connected. As shown in FIG. 3, the first overcurrent protection means 53 for stopping the on / off operation of the first MOS-FET 2 when the detected voltage becomes higher than a predetermined voltage is applied to the first drive circuit 8 as shown in FIG. It is provided between the converter 39 and the amplifier 40, and when the detection voltage of the second current detection resistor 52 becomes equal to or higher than a predetermined voltage, the second MOS-
The second overcurrent protection means 54 for stopping the on / off operation of the FET 3 is provided in the preceding stage of the amplifier 41 of the second drive circuit 9 as shown in FIG. The other circuit configuration is substantially the same as the circuit configuration of FIG. 10 except that the commercial frequency current transformer 13 shown in FIG. 10 is omitted. As shown in FIG. 2, the control circuit 12 of FIG. 1 has a reference when the amplitude of the reference sine wave output from the potential converter 33 exceeds the predetermined limit voltage level V _TH (FIG. 6). An amplitude limiter 55 that limits the amplitude of the sine wave is provided between the potential converter 33 and the inverting input terminal of the PWM comparator 35. The other circuit configuration is substantially the same as the circuit configuration in the control circuit 12 shown in FIG. 11 except that the output current detection circuit 29 shown in FIG. 11 is omitted. In the first overcurrent protection unit 53 in the first drive circuit 8, as shown in FIG. 3, the detection voltage of the first current detection resistor 51 becomes equal to or higher than the reference voltage V _{R3 of} the third reference power supply 56. The first comparator 57 as a first overcurrent detection means that outputs an overcurrent detection signal when
And the first M from the control circuit 12 through the potential converter 39.
The inverting amplifier 58, which inverts and amplifies the drive signal V _{G1 applied} to the OS-FET 2, and the first comparator 57, which is in the set state according to the output signal and the inverting amplifier 58 is in the reset state according to the output signal, Of the first MOS-FET by the signal output when the first flip-flop 59 and the first flip-flop 59 are in the set state.
The first NOR gate 60 serves as a first cutoff unit that cuts off the drive signal V _G1 for the second signal. Therefore, the first flip-flop 59 is the first MOS-F.
When the drive signal V _G1 to ET2 falls, the reset state is set. Further, in the first overcurrent protection means 54 in the second drive circuit 9, as shown in FIG. 4, the detection voltage of the second current detection resistor 52 is the reference voltage V _{R4 of} the fourth reference power supply 61. A second comparator 62 as a second overcurrent detection means that outputs an overcurrent detection signal when the above is reached, and an inversion amplification of the drive signal V _{G2 applied} from the control circuit 12 to the second MOS-FET 3 A second flip-flop 64, which is in a set state according to the output signal of the second comparator 62 and is in a reset state according to the output signal of the inverting amplifier 63, and a second flip-flop 64. A second signal for shutting off the drive signal V _G2 to the second MOS-FET 3 by the signal output when the state becomes
And a second NOR gate 65 as a means for shutting off. Therefore, the second flip-flop 64
Becomes a reset state when the drive signal V _G2 to the second MOS-FET 3 falls.

Next, the operation of the inverter device shown in FIG. 1 will be described. Regarding the operation at the normal time, the operation shown in FIG.
Since the operation is substantially the same as that of the inverter device shown in FIG. In the circuit of FIG. 1, when an overcurrent flows in the reactor 6 and the output capacitor 7 of the filter circuit 46 due to overload or the like, the first MOS-FET 2
Is ON, the overcurrent is detected by the first current detection resistor 51 as a voltage corresponding to the current. At this time, the triangular wave signal V _A output from the triangular wave oscillator 34 in the control circuit 12, the reference sine wave signal V _B output from the amplitude limiter 55, the first MOS-FET 2 from the control circuit 12
Drive signal V _G1 and the first current detection resistor 5 output to
Waveforms of the detection voltage V ₁ of _{No. 1} are shown in FIGS. Detection voltage V _{1 of} the first current detection resistor 51 (point S in FIG. 3)
Is compared with the reference voltage V _R3 of the third reference power supply 56 by the first comparator 57 of the first overcurrent protection means 53 in the first drive circuit 8, and the detected voltage V ₁ is equal to or higher than the reference voltage V _R3. In this case, the overcurrent detection signal V ₂ is output from the first comparator 57 (point R in FIG. 3). The voltage waveform of the overcurrent detection signal V ₂ output from the first comparator 57 at this time is shown in FIG. The overcurrent detection signal V ₂ output from the first comparator 57 puts the first flip-flop 59 in the set state, and the output signal V ₃ of the first flip-flop 59 becomes high as shown in FIG. 5 (F). It becomes a level (high level) (point T in FIG. 3). The output signal V ₃ of the first flip-flop 59 is the first NOR gate 60.
The drive signal V _G1 from the control circuit 12 to the first MOS-FET 2 is input to the other input terminal (point O in FIG. 3) through the potential converter 39.
Therefore, the output signal V of the first flip-flop 59 is
_{When 3} is high level, as shown in FIG. 5 (G), the first NO
The output signal V ₄ (point Q in FIG. 3) of the R gate 60 becomes low level (low level), and the first drive circuit 8 outputs the first M signal.
Drive signal V _{G1 applied} to the gate terminal of OS-FET2
Is cut off instantly. Therefore, the first MOS-FET2
Turns off instantly. After that, when the drive signal V _G1 (point O in FIG. 3) from the control circuit 12 to the first MOS-FET 2 changes from high level to low level as shown in FIG. 5 (B), it is shown in FIG. 5 (E). Output signal V of the inverting amplifier 58
₅ (point P in Figure 3) goes from low to high,
The flip-flop 59 is reset. At this time, the output signal V _{3 of} the first flip-flop 59 is as shown in FIG.
As shown in (F), the high level returns to the low level. When the second MOS-FET 3 is on, the second current detection resistor 52 detects the overcurrent as a voltage corresponding to the current. The operation thereafter is the same as the first MO described above.
Similarly to when the S-FET 2 is in the ON state, the second comparator 62 of the second overcurrent protection means 54 in the second drive circuit 9 compares it with the reference voltage V _R4 of the fourth reference power supply 61, When the detection voltage of the second current detection resistor 52 is equal to or higher than the reference voltage V _{R4, the} overcurrent detection signal is output from the second comparator 62, and the overcurrent detection signal puts the second flip-flop 64 into the set state. The output signal of the second NOR gate 65 becomes low level, and the output signal of the second NOR gate 65 becomes low level.
Drive signal V _{G2 applied} to the gate terminal of OS-FET3
Is cut off instantly. Therefore, the second MOS-FET3
Turns off instantly. After that, when the drive signal V _G2 from the control circuit 12 to the second MOS-FET 3 changes from high level to low level, the output signal of the inverting amplifier 63 changes from low level to high level, and the second flip-flop 64 is reset. At the same time, the output signal returns from high level to low level.

By the way, as shown in FIG. 6A, the AC output voltage V _OUT is remarkably reduced due to the output short circuit or the like, and the amplitude of the reference sine wave signal V _B (point H in FIG. 2) is as shown by the broken line portion. When the voltage of the triangular wave signal V _A (point A in FIG. 2) exceeds the maximum value, the control circuit 12 causes the first (or second) MOS-
The voltage of the drive signal V _G1 (or V _G2 ) to the FET 2 (or 3) (the voltage at the point O in FIG. 3) is fixed at a high level as shown by the broken line portion in FIG. The second) flip-flop 59 (or 64) is no longer reset. Therefore, once the drive signal V _G1 (or V _G2 ) is cut off by the first (or second) overcurrent protection means 53 (or 54), the amplitude of the reference sine wave signal V _B becomes equal to that of the triangular wave signal V _A. The first (or second) MO until it becomes smaller than the maximum value of the voltage
The S-FET2 (or 3) remains off, and the output cannot be recovered. Therefore, in the circuit of FIG. 1, the excess voltage component of the reference sine wave signal V _B is adjusted by the amplitude limiter 55 in FIG.
As shown by the solid line portion in (A), the amplitude of the reference sine wave signal V _B is limited to a limit voltage level V _TH which is slightly lower than the maximum value of the voltage of the triangular wave signal V _A (point B in FIG. 2). This provides a period in which the voltage of the drive signal V _G1 (or V _G2 ) shown in FIG. 6B is at a low level and prevents the first (or second) flip-flop 59 (or 64) from being reset. To prevent.

The inverter device shown in FIG. 1 can be modified. For example, in the inverter device shown in FIG. 7, the first and second current detection resistors 51 and 52 are respectively connected to the second MOS.
-Connected in series with the FET3 and the fourth MOS-FET5,
First overcurrent protection means 53 and second overcurrent protection means 5
4 is an amplifier 41 in the second drive circuit 9 (see FIG.
It is provided in the preceding stage of 3) and the preceding stage of the amplifier 41 in the fourth drive circuit 11. The other circuit configuration is substantially the same as that of the inverter device shown in FIG. In the case of the circuit shown in FIG. 7, the second and fourth MOS-FETs 3 and 5 are alternately turned on at a PWM-modulated frequency extremely higher than the commercial frequency.
It is turned off, and the first and third MOS-FETs 2 and 4 are alternately turned on and off at a commercial frequency. The protection operation of the inverter device shown in FIG. 7 when an overcurrent occurs is similar to that of the inverter device shown in FIG.
When T3 is on, the first overcurrent protection means 53 turns off the second MOS-FET 3 and the fourth MO-FET 3 is turned off.
When the S-FET 5 is on, the second overcurrent protection means 5
4 turns off the fourth MOS-FET 5. Although not shown, the first and second current detecting resistors 51 and 52 are connected to the first MOS, respectively, contrary to the circuit shown in FIG.
-Connected in series with the FET2 and the third MOS-FET4,
The first overcurrent protection means 53 is provided between the potential converter 39 and the amplifier 40 (FIG. 12) in the first drive circuit 8, and the second overcurrent protection means 53 is provided.
The overcurrent protection means 54 may be provided between the potential converter 39 and the amplifier 40 in the third drive circuit 10. In this case, the first and third MOS-FETs 2 and 4 are alternately turned on at a PWM-modulated frequency extremely higher than the commercial frequency.
It is turned off, and the second and fourth MOS-FETs 3 and 5 are alternately turned on and off at a commercial frequency. Contrary to the case of the circuit of FIG. 7 described above, the protection operation of this circuit when an overcurrent occurs is the first when the first MOS-FET 2 is in the ON state.
When the first MOS-FET 2 is turned off by the overcurrent protection means 53 and the third MOS-FET 4 is turned on, the second overcurrent protection means 54 causes the third MOS-F 3 to turn off.
ET4 is turned off.

Further, the inverter device shown in FIG.
1st and 2nd half-bridge capacitors 4 in place of the 3rd and 4th MOS-FETs 4 and 5 in the circuit of FIG.
2, 43 are connected and the DC-AC conversion bridge circuit section is of a half-bridge type. The other circuit configuration is substantially the same as that of the inverter device shown in FIG. In the case of the circuit shown in FIG. 8, P of the reference sine wave V _B in the control circuit 12
Although the WM modulation method is slightly different from that of the circuit shown in FIG. 1,
The protection operation at the time of overcurrent is substantially the same as that of the circuit shown in FIG.

FIG. 9 shows an example in which the inverter device shown in FIG. 1 is applied to a three-phase AC inverter device which generates a three-phase AC output. That is, the three-phase AC inverter device shown in FIG. 9 has the third and fourth MOS-FE in the circuit of FIG.
A DC-three-phase AC conversion bridge circuit section is configured by connecting fifth and sixth MOS-FETs 44 and 45 as fifth and sixth switching elements in series at both ends of T4 and T5,
Connection points of the first and second MOS-FETs 2 and 3 and connection points of the third and fourth MOS-FETs 4 and 5 and 5th and 6th
The first to the connection points of the MOS-FETs 44 and 45 of
First to third filter circuits 46a composed of third reactors 6a to 6c and first to third output capacitors 7a to 7c.
To 46c are connected, and the second, fourth and sixth MOS-FETs are connected.
First to third current detecting resistors 51, 52 and 66 are respectively connected in series with 3, 5, 45 respectively, and the first to third overcurrent protection means 53 and 54 of the circuit configuration shown in FIG. , 67 to the second, fourth and sixth drive circuits 9, 11, 48, respectively.
It is provided inside. The control circuit 12 applies a drive signal to each gate terminal of the first to sixth MOS-FETs 2 to 5, 44 and 45 to supply each of the MOS-FETs 2 to 5, 44 and 45.
To turn on and off. The other circuit configuration is substantially the same as that of the inverter device shown in FIG. In the case of the circuit shown in FIG. 9, the second, fourth and sixth MOS-FETs 3, 5, 4
5 is turned on and off sequentially with a phase difference of 120 ° at a PWM-modulated frequency much higher than the commercial frequency, and the first, third and fifth MOS-FETs 2, 4, 44
Are successively turned on at a commercial frequency with a phase difference of 120 °.
It is operated off. The protection operation of the three-phase AC inverter device shown in FIG. 9 when an overcurrent occurs is similar to that of the inverter device shown in FIG. 7, and when the second MOS-FET 3 is in the ON state, the first overcurrent protection means is provided. Second MOS-F by 53
When ET3 is in the off state and the fourth MOS-FET 5 is in the on state, the second overcurrent protection means 54 causes the fourth M-FET to operate.
The OS-FET5 is turned off, and the sixth MOS-FET
When 45 is on, the third overcurrent protection means 67 turns off the sixth MOS-FET 45. Although illustration is omitted, the circuit shown in FIG. 9 can be modified in the same manner as the circuit shown in FIG. That is, the first to third current detecting resistors 51, 52 and 66 are connected in series to the first, third and fifth MOS-FETs 2, 4 and 44, respectively, and the first circuit configuration shown in FIG. ~ Third overcurrent protection means 53,
54 and 67 may be provided in the first, third and fifth drive circuits 8, 10 and 47, respectively. In this case, the first,
The third and fifth MOS-FETs 2, 4 and 44 are 1 at each other at the PWM modulated frequency which is much higher than the commercial frequency.
Sequential on / off operation with a phase difference of 20 °
The sixth and sixth MOS-FETs 3, 5 and 45 are successively turned on and off at a commercial frequency with a phase difference of 120 °. Contrary to the case of the circuit of FIG. 9, the protection operation of this circuit when an overcurrent occurs is the reverse of the case of the circuit of FIG.
When ET2 is in the off state and the third MOS-FET 4 is in the on state, the second overcurrent protection means 54 causes the third M-FET to operate.
The OS-FET4 is turned off, and the fifth MOS-FET is turned on.
When 44 is on, the third overcurrent protection means 67 turns off the fifth MOS-FET 44.

As described above, in the inverter device of the embodiment shown in FIGS. 1 to 9, the MOS-FETs 2 to 5, 44 and 4 are used.
Drive circuits 8 to 11, 47, 4 provided close to each other
8 has overcurrent protection means 53, 54, 6 with a simple circuit configuration.
7 is provided, the response speed of the overcurrent protection means 53, 54, 67 is fast, and when the overcurrent flows to the output side, the MOS-
The on / off operation of the FETs 2 to 5, 44 and 45 can be stopped instantaneously. Therefore, it is easy to increase the frequency of the inverter device. In addition, the current detection resistors 51, 5
Since 2, 66 detect a switching current having a PWM-modulated frequency extremely higher than the commercial frequency, a small and lightweight one can be used. Therefore, it is possible to reduce the size and weight of the inverter device and reduce the manufacturing cost. Further, since the overcurrent protection means 53, 54, 67 can be configured only by a simple digital circuit including a comparator, a flip-flop, an inverting amplifier, and a NOR gate, there is an advantage that integration (IC) can be easily performed. .

The embodiment of the present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, a small and lightweight high-frequency current transformer may be used as the current detection means instead of the current detection resistors 51, 52, 66 of the above-described embodiments. Further, in each of the above-described embodiments, an example in which a MOS-FET is used as a switching element is shown, but a bipolar transistor, a junction FET (J
Other switching elements such as -FET) and SCR (reverse blocking 3-terminal thyristor) may be used. Further, each drive circuit 8-11, 47, 48 may be included in the control circuit 12. In addition, the filter circuits 46, 46 of the above-described embodiments
In addition to the illustrated inverted L-type circuit, T-type circuits, π-type circuits, and other various filter circuits can be used as a, 46b, and 46c. Further, it can be easily understood that the present invention can be applied to a multi-phase AC inverter device or the like for converting DC power into multi-phase AC power having three or more phases.

[0021]

According to the present invention, it is possible to use a current detecting means such as a small, lightweight and inexpensive current detecting resistor.
It is possible to reduce the size and weight of the inverter device and reduce the manufacturing cost. Further, since the current detection means and the overcurrent protection means are provided for each switching element to simplify the circuit configuration and to speed up the response speed of the overcurrent protection means, each switching is performed when an overcurrent flows to the output side. The on / off operation of the element can be stopped instantaneously. Therefore, it becomes possible to increase the frequency of the inverter device, for example, to increase the frequency of the carrier (triangular wave signal) in the control circuit, which was 20 kHz or less in the past, to about 100 kHz. As a result, the reactor of the filter circuit and the output capacitor can be downsized.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of an inverter device showing an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing the internal configuration of the control circuit of FIG.

FIG. 3 is an electric circuit diagram showing the internal configuration of the first drive circuit of FIG.

FIG. 4 is an electric circuit diagram showing an internal configuration of a second drive circuit shown in FIG.

FIG. 5 is a waveform diagram showing the voltage of each part of the circuits of FIGS.

6 is a voltage waveform diagram showing the operation of the amplitude limiter of FIG.

FIG. 7 is an electric circuit diagram of an inverter device showing a first modified embodiment of the present invention.

FIG. 8 is an electric circuit diagram of an inverter device showing a second modified embodiment of the present invention.

FIG. 9 is an electric circuit diagram showing an example in which the inverter device of the present invention is applied to a three-phase AC inverter device.

FIG. 10 is an electric circuit diagram showing a conventional example of an inverter device.

11 is a block circuit diagram showing the internal configuration of the control circuit of FIG.

FIG. 12 is an electric circuit diagram showing the internal configuration of the first and third drive circuits of FIG.

FIG. 13 is an electrical circuit diagram showing the internal configuration of the second and fourth drive circuits of FIG.

FIG. 14 is a waveform diagram showing the voltage of each part of the circuit of FIG.

FIG. 15 is a waveform diagram showing the voltage and current of each part of the circuits of FIGS. 10 and 11.

[Explanation of symbols]

1. ． ． DC power supply, 2 to 5, 44, 45. ． ． 5. First to sixth MOS-FETs (first to sixth switching elements), ． ． Reactor, 7. ． ． Output capacitor,
8-11, 47, 48. ． ． First to sixth drive circuits, 1
2. ． ． Control circuit, 13. ． ． Commercial frequency current transformer, 42, 43. ． ． First and second half-bridge capacitors, 46. ． ． Filter circuit, 46a-46
c. ． ． First to third filter circuits, 51, 52, 6
6. ． ． First to third current detection resistors (first to third current detection means), 53, 54, 67. ． ． First to third overcurrent protection means, 55. ． ． Amplitude limiter, 57, 6
2. ． ． First and second comparators (first and second overcurrent detecting means), 59, 64. ． ． First and second flip-flops 60, 65. ． ． First and second NOR gates (first and second blocking means)

Claims (12)

[Claims] 1. A DC power source, first and second switching elements connected in series to an output terminal of the DC power source, and third and third switching elements connected in series at both ends of the first and second switching elements. 4 switching elements, and the first and second
Applying a drive signal to each of the filter circuits connected between the connection points of the switching elements and the connection points of the third and fourth switching elements and the control terminals of the first to fourth switching elements. A control circuit for turning on / off each of the switching elements, wherein the first to fourth switching elements are turned on / off to generate an AC output from the filter circuit. First current detecting means for detecting a current flowing through the element as a voltage corresponding to the current, and second current detecting means for detecting a current flowing through the second switching element as a voltage corresponding to the current, respectively. It is connected in series with the first and second switching elements, and when the detection voltage of the first current detecting means becomes a predetermined voltage or higher, A first overcurrent protection means for stopping the on / off operation of the first switching element; and an on / off operation of the second switching element when the detection voltage of the second current detection means exceeds a predetermined voltage. An inverter device comprising: a second overcurrent protection means for stopping an off operation. 2. The first overcurrent protection means includes the first overcurrent protection means.
The first overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the current detection means becomes equal to or higher than a predetermined voltage, and the set state is set according to the output signal of the first overcurrent detection means. And a first flip-flop that is in a reset state in response to a drive signal applied from the control circuit to the first switching element, and a signal that is output when the first flip-flop is in a set state. A second cutoff means for cutting off a drive signal to the first switching element, wherein the second overcurrent protection means has a voltage detected by the second current detection means that is equal to or higher than a predetermined voltage. A second overcurrent detection means for outputting an overcurrent detection signal at times and a set state in accordance with the output signal of the second overcurrent detection means and being applied from the control circuit to the second switching element. A second flip-flop that is in a reset state according to the drive signal that is generated, and a second flip-flop that shuts off the drive signal to the second switching element by a signal that is output when the second flip-flop is in the set state 2. The inverter device according to claim 1, further comprising: 3. The first flip-flop is reset when the drive signal of the first switching element falls, and the second flip-flop is reset when the drive signal of the second switching element falls. The inverter device according to claim 2, which is in a state. 4. A DC power supply, first and second switching elements connected in series to an output terminal of the DC power supply, and third and third switching elements connected in series at both ends of the first and second switching elements. 4 switching elements, and the first and second
Applying a drive signal to each of the filter circuits connected between the connection points of the switching elements and the connection points of the third and fourth switching elements and the control terminals of the first to fourth switching elements. A control circuit for turning on / off each of the switching elements, wherein the first to fourth switching elements are turned on / off to generate an AC output from the filter circuit. A first current detection unit that detects a current flowing through the second switching element as a voltage corresponding to the current is connected in series with the first or second switching element, and flows through the third or fourth switching element. A second current detection means for detecting a current as a voltage corresponding to the current is connected in series with the third or fourth switching element, and the first current is detected. First overcurrent protection means for stopping the on / off operation of the first or second switching element when the detection voltage of the detection means exceeds a predetermined voltage, and detection of the second current detection means An inverter device comprising: second overcurrent protection means for stopping the on / off operation of the third or fourth switching element when the voltage exceeds a predetermined voltage. 5. The first overcurrent protection means is the first overcurrent protection means.
The first overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the current detection means becomes equal to or higher than a predetermined voltage, and the set state is set according to the output signal of the first overcurrent detection means. And a first flip-flop that is in a reset state in response to a drive signal applied from the control circuit to the first or second switching element, and is output when the first flip-flop is in a set state. A first cut-off unit that cuts off a drive signal to the first or second switching element by a signal, and the second overcurrent protection unit has a predetermined detection voltage of the second current detection unit. Second overcurrent detection means for outputting an overcurrent detection signal when the voltage becomes equal to or higher than the voltage of, and a set state is set in accordance with the output signal of the second overcurrent detection means, and the third or Fourth Su A second flip-flop that is in a reset state according to a drive signal applied to the switching element, and a signal that is output when the second flip-flop is in the set state, to the third or fourth switching element. The inverter device according to claim 4, further comprising: a second cutoff unit that cuts off the drive signal of. 6. The first flip-flop is in a reset state when the drive signal of the first or second switching element falls, and the first flip-flop is in the reset state when the drive signal of the third or fourth switching element falls. The inverter device according to claim 5, wherein the second flip-flop is in a reset state. 7. A direct current power source, first and second switching elements connected in series to an output terminal of the direct current power source, and first and second serially connected ends of the first and second switching elements. Second half-bridge capacitor, a filter circuit connected between a connection point of the first and second switching elements and a connection point of the first and second half-bridge capacitors, and the first and second A control circuit that applies a drive signal to each control terminal of the second switching element to turn on / off the switching element, and the filter is turned on / off by the first and second switching elements. In an inverter device for generating an AC output from a circuit, a first current detection means for detecting a current flowing through the first switching element as a voltage corresponding to the current. Second current detecting means for detecting a current flowing through the second switching element as a voltage corresponding to the current, and the second current detecting means are respectively connected in series with the first and second switching elements, and the first current detecting means The first overcurrent protection means for stopping the on / off operation of the first switching element when the detected voltage exceeds a predetermined voltage, and the detected voltage of the second current detection means is a predetermined voltage. An inverter device, comprising: a second overcurrent protection means for stopping the on / off operation of the second switching element when the above is reached. 8. The first overcurrent protection means comprises:
The first overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the current detection means becomes equal to or higher than a predetermined voltage, and the set state is set according to the output signal of the first overcurrent detection means. And a first flip-flop that is in a reset state in response to a drive signal applied from the control circuit to the first switching element, and a signal that is output when the first flip-flop is in a set state. A second cutoff means for cutting off a drive signal to the first switching element, wherein the second overcurrent protection means has a voltage detected by the second current detection means that is equal to or higher than a predetermined voltage. A second overcurrent detection means for outputting an overcurrent detection signal at times and a set state in accordance with the output signal of the second overcurrent detection means and being applied from the control circuit to the second switching element. A second flip-flop that is in a reset state according to the drive signal that is generated, and a second flip-flop that shuts off the drive signal to the second switching element by a signal that is output when the second flip-flop is in the set state 8. The inverter device according to claim 7, further comprising: 9. The first flip-flop is reset when the drive signal of the first switching element falls, and the second flip-flop is reset when the drive signal of the second switching element falls. The inverter device according to claim 8, which is in a state. 10. A DC power supply, first and second switching elements connected in series to an output terminal of the DC power supply, and third and third switching elements connected in series at both ends of the first and second switching elements. 4 switching elements, and the third and fourth
The fifth and sixth switching elements connected in series at both ends of the switching element, the connection points of the first and second switching elements, the connection points of the third and fourth switching elements, and the fifth and sixth switching elements. First to third filter circuits respectively connected to connection points of the switching elements, and the first to third filter circuits
A control circuit for applying a drive signal to each control terminal of a sixth switching element to turn on / off each of the switching elements, and by turning on / off the first to sixth switching elements, In an inverter device for generating a three-phase alternating current output from first to third filter circuits, the first current detection means for detecting a current flowing through the first or second switching element as a voltage corresponding to the current The second or third switching device is connected in series with the first or second switching device, and the second current detection means detects the current flowing through the third or fourth switching device as a voltage corresponding to the current. A third current detecting means, which is connected in series with the element and detects the current flowing through the fifth or sixth switching element as a voltage corresponding to the current, is provided in the fifth or fifth switching element. Is connected in series with a sixth switching element, and stops the on / off operation of the first or second switching element when the detection voltage of the first current detection means becomes equal to or higher than a predetermined voltage. No. 1 overcurrent protection unit, and a second overcurrent for stopping the on / off operation of the third or fourth switching element when the detection voltage of the second current detection unit exceeds a predetermined voltage. When the detection voltage of the protection means and the third current detection means exceeds a predetermined voltage, the fifth or sixth switching element is turned on.
An inverter device comprising: a third overcurrent protection means for stopping an off operation. 11. The first overcurrent protection means includes a first overcurrent detection means for outputting an overcurrent detection signal when the detection voltage of the first current detection means exceeds a predetermined voltage. A first flip-flop which is set according to an output signal of the first overcurrent detection means and is reset according to a drive signal applied from the control circuit to the first or second switching element. And a first cutoff unit that cuts off a drive signal to the first or second switching element by a signal output when the first flip-flop is in a set state. The overcurrent protection means includes a second overcurrent detection means that outputs an overcurrent detection signal when the detection voltage of the second current detection means exceeds a predetermined voltage, and the second overcurrent detection means. According to the output signal of A second flip-flop which is in a reset state in response to a drive signal applied from the control circuit to the third or fourth switching element, and when the second flip-flop is in a set state A second cutoff unit that cuts off a drive signal to the third or fourth switching element according to a signal to be output, wherein the third overcurrent protection unit detects the detection voltage of the third current detection unit. When the voltage exceeds a predetermined voltage, a third overcurrent detection means for outputting an overcurrent detection signal, and a set state according to an output signal of the third overcurrent detection means and the control circuit A third flip-flop that is in a reset state according to the drive signal applied to the fifth or sixth switching element, and a signal that is output when the third flip-flop is in the set state. The inverter apparatus according to "claim 10" and a third shut-off means for interrupting the drive signal to the fifth or sixth switching element by. 12. The first flip-flop is in a reset state when the drive signal of the first or second switching element falls, and the first flip-flop is in the reset state when the drive signal of the third or fourth switching element falls. The second flip-flop is in the reset state, and when the driving signal of the fifth or sixth switching element falls, the third flip-flop is reset.
The flip-flop of 1 is brought into a reset state.
1] Inverter device of description.