JP3254633B2 - EEP-ROM simultaneous test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simultaneously testing EEP-ROMs in a memory tester.

[0002]

2. Description of the Related Art An EEP-ROM is a read-only memory that can be electrically erased and rewritten, and its storage performance is gradually stabilized by repeatedly writing data after manufacturing. There are characteristics to do. For this reason, after fabrication, the number of times of repeated writing is appropriately defined, the test data is written by the memory tester a specified number of times, and the storage performance is stabilized and the quality is inspected. However, the specified number of times is not simple. First, the test data is written a plurality of [N] times, for example, 20 times in succession into the EEP-ROM to be inspected, and then the pass / fail is determined. Regardless of pass / fail, this continuous writing and pass / fail determination is repeated a plurality of times [S] times, for example, up to 10 times. On the other hand, in order to increase the efficiency of inspection in response to the recent increase in the production of EEP-ROMs, a plurality of memory testers are tested in parallel at the same time.

FIG. 3 shows a schematic configuration of a main part of a memory tester 10 for simultaneously testing a plurality of n EEP-ROMs by the above-described double-structure test method. The memory tester 10 includes a computer (CPU) 1, a pattern generator 2, a plurality of n sets of test circuits 3-1 to 3-n, and a ROM.
A control unit (EEPROM CONT unit) 4 is provided. Each of the test circuits 3-1 to 3-n has the same configuration, and includes a waveform generator 31, a drive amplifier 32, and a determiner 33 having a comparator 331 and a register 332 (RG). Each drive amplifier 32 has a plurality of n EEP-Rs.
DUs corresponding to OM51 to 5-n (# 1 to #nDUT)
T data input terminal _Di and write enable terminal WE
Each comparator 331 is connected to a data output terminal D _O. In addition, from the pattern generation unit 2, each determination unit
The expected data [D _K ] necessary for the judgment is given to the 33 comparators 331. Hereinafter, each test unit 3 and each DUT 5
Therefore, the test procedure for the test unit 3-1 for the DUT # 1 (hereinafter simply referred to as # 1) will be described. When the CPU 1 executes the test program, the pattern generator 2 generates the control signal [CONT] and the pattern data [PT] that is continuous a plurality of [N] times. A write enable signal [WE] and test data [D _i ] having a waveform suitable for the test corresponding to each pattern data [PT] are generated, and the drive amplifier 32 generates the # 1 enable terminal WE and the input data terminal, respectively. D _i and the test data [D _i ] is overlaid and written. Here, as for the waveform of the test data [D _i ], this waveform is a pulse having a considerably narrower width than the waveform of the normal write data. From the above, test data [D _i ]
Of the [N] consecutive write is completed, it is read, the read data [D _R] inputs is output from the data output terminal D _O to one terminal of the comparator 331, the above-mentioned input to the other terminal It is compared with the expected data [D _K ], and if they match, # 1 is determined to be non-defective. In the above description, each of the DUTs # 1 to #n has a slow speed in stabilizing the storage performance due to the variation in the characteristics. Therefore, some of the DUTs are determined to be non-defective at an intermediate stage. First, [N] times of continuous writing to all the DUTs and the determination of good or bad at each repetition are repeated up to [S] times. The failure result [D _F ] of only the [S] -th test is stored in the register 332 (RG) of the determination unit.
Stop signal from ROMCONT section 4 [S _T] is the waveform generating unit 31
Sent to When the [S] tests are completed, the test is sent to the CPU 1 and the evaluation data of each DUT is output.

[0004]

The EEP-ROM
Can be rewritten up to, for example, 10,000 times, but has a property that storage performance gradually deteriorates as the number of times of rewriting increases. For this reason, although the waveform of the test data [D _i ] is a narrow pulse as described above, the above [N]
Since continuous writing and [S] repetition tests are always performed, deterioration of storage performance is inevitable.
On the other hand, according to the results, there is a slow speed, but before [S] times,
In most cases, all DUTs are determined to be good. Therefore, it is necessary to improve the test method so as to avoid deterioration of the storage performance of the DUT as much as possible and to shorten the inspection throughput time. The present invention has been made based on the above idea, and has as its object to provide a simultaneous test method that avoids deterioration of the storage performance of an EEP-ROM and improves inspection throughput.

[0005]

According to the present invention, there is provided a method for simultaneously testing an EEP-ROM which has attained the above-mentioned object, wherein each of said determination units is provided in said memory tester before said number of repetitions [S] is reached. When there are EEP-ROMs determined to be non-defective, when each of the EEP-ROMs is determined to be non-defective, a stop signal is sent from the determination unit to the waveform generation unit, and each EEP-ROM determined to be non-defective is determined.
Stop writing test data [D _i ] to. In addition, the test is repeated on each EEP-ROM that is not determined to be non-defective during this time, up to [S] times, and the quality of each is determined.

[0006]

In the above simultaneous test method, the EEP-ROM determined to be non-defective by each judging unit before the test reaches a plurality of repetition times [S] is determined by the judging unit when it is judged to be non-defective. A stop signal is sent to the waveform generator to stop the writing of the test data [D _i ], so that the storage performance does not deteriorate thereafter. On the other hand, the remaining EEP-ROMs which were not determined to be non-defective products were subjected to the test repeated up to the number of repetitions [S].
Each pass / fail is determined. However, as mentioned above,
In most cases, all EEP-ROMs are determined to be non-defective before the number of times [S] is reached, and the simultaneous test is stopped when all are determined to be non-defective, thereby shortening the throughput time. You.

[0007]

FIG. 1 shows a configuration of an embodiment of a memory tester 10 'to which the present invention is applied, and FIG. 2 is a schematic flowchart showing a test procedure for FIG. FIG.
Has the same configuration as the memory tester 10 shown in FIG. However, when the DUT 5 is determined to be non-defective and the defective data [D _F ] is not stored in the register 332 of each determination unit 33, the corresponding waveform generation unit 31
Is provided with a function of sending a stop signal [ _ST ].

A procedure for writing a test signal in the memory tester 10 'will be described below with reference to FIG. 1 and FIG. Test start (step) causes CPU
1 executes the test program, the pattern generator 2 generates the control signal [CONT] and the pattern data [PT] continuous [N] times, and the waveform generator 31 to which these have been input receives the control signal [CONT]. a write enable signal [WE] by, test data [D _i] and the generated respectively, which are the input data terminal D _i and enable terminal WE of each DUT5 by drive amplifier 32 corresponding to the respective pattern data [PT] The test data [D _i ] is overlaid and written. Then, each of the read data _{[D R]} Each comparator (CO
Enter the MP) 331 is compared with the expected data _{[D K], [D R} ] = [D K] (YES in step) and a D
The UT is determined to be good. Up to this point, it is the same as the conventional one. When it is determined to be non-defective, stop signal to the waveform generator 31 from RG332 determination unit 33 [S _T] is Ru is output.
Separately , when the result is obtained for all DUTs, EE
Stop signal from PROMCONT section 4 _{[S T]} is sent to the waveform generating unit 31, a test for the DUT data [D
Writing of [ _i ] is stopped. Next, it is checked whether or not the number of repetitions has reached [S]. If the number has not reached, the routine returns to the step and is repeated up to the step, and writing to the non-defective DUT is stopped. When the number of times is reached, the answer is YES at the step,
PASS / FAIL is taken into RG332 only in the S-th time. Then, each defective data [ _DF ] stored in the RG 332 is sent to the CPU 1, and the simultaneous test of all DUTs is completed (10). However, if all the DUTs are determined to be good before reaching [S] times, the routine directly shifts from step to step, and subsequent [S]
This means that the tests up to the first test are omitted and the throughput is reduced. Incidentally, in the above case, [D _F ] is not stored in the RG 332 at the time of verification. Therefore RG 332
Will remain through. Instead, a real-time PA
The SS / FAIL signal is sent to the EEPROM CONT unit 41. The EEPROM CONT unit 4 receives real-time PASS / FAIL signals from each DUT, and receives all DUT-P
The ASS / FAIL signal is sent to the pattern generator, and the stop signal [ _ST ] is sent to the waveform generator 31. Therefore,
For example, if all DUTs pass before the specified number of times,
When the pattern generator receives the ALL-PASS signal,
Accept the L-PASS signal as a pattern stop,
Force termination. Therefore, at the time of this operation, the fail memory is unnecessary.

[0009]

As described above, in the simultaneous test method according to the present invention, a plurality of Es to be simultaneously tested are used.
Of the EP-ROMs, those which are determined to be non-defective before the number of repetitions [S] is reached, the writing of the test data [ _Di ] after the determination is stopped, and the deterioration of the storage performance is avoided. , Each EEP-ROM has the number of repetitions [S]
In most cases, all are judged to be good products before.
The throughput time is shortened accordingly, and EEP-
The effect of contributing to guaranteeing the quality of the ROM and improving the efficiency of a plurality of simultaneous tests is significant.

[Brief description of the drawings]

FIG. 1 is a memory tester 1 to which the present invention is applied.
It is a lineblock diagram in one Example of 0 '.

FIG. 2 is a schematic flowchart showing a test procedure for FIG. 1;

FIG. 3 is a schematic configuration diagram of a main part of the memory tester 10;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Computer (CPU), 2 ... Pattern generation part, 3
-1 to 3-n: Test circuit, 31: Waveform generator, 32: Drive amplifier, 33: Judgment unit, 331: Comparator, 332: Register (RG), 4: EEPROMCONT, 5: EEP
-ROM, 10: Conventional memory tester, 10 ': Memory tester to which the present invention is applied, # 1 to #n: Number of EEP-ROM (DUT) to be tested simultaneously, [PT] ...
Test pattern data, [CONT] ... control signal,
[D _i] test data, [WE] ... write enable signal, [D _R] ... read data, [N] ... number of consecutive times, [S]
… Repeated test count, [D _K ]… Expected data, [D _F ]
... bad data, [S _T] ... stop signal, step numbers to (10) ... flow.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 16/00-16/34 G01R 31/28

Claims (1)

(57) [Claims] 1. A plurality of EEP-ROMs are subjected to a simultaneous test, and test data [D _i ] is successively written to each of the EEP-ROMs a plurality of [N] times, and the [N]
A plurality of waveform generation units that perform writing repeatedly consecutively a plurality of times [S] times, and each of the EEP-RO
M to read data [D _R] as compared to the expected data [D _K], the memory tester comprising a determination unit acceptability multiple determines each respective EEP-ROM, the number of repetitions [S] Before reaching, when there is an EEP-ROM determined to be non-defective by each of the determination units, when each is determined to be non-defective, a stop signal is sent from the determination unit to the waveform generation unit, and The test data [D _i ] for each EEP-ROM determined to be non-defective
Writing is stopped, and a test is repeated for each EEP-ROM which is not determined to be non-defective during this time, up to the [S] times described above, and the quality of each EEP-ROM is determined. Simultaneous testing method.