KR20010084673A - Memory device capable of high speed testing with low frequency tester and the method thereof - Google Patents

Abstract

PURPOSE: A memory device capable of a high speed operation test with a low frequency tester and a test method thereof are provided, which can verify a high speed operation with a low frequency tester. CONSTITUTION: A high speed memory device(110) includes a memory core cell region(120) and a peripheral logic region(130). The memory core cell region is a memory block where a plurality of memory cells are arranged in rows and columns. The peripheral logic region(130) includes addresses and control signals which are transferred to the memory core cell region and it includes data paths. The peripheral logic region(130) includes a test mode control logic part(121), a BIST logic part(132) and a high speed interface part(133). While testing the high speed memory device, the test mode control logic part is connected with an external tester(200) and tests the high speed memory device directly according to a test pattern provided from the tester or loads the test pattern onto a part(A) of the memory core cell region. The BIST logic part converts the test pattern loaded on the part of the memory core cell region into a format by which the high speed interface part can receive it.

Description

Memory device capable of high speed testing with low frequency tester and the method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a memory device capable of high-speed operation test even with a low frequency tester and a test method thereof.

In general, semiconductor memory devices test for good or bad by an external tester. As a method for determining the quantity and defect, the memory cell data is read after writing a test pattern to the memory cells when the memory core cell area is tested, and the read data and the written data (expected) There is a way to compare (expected data). Thus, if the expected data and the read data are the same, it is determined as a pass, and if it is different, it is determined as a failure. The test pattern is configured in various ways, and is determined in the form of an address sequence for selecting a memory cell and data written in the memory cell. Types of such test patterns include checker boards, column bars, row bars, diamonds, and marches.

And, a test pattern in testing peripheral logic regions that interface with memory core cell regions is associated with fault coverage. Fault coverage is the ratio of the number of detectable faults to the expected total number of faults. Controllability refers to the ability of each node in a circuit to be implemented as a specific signal by a value set by the circuit input. Observability refers to the ability to determine the specific signal of each node in the circuit and observe its output by controlling the circuit input. Fault coverage is improved by enhancing controllability and observability. So the test pattern for the peripheral logic region should be a test pattern with improved fault coverage. Since the peripheral logic area provides a path of data read from the memory core cell area, the test pattern for the memory core cell area described above is also used to test the peripheral logic area.

These test patterns increase test coverage and may be provided directly from an external tester. In contrast, as shown in FIG. 1, test patterns are stored in a ROM 31 in the high-speed memory device 10 and then referred to as a built-in self test (hereinafter referred to as 'BIST'). The memory core cell area 20 may be tested through the logic unit 32 and the high speed interface unit 33. The ROM 31, the beast logic unit 32, and the high speed interface unit 33 belong to the peripheral logic area 30. Many test patterns are required to increase test coverage. However, when a large number of test patterns are stored in the ROM 31, the size of the ROM increases, thereby increasing the size of the high speed memory device.

On the other hand, as the memory device becomes faster, it is preferable that the tester for testing the memory device also be a high frequency tester. However, when the high speed memory device is tested using the existing low frequency tester for the utilization of the facility, the verification of the actual high speed operation is insufficient even though the memory cell of the memory core cell area is verified.

Accordingly, there is a need for a method capable of verifying high speed operation without increasing the size of the high speed memory device.

An object of the present invention is to provide a high speed memory device capable of verifying high speed operation even using a low frequency tester.

Another object of the present invention is to provide a test method of the high speed memory device.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a conventional high speed memory device.

2 is a block diagram of a high speed memory device according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of the high speed memory device of FIG. 2.

In order to achieve the above object, the present invention provides a memory device that operates at a high speed, comprising: a memory cell area in which a plurality of memory cells are arranged; a test mode control logic unit loading a test pattern into a portion of the memory cell area during a test; And an interface unit that operates at a high speed with the memory cell area according to the test pattern.

Preferably, the interface unit further includes a built-in self test (BIST) logic unit for converting the test pattern into an inputable format of the interface unit, and the memory device is connected to a tester operated at a low frequency during the test. The high speed operation is verified.

According to another aspect of the present invention, there is provided a test method of a memory device, comprising: a first step of testing memory cells in a memory cell region, a second step of loading a test pattern in a portion of the verified memory cell region; And a third step of testing an interface unit of the memory device using the test pattern. The first step may further include a step of verifying whether the memory cells are good or bad by testing at a low frequency, and the third step may further include converting the test pattern into a format suitable for high-speed operation of the interface unit. .

According to the present invention, even if the memory device is tested with a low frequency tester, the high speed operation of the memory device can be verified and the size of the memory device is not greatly increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

2 illustrates a high speed memory device according to an embodiment of the present invention. Referring to this, the high speed memory device 110 includes a memory core cell region 120 and a peripheral logic region 130. The memory core cell area 120 is a memory block in which a plurality of memory cells are arranged in rows and columns. The peripheral logic area 130 is an area including paths of addresses, control signals, and data transmitted to the memory core cell area 120. In particular, the peripheral logic area 130 includes a test mode control logic unit 131, a BIST logic unit 132, and a high speed interface unit 133.

When the high speed memory device is tested, the test mode control logic unit 131 is connected to the external tester 200 to directly test the high speed memory device 110 or to test the test pattern according to the test pattern provided by the tester 200. A portion A of the core cell region 120 is loaded. The beast logic unit 132 converts the test pattern loaded in the portion A of the memory core cell region 120 into a format that the high speed interface unit 133 can receive. The high speed interface unit 133 is a place where actual operations are performed with the memory cells in the memory core cell area 120 in operation of the high speed memory device 110.

The operation during the test of the high speed memory device 110 is described as follows with reference to FIG. 3.

In the first step, the memory cells in the memory core cell region 120 are tested by the test patterns provided by the external tester 200. At this time, since the tester 200 is a conventional low frequency device, memory cells are verified to be operated at a low frequency. As a result, when a defective cell is detected, the high speed memory device is determined to be defective, or when the defective cell is repairable, the high speed memory device is used as a good product through a method of repairing the defective cell. If the low frequency operation test determines that the memory cells are good, the process proceeds to the next second step.

The second step loads a predetermined test pattern provided from the tester 200 to a portion A of the memory core cell region 120 which has been verified to operate at low frequency in the first step. In this case, the test pattern may be a test pattern that may increase test coverage, and is a test pattern in consideration of fault coverage of the high speed interface unit 133.

The third step activates the bee logic unit 132 to transfer the test pattern loaded in the portion A of the memory core cell region 120 to the high speed interface unit 133. At this time, the test pattern is converted into a format that can be received by the high speed interface unit 133.

The fourth step is a step of determining whether the high speed interface unit 133 is operated at high speed according to the converted test pattern. If the high speed operation is performed, the test is completed by a good product determination, and if the high speed operation is not performed, the test is finished as a defective determination.

Through the above method, even when the high speed memory device 110 is tested by the low frequency tester, the high speed memory device is operated by operating the high speed interface unit 133 using a test pattern loaded in a portion A of the memory core cell region 120. Fast operation verification of 110 is possible. Since the test pattern stored in the conventional ROM is loaded in the portion A of the memory core cell region 120, an area such as a ROM for storing the test pattern is no longer needed. Therefore, the size of the high speed memory device 110 is that the size of the high speed memory device 110, even if there is a test mode control logic unit 131 for loading the test pattern in the portion (A) in the memory core cell region 120 ) Does not increase significantly compared to the area.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Even if the high speed memory device is tested with the low frequency tester, the high speed operation of the high speed memory device can be verified by operating the high speed interface unit using a test pattern loaded in a portion of the memory core cell region. Further, even if there is a test mode control logic section for loading a test pattern into a portion in the memory core cell region, the size of the fast memory device does not increase because its size is small compared to the conventional ROM region.

Claims (6)

In a high speed memory device, A memory cell area in which a plurality of memory cells are arranged; A test mode control logic unit loading a test pattern into a part of the memory cell area during a test; And And an interface unit communicating with the memory cell area according to the test pattern. The memory device of claim 1, wherein the memory device And a built-in self test (BIST) logic unit for converting the test pattern into an inputable format of the interface unit. The memory device of claim 1, wherein the memory device And the tester is connected to a tester operated at a low frequency during the test. In the test method of a memory device, A first step of testing memory cells in a memory cell area within the memory device; Loading a test pattern into a portion of the verified memory cell area; And And a third step of testing an interface unit of the memory device using the test pattern. The method of claim 4, wherein the first step And testing the low frequency to verify the quantity and defect of the memory cells. The method of claim 4, wherein the third step And converting the test pattern into a format suitable for high speed operation of the interface unit.