JP3251263B2 - Printed circuit board return path disconnection check system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring design of a printed circuit board, and more particularly to a system for searching a wiring path.

[0002]

2. Description of the Related Art The operating frequency of a digital circuit on a printed circuit board is increasing year by year, and problems such as disturbance of signal waveforms and increase of electromagnetic radiation occur due to electromagnetic characteristics which could be ignored so far. ing. One of the causes of these problems is that when wiring exists above and below the power supply layer and the ground layer, impedance mismatch due to the shape of the power supply layer and the ground layer, and the current return path (return path) is divided or detoured It has been confirmed that this is because

However, it is very difficult to take countermeasures after assembling the actual machine. Therefore, various simulators have been developed to analyze the cause in advance. For example, Japanese Patent No. 2722694 discloses a system that performs a wiring process using a grid model when there is a wiring obstacle. However, the power and ground layers are divided and modeled, and the electrical and magnetic calculations are performed to determine the characteristics. Therefore, the number of nets to be analyzed is enormous. As a result, there arises a problem that the calculation time increases enormously. In addition, there are many situations in which simulation cannot be performed due to the limitation of the machine capacity.

[0004]

SUMMARY OF THE INVENTION The present invention provides a system in which, at the design stage, a portion where a return path is divided or detours is searched from layout data which has been arranged and routed, and a countermeasure can be studied. The purpose is to do. Still another object of the present invention is to provide a system which can predict a return path generated after wiring or a return path generated from wiring based on only the connection information of elements before wiring and present a countermeasure plan.

[0005]

A printed circuit board return path disconnection check system according to the present invention extracts a wiring layer after wiring and its shape from wiring information indicating the shape of the wiring after wiring. One of the plane layers to be selected, the shape of the plane layer is extracted from the plane layer information, and the plane layer selection unit that outputs the shapes of the wiring layer and the plane layer, based on the information from the plane layer selection unit, In the wiring-plane layer overlap detecting section, which detects whether or not the wiring exists only on a single plane layer based on the wiring shape of the wiring layer and the shape of the plane layer, If it is detected that the wiring is not located only on a single plane layer, the wiring path is changed so that the wiring is searched so that the wiring exists only on the single plane layer. Is output to a result file, and if a route only on a single plane layer cannot be obtained even when the wiring route is changed, an ideal wiring route search unit is output to that effect to a result file. .

Further, the present invention provides a return path division check system for avoiding division of a return path of a printed circuit board from information before wiring, and has a rectangular area creating section, a plane layer selecting section, and an area-plane. The rectangular area creating unit includes component position information on a printed circuit board, component shape, component shape information indicating the position of component terminals, and wiring between components. From a netlist, which is a list of a wiring network indicating a connection relationship, the positions of component terminals connected to each other via wiring are determined, a rectangular area is created by surrounding all of these component terminals, and the plane layer selecting unit Selects a plane layer from the plane layer information and outputs it together with the rectangular area,
Then, the area-plane layer overlap detection unit detects whether or not the rectangular area overlaps only a single plane layer. If the rectangular area overlaps over the divided plane layers, all the component terminals are disconnected. It is detected whether or not it exists only on one plane layer of the specified plane layers. If all the component terminals exist only on this one plane layer, it is confirmed that a return path along the wiring can be secured. This is output to a result file, and when a component terminal exists over the divided plane layer, it is output that a return path cannot be secured.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, when designing the arrangement and wiring of a printed circuit board of a digital circuit, an overlap between a power supply layer and a ground layer (hereinafter referred to as a plane layer) adjacent to the wiring is checked, and the wiring is formed in a slit of the plane layer. A system that searches for whether it can be dealt with by changing the wiring route when the return current in the plane layer that exists on the To provide.

An embodiment of a check system according to the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of the present invention.
1 shows a configuration of a return path disconnection check system 1. The return path disconnection check system 1 receives as input wiring information 11 and plane layer information 12 after wiring, and selects a plane layer adjacent to the wiring layer above and below the wiring layer. A wiring-plane layer overlap detection unit 3 for detecting whether a wiring exists only on a single plane layer by superimposing images, and a route through which a feedback current flows along the wiring (hereinafter, a return path) ) And an ideal wiring route search unit 4 for searching whether or not the above can be secured. Then, the detection and search results are output to the result file 13.

[0009] As shown in FIG.
Obtains the shape of the wiring indicating the route of the wiring after the wiring from the wiring information 11. Then, the shape of the plane layer adjacent to the wiring layer is extracted from the plane layer information 12, and the above-described wiring shape and the shape of the plane layer are supplied to the wiring-plane layer overlap detection unit 3. The wiring-plane layer overlap detection unit 3 superimposes the wiring shape and the image of the plane layer shape, and checks whether the wiring exists only on a single plane layer. Here, when the wiring does not exist on the single plane layer, the return path is divided, and the wiring information and the plane information are input to the ideal wiring path searching unit 4. Here, it is sought whether a wiring can be present only on a single plane layer by changing the wiring route. If the wiring can be changed only on a single plane due to the change of the wiring route, the fact is output to the result file 13. If wiring cannot be performed on the single plane layer even if the wiring route is changed, information indicating that another measure is necessary is output to the result file 13.

The operation of this embodiment will be described below. FIG.
As shown in the figure, the signal layer 32 which is a wiring layer to be considered
Is sandwiched between the two plane layers 31 and 33, the plane layer selection unit 2 determines in step A1 of FIG.
1 is selected, and the shape of the plane layer 31 and the wiring information of the signal layer 32 are passed to the wiring-plane layer overlap detection unit 3. At this time, the wiring has a shape like 41 in FIG.
2 and 43, the wiring-plane layer overlap detection unit 3 superimposes those images to form a wiring 41
Are present on the two types of plane layers 42 and 43 and are not wires on a single plane layer (FIG. 3, step B1). In this case, the return path is divided. Next, the wiring is changed by the ideal wiring path search unit 4 to search for a wiring path only on the single plane layer. In FIG. 5, since it is possible to wire only on the single plane layer 42 by using the wiring 44, the fact that an ideal return path is possible is output to the result file 13 by changing the wiring path (see FIG. 5). 3, step B3).

Next, the case where the plane layers are 52 and 53 in FIG. 6 will be described. In step B1 of FIG.
Is detected over the two types of plane layers 52 and 53. Therefore, the ideal wiring path search unit 4 searches whether the wiring can be drawn on a single plane layer. However, since the plane layers at the start point and the end point of the wiring 51 are different from 52 and 53, the wiring path is changed. However, the result is that an ideal return path cannot be obtained. Therefore, the fact that another solution is required is output to the result file 13 (FIG. 3, step B).
4).

In step A3 of FIG. 2, the plane layer 33 below the signal layer 32 is selected, and the same processing as described above is performed. That is, if the result of both steps B1 is YES in the processing of steps A2 and A4, it is confirmed that the return path of the wiring is secured along the wiring and is an ideal return path. . If the result of step B1 is NO, a wiring path is searched for and processed by the same processing as that for the plane layer 31. As described above, the layout data indicating the shape and route of the arranged and routed wiring is searched for the portion where the return path is divided and detoured, and a countermeasure is presented. Can be considered.

Next, another embodiment of the present invention will be described. The basic configuration is as described above, but it is characterized in that a region to be wired when wiring is not performed is predicted, and whether a return path is secured in the region is checked and countermeasures are taken. FIG. 7 shows the configuration. In the figure, a return path division check system 61 includes a rectangular area creation unit 62,
It comprises a plane layer selection unit 63 and an area-plane layer overlap detection unit 64.

The rectangular area creating section 62 includes an element disposed on the printed circuit board 80 shown in FIG. 10, that is, component position information 66 which is information on the position of the component, and the shape of the component and its component terminals. From the component shape information 67 indicating where the component is located and the net list 68 of the wiring indicating which component terminal is connected to which component terminal, the corresponding net indicating the wiring connection relationship between a plurality of components is obtained. A component terminal position, which is a position where a wiring route to be routed between components always passes, is determined, and a rectangular area surrounding all of these component terminals is created. This area includes substantially all component terminals included in the wiring net.

FIG. 10 will be described as a specific example. When the component terminals of the corresponding net are the component terminals 82 and 84, the positions of the component terminals 82 and 84 are obtained from the component position information 66 and the component shape information 67, and a rectangular area 85 connecting the component terminals 82 and 84 is created (FIG. 8, Step C1). Next, the plane layer selection unit 63 selects one plane layer from the plane layer information 69, and selects the plane layer and the rectangular area 85.
Are passed to the area-plane layer overlap detection section 64. Here, it is detected that the rectangular area 85 overlaps both of the two plane layers 86 and 87 (FIG. 9, step C3).
Next, it is checked whether or not all the component terminals of the corresponding net exist only on one plane layer. In the case of FIG. 10, it is detected that the component terminals 82 and 84 exist only on the plane layer 86 (FIG. 9, step C4). As a result, it can be seen that this net can secure a return path along the wiring depending on the wiring path at the time of wiring, and the result is output to the result file 65.

As another specific example, the case of FIG. 11 will be described. The component terminal of the corresponding net is the component terminal 92
And 94, a rectangular area 95 is created in the manner described above (FIG. 8, step C1).
6 and 97 are input to the area-plane overlap detection unit 64. As a result, the rectangular area 95 has two plane layers 96, 9
7 is detected (step C3 in FIG. 9). Since the component terminals 92 and 94 connected to this net exist on different plane layers 96 and 97, respectively, it is understood that the return path is divided regardless of the wiring path (FIG. 9). Step C4). Therefore, the fact that a countermeasure is required is output to the result file 65 (step C6).

The above processing is performed for all plane layers (step C2 in FIG. 8), and information on the plane layer that can secure a return path is provided. As described above, according to the present embodiment, it is possible to predict the return path generated after the wiring from the connection information before the wiring only by dividing or detouring the circuit and to propose a countermeasure, thereby reducing the correction after the wiring design. Can be

[0018]

As described above, according to the return path disconnection check system according to the present invention, the return path is separated or detoured from the layout data already arranged and routed, thereby avoiding the return path disconnection at the design stage. There is an effect that a countermeasure can be taken, and furthermore, there is an effect that it is possible to avoid a return path division by predicting a wiring area and checking a return path in the area when wiring is not performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of a return path disconnection check system according to the present invention.

FIG. 2 is a view showing a flow of information processing in the embodiment shown in FIG. 1;

FIG. 3 is a view showing a flow of information processing in the embodiment of FIG. 1;

FIG. 4 is a diagram showing an arrangement of wiring layers in the embodiment of FIG. 1;

FIG. 5 is a diagram showing a process of detecting an overlap between a wiring layer and an adjacent plane layer to determine a change in a wiring path;

FIG. 6 is a diagram showing an overlapping state between a wiring layer and an adjacent plane layer.

FIG. 7 is a diagram showing a configuration of another embodiment of the return path disconnection check system of the present invention.

FIG. 8 is a view showing a flow of information processing in the embodiment shown in FIG. 7;

FIG. 9 is a diagram showing a flow of information according to the embodiment shown in FIG. 7;

FIG. 10 is a diagram showing a process of detecting an overlap between a wiring region and a plane layer and obtaining a wiring route in the embodiment shown in FIG. 7;

FIG. 11 is a diagram showing an overlapping state between a wiring region and an adjacent plane layer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 return path disconnection check system 2 plane layer selection unit 3 wiring-plane layer overlap detection unit 4 ideal wiring route search unit 11 wiring information 12 plane layer information 13 result file 31, 33 plane layer 32 signal layer (wiring layer) 61 return path Division check system 62 Rectangular area creation unit 63 Plane layer selection unit 64 Area-plane layer overlap detection unit 65 Result file 66 Part position information 67 Part shape information 68 Netlist 69 Plane layer information 80 Printed circuit boards 81, 83 Parts (elements) 82 , 84 Component terminals (terminals) 85, 95 Rectangular area 86, 87 Plain layer 91, 93 Components (elements) 92, 94 Component terminals (terminals) 96, 97 Plain layer

Claims (2)

(57) [Claims] 1. A wiring layer after wiring and its shape are extracted from wiring information, one of the plane layers adjacent to the wiring layer is selected, and the shape of this plane layer is extracted from the plane layer information. A plane layer selection unit that outputs the shape of the plane layer, and, based on information from the plane layer selection unit, whether the wiring exists only on a single plane layer based on the wiring shape of the wiring layer and the shape of the plane layer. A wire-plane layer overlap detection unit for detecting whether or not the wire-plane layer overlap detection unit detects that the wire is not only on a single plane layer; Search for a wiring route only on a single plane layer, output this wiring route to the result file,
If the route only on the single plane layer is not obtained even after changing the wiring route, the return path division of the printed circuit board is characterized by comprising an ideal wiring route search unit for outputting the fact to a result file. Check system. 2. A return path division check system comprising a rectangular area creating section, a plane layer selecting section, and an area-plane layer overlap detecting section, wherein the rectangular area creating section includes: position information of a component on a printed circuit board; From the component shape information indicating the shape of the component and the position of the component terminal and the netlist indicating the connection relationship of the wiring between the components, the positions of the component terminals connected to each other via the wiring are obtained, and all of these component terminals are obtained. The plane layer selecting unit selects a plane layer from the plane layer information and outputs the selected plane layer together with the rectangular region. The area-plane layer overlap detector detects that the rectangular area is Detects whether it overlaps only the plane layer of
When overlapping over the divided plane layer, it is detected whether or not all the component terminals are present only on one plane layer among the divided plane layers, and only on the one plane layer. When a component terminal exists over a divided plane layer, a signal that a return path cannot be secured is output. Path disconnection check system.