JP4915803B2 - Substrate layout check apparatus, method thereof and computer program thereof - Google Patents

Description

  The present invention relates to a technique for checking a layout of a printed circuit board, and more particularly to a board layout check apparatus, a method thereof, and a computer program thereof for checking the presence of a via that becomes a current return path among vias of a printed circuit board.

  In recent years, the operating frequency of electronic circuits has increased, and countermeasures against electromagnetic radiation of electronic devices have become important. One measure for reducing electromagnetic radiation is to suppress electromagnetic radiation from a printed circuit board. In order to suppress electromagnetic radiation from the printed circuit board, it is important to secure a return current path.

  Usually, a solid surface is often provided on a power supply layer, a ground layer (hereinafter collectively referred to as a plane layer), etc., as a return current path for a current flowing through a signal line wired on a substrate. When a solid surface is provided immediately above or directly below the signal line, the return current of the high-frequency signal has a property of flowing through the solid surface directly above or directly below the signal line.

  However, if there is a slit on the solid surface immediately above or directly below the return path of the signal line, the return current bypasses the slit. When the detour is large, the loop area through which the current flows increases, and the electromagnetic wave radiated from the loop also increases.

  Similarly, when signal lines are provided in a plurality of layers, a signal line in a certain layer is connected to a signal line in another layer through a signal via. When the current of the signal line flows through the vias, the return current flows through the vias between the plane layers connecting the solid surfaces serving as return current paths. When the via serving as the return path is located farther than the via through which the original signal flows, the loop area through which the current flows increases and the electromagnetic wave radiated from the wiring also increases. Therefore, it is desirable to provide a via that connects the plane layers as a return current path near the via through which the signal flows.

  As a technique for checking whether or not a via serving as a return path is provided near a signal via, there is an invention disclosed in Patent Document 1 below.

The return path check system for a printed wiring board disclosed in Patent Document 1 includes a plane layer selection unit that selects a plane layer to be checked for each signal layer, and a return path across the slit in the plane layer to be checked. For each location where the return path crosses the slit, a bypass capacitor / via information extractor that extracts the bypass capacitor and via information in the extraction range, and the extracted bypass capacitor and via A bypass path detection unit that determines whether or not the return current can be bypassed, a bypass path determination unit that determines whether there is a detected bypass path within the determination range, and a finally obtained bypass path And an information output unit for outputting the above information.
JP 2007-11629 A

  However, the return path check system disclosed in Patent Document 1 described above cannot correctly check a return path that passes through a plane layer via a plurality of vias. Therefore, when each via detected within the range cannot bypass the return current, it is not determined that the return current is bypassed even if the return current can be bypassed via a plurality of vias.

  Therefore, the designer needs to confirm whether or not there is a return current path through a plurality of vias at a place where it is determined that there is no bypass path. Since such confirmation requires more time than confirmation of a single via, there is a problem that the time required for design modification increases.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a board layout check apparatus and method capable of correctly evaluating a return path passing through a plane layer via a plurality of vias. And providing a computer program thereof.

According to one aspect of the present invention, the board layout check device extracts a check via that requires a return current path check from the vias connected to the wiring to be checked based on the layout information of the printed circuit board. A plurality of plane interlayer vias connecting the plane layers of at least three plane layers, which are return current paths of the check vias extracted by the first extraction means and the first extraction means, are extracted as return path vias. A second extraction unit; a calculation unit that calculates a return path evaluation value from the positional relationship between each of the check via extracted by the first extraction unit and the return path via extracted by the second extraction unit; Determining means for determining suitability of the return path based on the return path evaluation value calculated by the means; Including.

  Preferably, the second extraction means includes a plurality of plane interlayer vias connecting the plane layer one layer below the uppermost layer to which the check via is connected and the plane layer one layer below the lowermost layer to which the check via is connected. Are extracted as return path vias.

  Preferably, the second extracting means connects a plane layer having the smallest layer interval from the uppermost layer to which the check via is connected and a plane layer having the smallest layer interval from the lowermost layer to which the check via is connected. Are extracted as return path vias.

Preferably, the second extraction means extracts a plurality of planes interlayer via Oh Ru from the check via within a certain distance as a return path via.

  Preferably, the second extraction unit determines that an error has occurred when no plane interlayer via can be extracted.

  Preferably, the second extraction unit determines that an error has occurred when no return path via has been extracted.

  Preferably, the calculating means sets the area of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via as the return path evaluation value.

  Preferably, the calculation means uses the length of the outer periphery of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via as the return path evaluation value.

  Preferably, the calculating means calculates a via length between the check via and the return path via from a length of an outer periphery of a surface sandwiched between the return path via and the check via in a plane passing through the return path via and the check via. The value obtained by subtracting the sum is used as the return path evaluation value.

  Preferably, the determination unit compares the minimum value of the return path evaluation value calculated by the calculation unit with a predetermined determination value, and determines that an error occurs when the minimum value of the return path evaluation value exceeds the determination value. .

According to another aspect of the present invention, there is provided a board layout check method for causing a computer to execute a process of checking a layout of a printed circuit board, which is connected to a wiring to be checked based on layout information of the printed circuit board. Extracting a check via that requires a return current path check from a plurality of vias, and a plurality of plane layers connecting the plane layers of at least three plane layers that are the return current paths of the extracted check via Extracting a via as a return path via , calculating a return path evaluation value from the positional relationship between the extracted check via and the extracted return path via , and based on the calculated return path evaluation value computer and determining the appropriateness of the return path To be executed.

According to still another aspect of the present invention, there is provided a computer program for causing a computer to execute a process for checking a layout of a printed circuit board, which is connected to a wiring to be checked based on layout information of the printed circuit board. Extracting a check via that requires a return current path check from a plurality of vias, and a plurality of plane layers connecting the plane layers of at least three plane layers that are the return current paths of the extracted check via Extracting a via as a return path via , calculating a return path evaluation value from the positional relationship between the extracted check via and the extracted return path via , and based on the calculated return path evaluation value And a step for determining whether the return path is appropriate. To be executed by the data.

According to an aspect of the present invention, the second extraction unit serves as a return current path of the check via extracted by the first extraction unit, and includes a plurality of plane layers connecting the plane layers of at least three plane layers. extracted via a return path via, calculating calculating means, the return route evaluation value from the positional relationship between each of the first return path via extracted by checking via the second extracting means extracted by the extraction means Therefore, it is possible to correctly evaluate the return path that passes through the plane layer via a plurality of vias.

  In addition, the second extraction means may include a plurality of plane interlayer vias that connect the plane layer one layer below the uppermost layer to which the check via is connected and the plane layer on the lowermost layer to which the check via is connected. Since the return route via is extracted, the return route via can be easily extracted.

  Further, the second extraction means connects a plane layer having the narrowest layer interval from the uppermost layer to which the check via is connected and a plane layer having the smallest layer interval from the lowermost layer to which the check via is connected. Since the plane interlayer via is extracted as the return path via, the return path via can be easily extracted.

The second extraction means, since to extract a plurality of planes interlayer via Oh Ru from the check via within a certain distance as a return path via, it can be prevented from unnecessary plane interlayer via is extracted with Become.

  In addition, since the second extraction means determines an error when no plane interlayer via can be extracted, it is possible to easily identify a location where the return current cannot be bypassed.

  In addition, since the second extraction unit determines an error when no return path via can be extracted, it is possible to easily identify a portion where the return current cannot be bypassed.

  In addition, since the calculation means uses the area of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via as the return path evaluation value, the return path evaluation value is easily calculated. It becomes possible.

  In addition, since the calculation means uses the length of the outer periphery of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via as the return path evaluation value, the return path evaluation value is easy. Can be calculated.

  Further, the calculation means calculates the sum of the via lengths of the check via and the return path via from the outer circumference of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via. Since the value obtained by subtracting is used as the return path evaluation value, the return path evaluation value can be easily calculated.

  Further, the determination unit compares the minimum value of the return path evaluation value calculated by the calculation unit with a predetermined determination value, and determines that an error occurs when the minimum value of the return path evaluation value exceeds the determination value. Thus, it becomes possible to easily identify a location where return current bypass is insufficient.

  FIG. 1 is a block diagram showing an example of a hardware configuration of a board layout check apparatus according to an embodiment of the present invention. This board layout check device is equipped with a computer main body 1, a display device 2, an FD drive 3 to which an FD (Flexible Disk) 4 is mounted, a keyboard 5, a mouse 6, and a CD-ROM (Compact Disc-Read Only Memory) 8. CD-ROM device 7 and network communication device 9 are included. The board layout check program is supplied by a recording medium such as FD4 or CD-ROM8.

  A board layout check program is executed by the computer main body 1 to check the layout of the printed circuit board. The board layout check program may be supplied to the computer main body 1 from another computer via a communication line.

  A computer main body 1 shown in FIG. 1 includes a CPU (Central Processing Unit) 10, a ROM (Read Only Memory) 11, a RAM (Random Access Memory) 12, and a hard disk 13. The CPU 10 performs processing while inputting / outputting data to / from the display device 2, FD drive 3, keyboard 5, mouse 6, CD-ROM device 7, network communication device 9, ROM 11, RAM 12 or hard disk 13. The board layout check program recorded in the FD 4 or the CD-ROM 8 is stored in the hard disk 13 by the CPU 10 via the FD drive 3 or the CD-ROM device 7. The CPU 10 performs a layout check on the printed circuit board by loading a board layout check program from the hard disk 13 to the RAM 12 and executing it appropriately.

  FIG. 2 is a block diagram showing a functional configuration of the board layout check apparatus according to the embodiment of the present invention. The board layout check apparatus includes an input unit 21, a board layout creation unit 22, a storage unit 23, a layout check unit 24, and an output unit 25.

  The input unit 21 includes the keyboard 5 and the mouse 6 shown in FIG. 1, and a printed circuit board designer inputs information necessary for board layout design via the input unit 21.

  The board layout creation unit 22 creates board layout information based on the information input by the input unit 21. The storage unit 23 stores the board layout information created by the board layout creating unit 22.

  The layout check unit 24 determines whether or not a via return current path exists appropriately based on the board layout information stored in the storage unit 23. The layout check unit 24 is realized by the computer main body 1 executing a board layout check program.

  The output unit 25 includes the display device 2 shown in FIG. 1 and the like, and outputs check target wiring, check vias, return path vias, determination results, and the like, which will be described later.

  The layout check unit 24 includes a check target wiring extraction unit 31, a check via extraction unit 32, a necessary connection plane layer extraction unit 33, a plane interlayer via extraction unit 34, a return path via extraction unit 35, and a return path evaluation value. A calculation unit 36 and a determination unit 37 are included.

  The check target wiring extraction unit 31 extracts a check target wiring that is a wiring that needs to check the return current path of the via based on a preset condition.

  The check via extraction unit 32 extracts a check via that requires a return current path check from the vias connected to the check target wiring extracted by the check target wiring extraction unit 31. The check via extraction unit 32 may extract all vias on the check target wiring, or may extract only vias that satisfy a preset condition.

  The necessary connection plane layer extraction unit 33 extracts a necessary connection plane layer that is a plane layer that needs to be connected as a return current path.

  The plane interlayer via extraction unit 34 extracts a plane interlayer via that connects the plane layers in the printed circuit board.

  The return path via extraction unit 35 connects one or a plurality of plane layers connecting the necessary connection plane layers extracted by the necessary connection plane layer extraction unit 33 from the plane interlayer vias extracted by the plane interlayer via extraction unit 34. Vias are extracted as return path vias.

  The return path evaluation value calculation unit 36 calculates a return path evaluation value from the positional relationship between the return path via and the check via extracted by the return path via extraction unit 35. The return path evaluation value calculation unit 36 uses the area and outer peripheral length of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via as the return path evaluation value.

  Further, the distance away from the check via may be simply set as the evaluation value. In this case, a value obtained by subtracting the sum of the via lengths of the check via and the return route via from the outer peripheral length of the surface sandwiched between the return route via and the check via in the plane passing through the return route via and the check via. You may make it.

  The determination unit 37 compares the return route evaluation value calculated by the return route evaluation value calculation unit 36 with a predetermined determination value to determine whether the return route is appropriate.

  FIG. 3 is a diagram showing an example of a cross section of an eight-layer substrate. This printed circuit board is constituted by the first layer 41 to the eighth layer 48. The first layer 41 and the eighth layer 48 are layers on which signal lines are arranged, and the second layer 42, the fourth layer 44, and the seventh layer 47 are the same plane layer. The other layers are layers on which the other plane layer and signal lines are arranged.

  FIG. 4 is a flowchart showing an example of a processing procedure of the board layout check apparatus according to the embodiment of the present invention. The processing procedure of the board layout check apparatus will be described with reference to the cross-sectional view of the 8-layer board shown in FIG.

  First, the check target wiring extraction unit 31 determines a target wiring to be checked for a return path of a signal flowing through a via from a condition determined by a designer or the like (S11). For example, if the wiring type such as clock / data, the frequency of the signal to be transmitted, the rise / fall time, etc. satisfy the set conditions, the wiring is set as the check target wiring. Alternatively, the designer himself / herself may directly specify the wiring to be checked.

  Next, the check target wiring extraction unit 31 selects a wiring to be processed from the plurality of extracted check target wirings (S12). The check target wiring extraction unit 31 selects an arbitrary check target wiring, and after the processing of the check target wiring is completed, sequentially selects other check target wirings and performs processing for all the check target wirings.

  Next, the check via extraction unit 32 extracts vias on the check target wiring selected by the check target wiring extraction unit 31 as check vias (S13). The check via extraction unit 32 may extract all vias on the selected check wiring as check vias, or may extract check vias based on a predetermined condition. Alternatively, check vias that directly meet the conditions may be extracted, for example, vias within a certain range may be used as check vias without extracting check vias from the check target wiring. In addition, the designer may directly specify the check via.

  Next, the check via extraction unit 32 selects a via for performing a determination process from the extracted plurality of check vias (S14). The check via extraction unit 32 selects an arbitrary check via, and after the processing of the check via is completed, sequentially selects other check vias and processes all the check vias.

  Next, the necessary connection plane layer extraction unit 33 extracts a plane layer that needs to be connected as a return path (S15). If a plane layer is always provided in the upper and lower layers of the wiring through which signals flow (if the wiring layer is an outer layer wiring, the lower layer or the upper layer), the layer one layer below the uppermost layer of the layer to which the check via is connected To the layer one layer above the lowest layer of the layer to which the check via is connected is extracted as a plane layer requiring connection.

  Also, in some designs where there is no plane layer above and below the line through which the signal flows, the check via is connected from the plane layer with the smallest layer spacing from the top layer of the layer to which the check via is connected. From the lowest layer of the layer to the plane layer having the smallest layer interval is extracted as a plane layer that needs to be connected. When the power plane and the ground plane exist as the plane layer, the plane layer that needs to be connected as the return path is extracted for each of the power source and the ground.

  FIGS. 3A and 3B show a case where there are planes in the upper and lower layers of the layer where the signal line is arranged. If the via 52 is selected as the check via, the via 52 is the first layer. 41 and the eighth layer 48. In this case, the necessary connection plane layer extraction unit 33 extracts the second layer 42 and the seventh layer 47 as the necessary connection plane layers.

  Next, the plane interlayer via extraction unit 34 extracts vias connecting the plane layers extracted by the necessary connection plane layer extraction unit 33 (S16). The plane interlayer via extraction unit 34 extracts vias satisfying a certain condition for each check via, such as extracting vias connecting plane layers within a certain distance set in advance from the check via for each check via.

  Further, all the plane interlayer vias may be extracted or may be extracted for each check wiring. If no plane interlayer via is extracted, the determination process of the check via selected as an error as the determination result is terminated.

  In FIG. 3A and FIG. 3B, vias 54a, 54b, 54c, 54d and 54e connecting the plane layers are extracted as plane layer vias.

  Next, the return path via extraction unit 35 selects a plane interlayer via that connects the necessary connection plane layers extracted by the necessary connection plane layer extraction unit 33 from the plane interlayer vias extracted by the plane interlayer via extraction unit 34. A return route via is extracted (S17). At this time, not only a single plane interlayer via but also a plurality of plane interlayer vias connecting the necessary connection plane layers are extracted.

  In FIG. 3A, since the plane interlayer vias 54a and 54b connect the second layer 42 and the seventh layer 47, which are necessary connection plane layers, the vias 54a and 54b are extracted as return path vias. .

  Similarly in FIG. 3B, the via 54e is extracted as a return path via. Further, since the via 54c connects the second layer 42 and the fourth layer 44, and the via 54d connects the fourth layer 44 and the seventh layer 47, the via 54c and the via 54d are passed through. Thus, the second layer 42 and the seventh layer 47 which are necessary connection plane layers are connected. Therefore, the two via groups of the via 54c and the via 54d are extracted as return path vias.

  At this time, the vias 54c and 54d connected in the fourth layer 44 need to be connected within a certain path length. If the via 54c and the via 54d are not connected in the fourth layer 44, or if they are connected largely detoured, the via 54c and the via 54d are not extracted as return path vias.

  As a reference for the path length connecting vias, a value based on a straight line distance between vias that is the shortest path length is used. For example, a value obtained by multiplying a linear distance between vias by a predetermined value greater than 1 is used as a reference value for the path length. When the straight line distance and the path length are equal, the loop area is the smallest and ideal. The designer may determine the path length standard and the path length allowed in the connection between the vias.

  Next, the return route via extraction unit 35 determines whether or not a return route via is extracted (S18). If the return path via does not exist, it is determined as an error (S18, No), the determination process of the selected check via is terminated, and the process proceeds to step S24.

  Further, when there is one or more return path vias (S18, Yes), the return path via extraction unit 35 selects a target return path via. The return path via extraction unit 35 selects an arbitrary return path via as the target return path via (S19), and after the processing of the selected return path via is completed, sequentially selects other return path vias and returns all returns. Process for route via.

  At this time, the return path via extraction unit 35 selects the plurality of extracted return path vias as one target return path via. For example, in FIG. 3B, vias 54c and 54d are selected as one return path via.

  Next, the return path evaluation value calculation unit 36 calculates a value for evaluating the return path from the selected target return path via and check via (S20). In FIGS. 3A and 3B, the check via and the target return path via are passed through the check via and the target return path via in consideration that the size of the loop formed by the check via and the target return path via affects the noise. The area of the plane sandwiched between the return path via and the check via in the plane is calculated as the return path evaluation value.

  In FIG. 3A, the return path evaluation value calculation unit 36 calculates the area of the hatched portion as the evaluation value of the via 54a extracted as the return path via. Further, the area of the dotted line is calculated as the evaluation value of the via 54b extracted as the return path via.

  In FIG. 3B, the return path evaluation value calculation unit 36 calculates the area of the hatched portion as the evaluation value of the vias 54c and 54d, and calculates the area of the dotted line portion as the evaluation value of the via 34e. Thus, when a plurality of vias become return path vias, an evaluation value is calculated for each via, and the evaluation value is calculated by adding them.

  The return path evaluation value may be the length of the outer periphery of the surface sandwiched between the return path via and the check via in the plane passing through the target return path via and the check via. When the distance away from the check via is simply used as the evaluation value, the length of the outer circumference of the surface between the target return path via and the check via in the plane passing through the target return path via and the check via In addition, a value obtained by subtracting the sum of the via lengths of the check via and the target return path via may be used.

  Next, the return route evaluation value calculation unit 36 determines whether there is a return route via whose return route evaluation value is not calculated among the return route vias extracted by the return route via extraction unit 35 (S21). ). If there is a return path via for which the return path evaluation value is not calculated (S21, No), the process returns to step S19, selects a return path via for which the return path evaluation value is not calculated, and repeats the same processing. .

  Further, when the return path evaluation value calculation unit 36 calculates the return path evaluation values for all the return path vias (Yes in S20), the return path evaluation value is the most among the return path evaluation values calculated for each return path via. A return route via having a small value is extracted, and the return route evaluation value is extracted and set as the minimum return route evaluation value.

  In FIG. 3A, since the area of the shaded portion is smaller than that of the dotted line portion, the via 54a is extracted as the return route via having the minimum return route evaluation value, and the area of the shaded portion is the minimum return route evaluation value. It becomes.

  Similarly, in FIG. 3B, the via 54c and the via 54d are extracted, and the area of the hatched portion becomes the minimum return path evaluation value. At this time, a path passing through the extracted via is defined as a signal return path.

  Next, the determination unit 37 compares the minimum return path evaluation value calculated by the return path evaluation value calculation unit 36 with the determination value. If the minimum return path evaluation value exceeds the determination value, the determination of the selected check via is performed. The result is an error (S23). As this determination value, a value allowed as the minimum return path evaluation value is set in advance.

  The determination unit 37 determines whether there is a via for which the determination process has not been completed among the check vias extracted by the check via extraction unit 32 (S24). If there is a via for which the determination process has not ended (S24, No), the process returns to step S14, selects the target check via for which the determination process has not ended, and repeats the same process.

  When the determination process is completed for all the check vias extracted by the check via extraction unit 32 (S24, Yes), the process is not completed in the check target wiring extracted by the check target wiring extraction unit 31. It is determined whether or not a check target wiring exists (S25). If there is a check target wiring that has not been processed (S25, No), the process returns to step S12 to select a check target wiring that has not been processed, and the same processing is repeated. Further, when all the check target wiring processes are completed (S25, Yes), the process is terminated.

  In the above description, the determination is made by comparing the minimum return path evaluation value and the determination value. However, in order to increase the processing speed, the presence / absence of a return path that simply satisfies the condition is simply checked, and the return path evaluation value calculated by the return path evaluation value calculation unit 36 is compared with the determination value. If it is below, processing for the next check via may be performed.

  In this case, only when the return path evaluation values of all return path vias exceed the determination value, the check via determination result is an error. If at least one return path evaluation value is less than the judgment value among the return path evaluation values, there may be a return path via with a smaller evaluation value, but which via is actually the evaluation value of the return path. It is not possible to determine whether is the minimum.

  As described above, according to the board layout check device of the present embodiment, the return path via extraction unit 35 extracts a plurality of plane interlayer vias as return path vias, and the return path evaluation value calculation unit 36 sets a plurality of planes. Since the evaluation value is calculated from the return path via including the interlayer via and the check via, it is possible to correctly evaluate the return path via the plane layer via the plurality of plane interlayer vias. This makes it possible to determine the locations that need to be corrected, and to efficiently correct the board layout.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows an example of the hardware constitutions of the board | substrate layout check apparatus in embodiment of this invention. It is a block diagram which shows the functional structure of the board | substrate layout check apparatus in embodiment of this invention. It is a figure which shows an example of the cross section of an 8-layer board | substrate. It is a flowchart which shows an example of the process sequence of the board | substrate layout check apparatus in embodiment of this invention.

Explanation of symbols

  1 computer main body, 2 display device, 3 FD drive, 4 FD, 5 keyboard, 6 mouse, 7 CD-ROM device, 8 CD-ROM device, 9 network communication device, 10 CPU, 11 ROM, 12 RAM, 13 hard disk, 21 Input section, 22 Substrate layout creation section, 23 Storage section, 24 Layout check section, 25 Output section, 31 Check target wiring extraction section, 32 Check via extraction section, 33 Necessary connection plane layer extraction section, 34 Plane interlayer via extraction section 35, return path via extraction unit, 36 return path evaluation value calculation unit, 37 determination unit, 41 to 48, first layer to eighth layer, 51 signal line, 52, 54a to 54e plain interlayer via, 53 return route.

Claims (12)

First extraction means for extracting a check via that requires a return current path check from the vias connected to the wiring to be checked based on the layout information of the printed circuit board;
Second extraction means for extracting, as return path vias, a plurality of plane interlayer vias connecting the plane layers of at least three plane layers, which are return current paths of the check vias extracted by the first extraction means;
Calculating means for calculating a return path evaluation value from a positional relationship between each of the check via extracted by the first extracting means and the return path via extracted by the second extracting means;
A board layout check apparatus comprising: a determination unit that determines whether or not the return path is appropriate based on the return path evaluation value calculated by the calculation unit.   The second extraction means includes a plurality of plane interlayer vias connecting a plane layer one layer below the uppermost layer to which the check via is connected and a plane layer one layer below the lowermost layer to which the check via is connected The board layout check device according to claim 1, wherein the device is extracted as a return path via.   The second extracting means connects a plane layer having the smallest layer spacing from the uppermost layer to which the check via is connected and a plane layer having the smallest layer spacing from the lowermost layer to which the check via is connected. The board layout check device according to claim 1, wherein the plane interlayer via is extracted as a return path via. It said second extraction means extracts a plurality of planes interlayer via Ru Ah within a certain distance from the check via a return path via the substrate layout checking device according to claim 1.   5. The board layout check device according to claim 1, wherein the second extraction unit determines that an error occurs when no plane interlayer vias can be extracted. 6.   5. The board layout check apparatus according to claim 1, wherein the second extraction unit determines that an error occurs when no return path via is extracted. 6.   The calculation unit according to any one of claims 1 to 6, wherein an area of a surface sandwiched between the return path via and the check via in a plane passing through the return path via and the check via is set as a return path evaluation value. Board layout check device.   The calculation means according to any one of claims 1 to 6, wherein a length of an outer periphery of a surface sandwiched between the return path via and the check via in a plane passing through the return path via and the check via is set as a return path evaluation value. The board layout check device according to 1.   The calculation means calculates the sum of the via lengths of the check via and the return path via from the length of the outer periphery of the surface sandwiched between the return path via and the check via in the plane passing through the return path via and the check via. The board layout check apparatus according to claim 1, wherein the subtracted value is used as a return path evaluation value.   The determination unit compares the minimum value of the return path evaluation value calculated by the calculation unit with a predetermined determination value, and determines an error when the minimum value of the return path evaluation value exceeds the determination value. The board | substrate layout check apparatus in any one of Claims 1-9. A board layout check method for causing a computer to execute a process of checking a layout of a printed circuit board,
Extracting a check via that requires a return current path check from the vias connected to the wiring to be checked based on the layout information of the printed circuit board;
Extracting a plurality of plane interlayer vias that connect the plane layers of at least three plane layers as return path vias of the extracted check vias as return path vias;
Calculating a return path evaluation value from a positional relationship between each of the extracted check via and the extracted return path via;
A board layout check method that causes a computer to execute a step of determining whether or not a return path is appropriate based on the calculated return path evaluation value. A computer program for causing a computer to execute processing for checking a layout of a printed circuit board,
Extracting a check via that requires a return current path check from the vias connected to the wiring to be checked based on the layout information of the printed circuit board;
Extracting a plurality of plane interlayer vias that connect the plane layers of at least three plane layers as return path vias of the extracted check vias as return path vias;
Calculating a return path evaluation value from a positional relationship between each of the extracted check via and the extracted return path via;
A computer program causing a computer to execute a step of determining whether or not a return path is appropriate based on the calculated return path evaluation value.

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