JP3245342B2 - Manufacturing method of multilayer capacitor - Google Patents

Manufacturing method of multilayer capacitor

Info

Publication number
JP3245342B2
JP3245342B2 JP34225195A JP34225195A JP3245342B2 JP 3245342 B2 JP3245342 B2 JP 3245342B2 JP 34225195 A JP34225195 A JP 34225195A JP 34225195 A JP34225195 A JP 34225195A JP 3245342 B2 JP3245342 B2 JP 3245342B2
Authority
JP
Japan
Prior art keywords
dielectric
dielectric layer
multilayer capacitor
weight
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP34225195A
Other languages
Japanese (ja)
Other versions
JPH09186045A (en
Inventor
等 大小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP34225195A priority Critical patent/JP3245342B2/en
Publication of JPH09186045A publication Critical patent/JPH09186045A/en
Application granted granted Critical
Publication of JP3245342B2 publication Critical patent/JP3245342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チタンジルコン酸
バリウムを主成分とし、Li、Si、Bのうち少なくと
も1種を含有する誘電体層と、ニッケル等の卑金属から
なる内部電極層とを交互に積層してなる積層型コンデン
サの製法に関するものである。
[0001] The present invention relates to a method of alternately forming a dielectric layer containing barium titanium zirconate as a main component and containing at least one of Li, Si and B and an internal electrode layer made of a base metal such as nickel. The present invention relates to a method for manufacturing a multilayer capacitor formed by laminating the capacitors.

【0002】[0002]

【従来技術】従来、積層型コンデンサは、内部電極を構
成する電極層と誘電体層とを交互に積層した後、一体焼
成して製造されている。
2. Description of the Related Art Hitherto, a multilayer capacitor has been manufactured by alternately laminating electrode layers constituting an internal electrode and a dielectric layer and then firing them integrally.

【0003】ところで積層コンデンサを作製する場合、
従来のBaTiO3を主成分とする誘電体材料では、1
300〜1500℃で焼成するため、内部電極材料とし
ては、このような温度で溶融しないPt,Pd等の貴金
属が使用されてきた。
By the way, when manufacturing a multilayer capacitor,
In a conventional dielectric material mainly composed of BaTiO 3 , 1
Since firing is performed at 300 to 1500 ° C., noble metals such as Pt and Pd that do not melt at such a temperature have been used as the internal electrode material.

【0004】しかしながら、これらの貴金属は高価であ
り、高容量化を図るために内部電極数を増加させた場合
にはコストが著しく高くなるという問題があった。そこ
で、近年、安価なニッケル等の卑金属が内部電極材料と
して用いられている。
[0004] However, these noble metals are expensive, and there has been a problem that when the number of internal electrodes is increased in order to increase the capacity, the cost is significantly increased. Therefore, in recent years, inexpensive base metals such as nickel have been used as internal electrode materials.

【0005】しかしながら、ニッケル等の卑金属からな
る内部電極を用いた場合には、内部電極の酸化を防止す
るため還元雰囲気中で焼成しなければならず、そのよう
な雰囲気下で焼成すると、誘電体セラミックスが還元さ
れ絶縁性を失ってしまうという問題があった。
However, when an internal electrode made of a base metal such as nickel is used, it must be fired in a reducing atmosphere to prevent oxidation of the internal electrode. There is a problem that the ceramics are reduced and lose insulation.

【0006】そこで、近年では、還元雰囲気中で焼成し
た場合でも、誘電体セラミックスが還元されないよう
な、例えば、塩基性酸化物である(Ba,Ca,Sr)
Oを酸性酸化物であるTiO2に対して化学量論比より
過剰にしたチタン酸バリウム固溶体(Ba,Ca,S
r)(Ti,Zr)O3から成る基本成分と、Li2Oと
SiO2を含む添加成分とを含む誘電体磁器組成物が提
案されている(例えば、特公昭60−20851号公報
等参照)。
In recent years, therefore, basic oxides such as (Ba, Ca, Sr) which do not reduce dielectric ceramics even when fired in a reducing atmosphere.
Barium titanate solid solution (Ba, Ca, S) in which O is added in excess of stoichiometric ratio to TiO 2 as an acidic oxide
r) (Ti, Zr) a basic component consisting of O 3, a dielectric ceramic composition comprising an additive component containing Li 2 O and SiO 2 have been proposed (e.g., see JP-B-60-20851, etc. ).

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記の
ような従来の組成を用いた積層型コンデンサでは、高
温、高電圧の環境下で用いられる場合には製品寿命が短
いという問題があった。即ち、上記従来の組成では、高
温、高電圧の環境下では、誘電体磁器自体の電気伝導性
が高くなり、誘電体としての機能が低下し、誘電体とし
ての寿命が短くなるという問題があった。特に、近年で
は、高容量化のために誘電体層を薄層化する傾向にある
が、誘電体層が薄くなる程、高温、高電圧環境下におい
ては電気伝導性が高くなり易く、誘電体としての機能が
低下し易いという問題があった。
However, the multilayer capacitor using the above-mentioned conventional composition has a problem that the product life is short when used in a high temperature and high voltage environment. That is, in the above-described conventional composition, in a high-temperature, high-voltage environment, the electric conductivity of the dielectric porcelain itself increases, the function as a dielectric decreases, and the life as a dielectric decreases. Was. In particular, in recent years, there has been a tendency to reduce the thickness of the dielectric layer in order to increase the capacity. However, as the dielectric layer becomes thinner, the electrical conductivity tends to increase under high temperature and high voltage environments. There is a problem that the function of the device is easily deteriorated.

【0008】[0008]

【発明の目的】本発明は、誘電体磁器厚みが3〜10μ
mという薄い場合でも、高温、高電圧の環境下における
寿命を向上することができる積層型コンデンサの製法を
提供することを目的とする。
The object of the present invention is to provide a dielectric ceramic having a thickness of 3 to 10 μm.
It is an object of the present invention to provide a method of manufacturing a multilayer capacitor capable of improving the life under a high-temperature, high-voltage environment even when the thickness is as small as m.

【0009】[0009]

【課題を解決するための手段】本発明者は、上記問題に
対して鋭意検討した結果、チタンジルコン酸バリウムを
含有する主成分と、該主成分100重量部に対してL
i、Si、Bのうちの少なくとも一種をそれぞれLi2
O、SiO2、B23換算で総量0.4〜1.2重量部
となる仮焼された粒界相成分とを含有する誘電体形成膜
と、卑金属を含有する内部電極膜とを交互に積層した積
層成形体を 作製し、非還元性雰囲気において1200〜
1300℃で焼成し、最高温度から800℃までの降温
速度を20〜40℃/hr以下としたことにより、誘電
体層が薄層であっても高温、高電圧の環境下における寿
命を向上することができることを見い出し、本発明に至
った。
Means for Solving the Problems As a result of intensive studies on the above problem, the present inventor has found that barium titanium zirconate is used.
The main component to be contained , and L per 100 parts by weight of the main component
At least one of i, Si and B is Li 2
O, the total amount in SiO 2, B 2 O 3 in terms of 0.4 to 1. 2 parts by weight
Forming film containing calcined grain boundary phase component
And an internal electrode film containing a base metal alternately laminated.
A layer molded body is produced, and in a non-reducing atmosphere,
Baking at 1300 ° C, temperature drop from maximum temperature to 800 ° C
It has been found that by setting the speed to 20 to 40 ° C./hr or less, it is possible to improve the life under a high-temperature and high-voltage environment even if the dielectric layer is a thin layer.

【0010】即ち、本発明の積層型コンデンサの製法に
より作製される積層型コンデンサは、チタンジルコン酸
バリウムからなる主結晶相と、このチタンジルコン酸バ
リウム100重量部に対してLi、Si、Bのうちの少
なくとも一種をそれぞれLi2O、SiO2、B23換算
で総量0.4〜1.2重量部の割合で含有する偏析相と
を有する誘電体層と、卑金属からなる内部電極層とを交
互に積層してなる積層型コンデンサであって、前記誘電
体層が3〜10μmの厚みを有するとともに、前記誘電
体層の破断面において存在する偏析相数のうち60%以
上が結晶質であることを特徴とする。ここで、偏析相中
の結晶質が、Li,SiおよびBのうち少なくとも2種
を含有する複合酸化物からなることが望ましい。
That is, in the method for manufacturing the multilayer capacitor of the present invention,
The multilayer capacitor manufactured by the above-described method is characterized in that at least one of Li, Si, and B is Li 2 O, SiO 2 , A multilayer capacitor comprising a dielectric layer having a segregated phase containing a total amount of 0.4 to 1.2 parts by weight in terms of B 2 O 3 and an internal electrode layer made of a base metal alternately laminated. The dielectric layer has a thickness of 3 to 10 μm, and 60% or more of the number of segregated phases existing on the fracture surface of the dielectric layer is crystalline. Here, it is desirable that the crystalline material in the segregated phase be composed of a composite oxide containing at least two of Li, Si and B.

【0011】[0011]

【作用】本発明の積層型コンデンサの製法では、誘電体
層の厚みを3〜10μmと薄層化した場合でも、誘電体
としての機能を十分に有し、かつ、高温、高電圧の環境
下においても寿命を長くすることができる。
According to the method for manufacturing a multilayer capacitor of the present invention, even when the thickness of the dielectric layer is reduced to 3 to 10 μm, the capacitor has a sufficient function as a dielectric and can be used in a high-temperature, high-voltage environment. Can also extend the life.

【0012】即ち、高温、高電圧の環境下における寿命
は誘電体磁器中の粒界相を移動する電子の移動度に影響
されると考えられるが、結晶質の偏析相の方が非晶質の
場合よりも電子の移動度が小さいため、誘電体層中の全
粒界相成分数のうち60%以上を結晶質とすることによ
り、粒界相の電子の移動度を小さくすることができる。
That is, the life under high temperature and high voltage environment is considered to be affected by the mobility of electrons moving through the grain boundary phase in the dielectric porcelain, but the crystalline segregation phase is more amorphous. Since the mobility of electrons is smaller than in the case of the above, by making 60% or more of the total number of grain boundary phase components in the dielectric layer crystalline, the mobility of electrons in the grain boundary phase can be reduced. .

【0013】[0013]

【発明の実施の形態】本発明の積層型コンデンサの製法
は、チタンジルコン酸バリウムを含有する主成分と、該
主成分100重量部に対してLi,Si,Bのうちの少
なくとも一種をそれぞれLi 2 O、SiO 2 、B 2 3 換算
で総量0.4〜1.2重量部となる仮焼された粒界相成
分とを含有する誘電体形成膜と、卑金属を含有する内部
電極膜とを交互に積層した積層成形体を作製し、非還元
性雰囲気 において1200〜1300℃で焼成し、最高
温度から800℃までの降温速度を20〜40℃/hr
としたものであるが、本発明に用いられる誘電体層は、
例えば、Ba(Ti、Zr)O3100モル部に対して
CaTiO3を0.05〜8.0モル部含有する成分
と、該成分100重量部に対して、Nd23を0.3〜
0.8重量部、MnO2を0.1〜0.2重量部含有さ
せて、主成分が構成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer capacitor according to the present invention
Is a main component containing barium titanium zirconate,
For 100 parts by weight of the main component, a small amount of Li, Si, and B
At least one kind converted to Li 2 O, SiO 2 , B 2 O 3
At 0.4 to 1.2 parts by weight in total
-Containing dielectric-forming film and base metal-containing interior
Produce a laminated molded body in which electrode films are alternately laminated and perform non-reduction.
Baking at 1200-1300 ° C in a neutral atmosphere
The cooling rate from the temperature to 800 ° C is 20 to 40 ° C / hr.
Although, the dielectric layer used in the present invention,
For example, Ba (Ti, Zr) and component a CaTiO 3 containing 0.05 to 8.0 parts by mol with respect to O 3 100 molar parts, relative to the component 100 parts by weight, the Nd 2 O 3 0.3 ~
0.8% by weight and 0.1 to 0.2 part by weight of MnO 2 are contained to form a main component.

【0014】一方、例えば、Li2O、SiO2、B23
のモル比で表される三角図において、(Li2O,Si
2,B23)で示す、A(20,80,0)、B(7
0,30,0)、C(80,0,20)、D(40,2
0,40)の4点で囲まれる組成範囲の粒界成分を90
0℃以上の温度で仮焼し、Li、Si、Bのうち少なく
とも2種を含有する複合酸化物を作製する。そして、こ
のLi、Si、Bを含有する複合酸化物を上記主成分1
00重量部に対して、総量0.4〜1.2重量部添加含
有してなるものである。誘電体層中に、不純物としてA
23、Fe23、ZrO2等が混入する場合がある。
On the other hand, for example, Li 2 O, SiO 2 , B 2 O 3
In the triangular diagram represented by the molar ratio of (Li 2 O, Si
A (20, 80, 0) and B (7, O 2 , B 2 O 3 )
0, 30, 0), C (80, 0, 20), D (40, 2)
(0, 40) is 90%.
Calcination is performed at a temperature of 0 ° C. or higher to produce a composite oxide containing at least two of Li, Si, and B. Then, the composite oxide containing Li, Si, and B is mixed with the main component 1 described above.
The total amount is 0.4 to 1.2 parts by weight based on 00 parts by weight. In the dielectric layer, A
l 2 O 3 , Fe 2 O 3 , ZrO 2 and the like may be mixed.

【0015】チタンジルコン酸バリウム100重量部に
対してLi、Si、Bのうちの少なくとも一種をそれぞ
れLi2O、SiO2、B23換算で総量0.4〜1.2
重量部の割合で含有せしめたのは、Li、Si、Bが
0.4重量部よりも少ない場合には、高温、高電圧の環
境下における寿命が低下するからであり、また、1.2
重量部よりも多い場合には容量が低下するからである。
At least one of Li, Si and B is added to 100 parts by weight of barium titanium zirconate in a total amount of 0.4 to 1.2 in terms of Li 2 O, SiO 2 and B 2 O 3 respectively.
The reason for the inclusion in parts by weight is that when the content of Li, Si, and B is less than 0.4 parts by weight, the life under a high-temperature and high-voltage environment is reduced.
If the amount is more than the weight part, the capacity is reduced.

【0016】本発明においては、添加される粒界相成分
は、Li,Si,BをそれぞれLi2O、SiO2、B2
3換算で総量0.4〜1.2重量部含有すれば良く、
3種類の成分を必須成分とするものでもなく、2種でも
良い。これらのうちLiとSiの組み合わせは誘電率向
上という観点から特に望ましい。
In the present invention, the grain boundary phase components to be added are Li, Si and B, respectively, Li 2 O, SiO 2 and B 2.
O 3 may be contained amount 0.4 to 1.2 parts by weight in terms of,
The three components are not essential components, but may be two. Of these, a combination of Li and Si is particularly desirable from the viewpoint of improving the dielectric constant.

【0017】また、卑金属からなる内部電極層は、例え
ば、Ni、Co、Cu等からなるものである。
The internal electrode layer made of a base metal is made of, for example, Ni, Co, Cu or the like.

【0018】さらに、誘電体層の厚みを3〜10μmと
したのは、誘電体層の厚みが3μmより薄いと誘電体層
の作製が困難であるからであり、厚みが10μmよりも
厚くなると、高容量化を図ることができなくなるからで
ある。本発明の誘電体層の厚みは、高容量化および誘電
体層の作製の容易性という観点から5〜8μmであるこ
とが望ましい。
Further, the reason why the thickness of the dielectric layer is set to 3 to 10 μm is that if the thickness of the dielectric layer is smaller than 3 μm, it is difficult to manufacture the dielectric layer. If the thickness is larger than 10 μm, This is because high capacity cannot be achieved. The thickness of the dielectric layer of the present invention is desirably 5 to 8 μm from the viewpoint of increasing the capacity and facilitating the production of the dielectric layer.

【0019】また、誘電体層における偏析相のうち、L
i、Si、Bを含有する複合酸化物からなる偏析相は、
例えば、(3Li2O・B23+Li4SiO4)、(L
4SiO4)、(Li4SiO4+Li2O)のように表
現されるようなものがあり、このような偏析相が結晶質
であり、誘電体層中に存在する偏析相の個数の内、結晶
質である割合を一定に制御することにより、上記に示し
たように粒界相の電子の移動度を制御し、高温、高電圧
の環境下における製品寿命を長くすることができるので
ある。
Further, among the segregated phases in the dielectric layer, L
The segregated phase composed of the composite oxide containing i, Si, and B is
For example, (3Li 2 O · B 2 O 3 + Li 4 SiO 4), (L
i 4 SiO 4), there are those as expressed as (Li 4 SiO 4 + Li 2 O), such segregation phase is crystalline, the number of the segregation phase existing in the dielectric layer Of these, by controlling the ratio of being crystalline to constant, the mobility of electrons in the grain boundary phase can be controlled as described above, and the product life in a high-temperature, high-voltage environment can be extended. is there.

【0020】偏析相は、誘電体層の一断面(破断面)に
おいて、存在する偏析相の個数の内、60%以上が結晶
質であることが必要である。結晶質である偏析相の存在
の割合が60%よりも低い場合には、高温、高電圧下で
の寿命が顕著に短くなる。
It is necessary that 60% or more of the number of segregated phases existing in one cross section (fracture surface) of the dielectric layer is crystalline. When the proportion of the crystalline segregated phase is lower than 60%, the life under high temperature and high voltage is significantly shortened.

【0021】このように、結晶質である偏析相の存在の
割合を60%以上とするためには、焼成時において最高
温度から800℃までの降温速度を20〜40℃/hr
とすることが必要である。これは、降温速度を20〜4
0℃/hrとすることにより、偏析相の結晶化を促進
し、結晶質の偏析相の存在の割合を60%以上とするこ
とができるのである。
As described above, in order to make the proportion of the crystalline segregated phase 60% or more, the rate of temperature decrease from the maximum temperature to 800 ° C. during firing is 20 to 40 ° C./hr.
It is necessary to This means that the cooling rate is 20 to 4
By setting the temperature to 0 ° C./hr, the crystallization of the segregated phase is promoted, and the proportion of the crystalline segregated phase can be increased to 60% or more.

【0022】本発明の積層型コンデンサの製法は、先
ず、例えば、上記した誘電体磁器組成物に所定のバイン
ダー、可塑剤を添加し誘電体層用のスリップを作製する
とともに、例えば、Niに所定のバインダー、可塑剤を
添加し内部電極用のスリップを作製する。そして、台板
上に、誘電体層用のスリップをドクターブレード法によ
り複数回塗布し、所定厚みの誘電体成形膜を形成し、こ
の誘電体成形膜の表面に内部電極用スリップをスクリー
ン印刷して所定形状の内部電極膜を形成する。
In the manufacturing method of the multilayer capacitor of the present invention , first, for example, a predetermined binder and a plasticizer are added to the above-mentioned dielectric porcelain composition to prepare a slip for a dielectric layer. The binder and the plasticizer are added to prepare a slip for the internal electrode. Then, a slip for a dielectric layer is applied a plurality of times on the base plate by a doctor blade method to form a dielectric molded film having a predetermined thickness, and a slip for an internal electrode is screen-printed on the surface of the dielectric molded film. To form an internal electrode film having a predetermined shape.

【0023】この工程を所望の容量が得られるまで繰り
返した後、該積層体を酸素分圧が3×10-5〜3×10
-3Paの非還元性雰囲気において1200〜1300℃
で1〜5時間一体焼成し、この最高温度から800℃ま
での降温速度を20〜40℃/hrとする。この後、窒
素雰囲気において900〜1100℃で2〜7時間熱処
理することにより、本発明の積層型コンデンサを得る。
After repeating this process until a desired capacity is obtained, the laminate is subjected to an oxygen partial pressure of 3 × 10 -5 to 3 × 10 5
1200 to 1300 ° C in a non-reducing atmosphere of -3 Pa
For 1 to 5 hours, and the rate of temperature decrease from this maximum temperature to 800 ° C. is 20 to 40 ° C./hr. Thereafter, heat treatment is performed at 900 to 1100 ° C. for 2 to 7 hours in a nitrogen atmosphere to obtain the multilayer capacitor of the present invention.

【0024】[0024]

【実施例】出発原料として水熱合成法により得られた平
均粒径0.5μmのBa(Ti、Zr)O3粉末を用
い、このBa(Ti、Zr)O3100モル部に対して
平均粒径1.0μmのCaTiO3を0.05モル部添
加した成分を作製し、この成分100重量部に対してN
23を0.5重量部、MnO2を0.2重量部添加
し、混合して主成分を作製する。この主成分100重量
部に対して、Li2O、SiO2、B23のモル比が表1
に示す比となる仮焼した粒界相成分を、表1に示す量だ
け添加し、ZrO2ボールにより混合し、バインダー、
可塑剤を加え、誘電体層用スリップを得た。
EXAMPLES Using Ba (Ti, Zr) O 3 powder having an average particle size of 0.5μm obtained by hydrothermal synthesis method as a starting material, the average for this Ba (Ti, Zr) O 3 100 molar parts A component was prepared by adding 0.05 mol part of CaTiO 3 having a particle size of 1.0 μm.
0.5 parts by weight of d 2 O 3 and 0.2 parts by weight of MnO 2 are added and mixed to prepare a main component. The molar ratio of Li 2 O, SiO 2 , and B 2 O 3 to 100 parts by weight of the main component is shown in Table 1.
The calcined grain boundary phase component having the ratio shown in Table 1 was added in an amount shown in Table 1, and mixed with a ZrO 2 ball to form a binder.
A plasticizer was added to obtain a dielectric layer slip.

【0025】また、Niとテルピネオールを添加し、A
23ボールにより混合し、バインダー、可塑剤を加
え、内部電極層用スリップを得た。
Also, Ni and terpineol are added, and A
mixed by l 2 O 3 balls, a binder, a plasticizer is added to give a slip internal electrode layer.

【0026】そして、誘電体層用スリップを台板にドク
ターブレード法により複数回塗布して、焼成後の厚みが
表1の厚みとなるように誘電体成形膜を作製し、この誘
電体成形膜の上面に、内部電極層用スリップをクシ型構
造となるようにスクリーン印刷し、誘電体成形膜の形成
から電極膜の形成までの工程を20回繰り返し、誘電体
成形膜を20層有する積層成形体を作製した。この積層
成形体を熱圧着後、酸素分圧が3×10-4Paの非還元
性雰囲気において1250℃で2時間焼成し、800℃
までの降温速度を表1に示す速度として冷却した後、窒
素雰囲気中において1000℃で5時間熱処理した。こ
の後、該焼結体の両端面に、Cuからなる外部電極を形
成し、本発明の積層型コンデンサを得た。
Then, the dielectric layer slip is applied to the base plate a plurality of times by the doctor blade method, and a dielectric molded film is produced so that the thickness after firing becomes the thickness shown in Table 1. On the upper surface of the substrate, screen printing of the slip for the internal electrode layer is performed so as to form a comb-shaped structure, and the steps from the formation of the dielectric molded film to the formation of the electrode film are repeated 20 times, thereby forming a laminate having 20 dielectric molded films. The body was made. After thermocompression bonding of the laminated molded body, the laminated molded body is fired at 1250 ° C. for 2 hours in a non-reducing atmosphere having an oxygen partial pressure of 3 × 10 −4 Pa.
After cooling at the rate shown in Table 1, the heat treatment was performed at 1000 ° C. for 5 hours in a nitrogen atmosphere. Thereafter, external electrodes made of Cu were formed on both end surfaces of the sintered body to obtain a multilayer capacitor of the present invention.

【0027】このようにして得られた積層型コンデンサ
に対して、誘電体層厚みを走査型電子顕微鏡(SEM)
にて観察、測定するとともに、誘電体層中の粒界相成分
の存在状態を透過電子顕微鏡(TEM)にて観察した。
結晶質であるかどうかの確認は、個々の偏析相に対して
電子解析像が得られるかを確認することにより行い、任
意に選択した誘電体層中の50個の偏析相に対する結晶
質の偏析相数の割合(%)を求めた。
For the multilayer capacitor thus obtained, the thickness of the dielectric layer was measured by using a scanning electron microscope (SEM).
And the state of the grain boundary phase component in the dielectric layer was observed with a transmission electron microscope (TEM).
The confirmation of the crystalline state is performed by confirming whether an electron analysis image can be obtained for each segregated phase, and the crystalline segregation for 50 segregated phases in the arbitrarily selected dielectric layer is performed. The ratio (%) of the number of phases was determined.

【0028】また、容量をLCRメータで測定周波数1
kHz、入力信号レベル1Vrmsという条件で測定
し、誘電体層一層当たりの容量に換算して求めた。
The capacity is measured with an LCR meter at a measurement frequency of 1.
It was measured under the conditions of kHz and an input signal level of 1 Vrms, and was obtained by converting into a capacitance per one dielectric layer.

【0029】さらに、150℃の測定炉中で誘電体厚み
に対して8V/μmの電圧を印加し、ショート故障に至
るまでの時間(寿命)を測定し、この結果を表1に示
す。
Further, a voltage of 8 V / μm with respect to the thickness of the dielectric was applied in a measuring furnace at 150 ° C., and the time until the short-circuit failure (life) was measured. The results are shown in Table 1.

【0030】[0030]

【表1】 [Table 1]

【0031】この表1の結果より、本発明の試料では2
50nF以上の高容量であり、また、150℃、8V/
μmの電圧を印加した場合でも、ショート故障に至るま
での時間が185時間以上と長く、高温、高電圧の環境
下であっても、信頼性が高く長寿命であることが判る。
From the results in Table 1, it was found that the sample of the present invention
High capacity of 50 nF or more, and 150 ° C., 8 V /
Even when a voltage of μm is applied, the time until a short-circuit failure is as long as 185 hours or more, indicating that the device has high reliability and a long life even in a high temperature and high voltage environment.

【0032】図1に、本発明のNo.7の積層型コンデ
ンサの断面をTEMにて5000倍に拡大した結果を示
す。図において、符号1は誘電体層、符号2は内部電極
層、符号3は(Ba,Ca)(Ti,Zr)O3からな
るセラミック粒子、符号4は偏析相を示す。さらに、こ
の試料の誘電体磁器の断面をTEMにて10万倍に拡大
した結果を図2に示す。図において、符号3は(Ba,
Ca)(Ti,Zr)O3からなるセラミック粒子、符
号4は偏析相を示す。
FIG. 1 shows No. 1 of the present invention. 7 shows the result of enlarging the cross section of the multilayer capacitor No. 7 by 5000 times with a TEM. In the figure, reference numeral 1 denotes a dielectric layer, reference numeral 2 denotes an internal electrode layer, reference numeral 3 denotes ceramic particles made of (Ba, Ca) (Ti, Zr) O 3 , and reference numeral 4 denotes a segregation phase. FIG. 2 shows the result of magnifying the cross section of the dielectric ceramic of this sample by 100,000 times by TEM. In the figure, reference numeral 3 indicates (Ba,
Ceramic particles composed of Ca) (Ti, Zr) O 3 , reference numeral 4 denotes a segregated phase.

【0033】[0033]

【発明の効果】本発明の積層型コンデンサの製法では、
チタンジルコン酸バリウムを含有する主成分と、該主成
分100重量部に対してLi,Si,Bのうちの少なく
とも一種をそれぞれLi 2 O、SiO 2 、B 2 3 換算で総
量0.4〜1.2重量部となる仮焼された粒界相成分と
を含有する誘電体形成膜と、卑金属を含有する内部電極
膜とを交互に積層した積層成形体を作製し、非還元性雰
囲気において1200〜1300℃で焼成し、最高温度
から800℃までの降温速度を20〜40℃/hrと
し、誘電体層の破断面において、Li,SiおよびBの
うち少なくとも2種を含有する複合酸化物からなり、6
0%以上の結晶質を有する偏析相を生成させることか
ら、誘電体の厚みを3〜10μmと薄層化した場合で
も、誘電体としての機能を十分に有し、かつ、高温、高
電圧の環境下においても寿命を長くすることができる。
【The invention's effect】In the manufacturing method of the multilayer capacitor of the present invention,
A main component containing barium titanium zirconate;
Per 100 parts by weight of Li, Si, B
And one kind each Li Two O, SiO Two , B Two O Three Total in conversion
A calcined grain boundary phase component in an amount of 0.4 to 1.2 parts by weight;
-Containing dielectric film and internal electrode containing base metal
A laminated molded body in which the film and the film are alternately laminated is manufactured, and a non-reducing atmosphere is formed.
Fired at 1200-1300 ° C in ambient atmosphere, maximum temperature
From 40 to 800 ° C / hr.
In the fracture surface of the dielectric layer, Li, Si and B
A composite oxide containing at least two of them,
Whether to generate a segregated phase having 0% or more of crystallinity
When the thickness of the dielectric is reduced to 3 to 10 μm,
Also have a sufficient function as a dielectric, and
The life can be prolonged even under a voltage environment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】試料No.7の積層型コンデンサの断面をTE
Mにて5000倍に拡大した図である。
FIG. The cross section of the multilayer capacitor of No. 7 is TE
It is the figure expanded 5000 times by M.

【図2】試料No.7の積層型コンデンサの誘電体層磁
器の断面をTEMにて10万倍に拡大した図である。
FIG. 7 is a diagram in which the cross section of the dielectric ceramic of the multilayer capacitor of No. 7 is magnified 100,000 times by TEM.

【符号の説明】[Explanation of symbols]

1・・・誘電体層 2・・・内部電極層 3・・・セラミック粒子 4・・・偏析相 DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2 ... Internal electrode layer 3 ... Ceramic particles 4 ... Segregation phase

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】チタンジルコン酸バリウムを含有する主成
分と、該主成分100重量部に対してLi,Si,Bの
うちの少なくとも一種をそれぞれLi2O、SiO2、B
23換算で総量0.4〜1.2重量部となる仮焼された
粒界相成分とを含有する誘電体形成膜と卑金属を含有
する内部電極膜とを交互に積層した積層成形体を作製
非還元性雰囲気において1200〜1300℃で焼
成し、最高温度から800℃までの降温速度を20〜4
0℃/hrとしたことを特徴とする積層型コンデンサの
製法。
A main component containing barium titanium zirconate.
And at least one of Li, Si and B with respect to 100 parts by weight of the main component , respectively, Li 2 O, SiO 2 , B
It is calcined a total 0.4 to 1.2 parts by weight 2 O 3 in terms of
Dielectric forming film containing grain boundary phase component and base metal
To produce a laminated molded body with alternately laminated internal electrode films
And fired at 1200-1300 ° C in a non-reducing atmosphere.
And the cooling rate from the maximum temperature to 800 ° C is 20 to 4
A method for producing a multilayer capacitor, wherein the temperature is set to 0 ° C./hr .
JP34225195A 1995-12-28 1995-12-28 Manufacturing method of multilayer capacitor Expired - Fee Related JP3245342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34225195A JP3245342B2 (en) 1995-12-28 1995-12-28 Manufacturing method of multilayer capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34225195A JP3245342B2 (en) 1995-12-28 1995-12-28 Manufacturing method of multilayer capacitor

Publications (2)

Publication Number Publication Date
JPH09186045A JPH09186045A (en) 1997-07-15
JP3245342B2 true JP3245342B2 (en) 2002-01-15

Family

ID=18352280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34225195A Expired - Fee Related JP3245342B2 (en) 1995-12-28 1995-12-28 Manufacturing method of multilayer capacitor

Country Status (1)

Country Link
JP (1) JP3245342B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269066A (en) * 1999-03-19 2000-09-29 Taiyo Yuden Co Ltd Multilayer ceramic capacitor
JP4200792B2 (en) 2003-03-12 2008-12-24 株式会社村田製作所 Multilayer ceramic capacitor

Also Published As

Publication number Publication date
JPH09186045A (en) 1997-07-15

Similar Documents

Publication Publication Date Title
JP3039397B2 (en) Dielectric ceramic composition and multilayer ceramic capacitor using the same
JP4920520B2 (en) Dielectric porcelain, manufacturing method thereof, and multilayer ceramic capacitor using the same
JP2001006966A (en) Ceramic capacitor and its manufacture
JP2002080275A (en) Dielectric ceramic and electronic component
KR100562433B1 (en) Nonreducing dielectric ceramic, its production method, and multilayer ceramic capacitor
JP2007258661A (en) Laminated ceramic capacitor and its manufacturing method
JP5343974B2 (en) Dielectric ceramic composition and multilayer ceramic capacitor
JP4587924B2 (en) Multilayer ceramic capacitor
JP2008254988A (en) Dielectric ceramics and method for producing the same, and monolithic ceramic capacitor
JP5251913B2 (en) Dielectric ceramic composition and multilayer ceramic capacitor
JP2004323315A (en) Dielectric ceramic composition, its production method, and multilayer ceramic capacitor obtained by using the same
JP5733313B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
JPH11302072A (en) Dielectric ceramic, laminated ceramic capacitor and its production
JP2010208905A (en) Method for manufacturing dielectric ceramic, dielectric ceramic, method for manufacturing laminated ceramic capacitor and the laminated ceramic capacitor
JP5229685B2 (en) Dielectric ceramic and multilayer ceramic capacitor
JP4349007B2 (en) Multilayer electronic components
JP3363322B2 (en) Multilayer capacitors
JP2009096671A (en) Dielectric ceramic and multi-layer ceramic capacitor
JP4729847B2 (en) Non-reducing dielectric ceramic and multilayer ceramic capacitors
JP2008081351A (en) Dielectric ceramic, multilayer ceramic capacitor, and method for manufacturing the same
JP3245342B2 (en) Manufacturing method of multilayer capacitor
JP3856984B2 (en) Dielectric porcelain and manufacturing method thereof
JP3146966B2 (en) Non-reducing dielectric ceramic and multilayer ceramic electronic component using the same
JPH11302071A (en) Dielectric ceramic, laminated ceramic capacitor and its production
JP2004210613A (en) Dielectric ceramic, its producing method and laminated ceramic capacitor

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071026

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081026

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091026

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101026

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101026

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111026

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees