JP3242459B2 - Manufacturing method of ceramic wiring board - Google Patents

Manufacturing method of ceramic wiring board

Info

Publication number
JP3242459B2
JP3242459B2 JP22178092A JP22178092A JP3242459B2 JP 3242459 B2 JP3242459 B2 JP 3242459B2 JP 22178092 A JP22178092 A JP 22178092A JP 22178092 A JP22178092 A JP 22178092A JP 3242459 B2 JP3242459 B2 JP 3242459B2
Authority
JP
Japan
Prior art keywords
particles
layer
ceramic
wiring board
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22178092A
Other languages
Japanese (ja)
Other versions
JPH0664989A (en
Inventor
一信 盛岡
笠井与志治
悟 小川
雅也 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP22178092A priority Critical patent/JP3242459B2/en
Publication of JPH0664989A publication Critical patent/JPH0664989A/en
Application granted granted Critical
Publication of JP3242459B2 publication Critical patent/JP3242459B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/52Multiple coating or impregnating multiple coating or impregnating with the same composition or with compositions only differing in the concentration of the constituents, is classified as single coating or impregnation
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2111/00Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
    • C04B2111/00474Uses not provided for elsewhere in C04B2111/00
    • C04B2111/00844Uses not provided for elsewhere in C04B2111/00 for electronic applications
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2111/00Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
    • C04B2111/90Electrical properties
    • C04B2111/94Electrically conducting materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、セラミック配線板の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ceramic wiring board.

【0002】[0002]

【従来の技術】電子材料分野、特にハイブリッドIC分
野で使われるセラミック配線板では、従来、セラミック
基板の表面に導電性ペースト(銅ペースト等)をスクリ
ーン印刷・焼き付けすることで所定パターンの回路を形
成し、その後、厚膜の抵抗体層を焼き付け形成すること
が行われている。ただ、この方法の場合、回路の微細化
が図り難かったり、導電性ペーストがガラス質を含むた
めハンダ付着性が劣り、不良品が出やすく、使用中の故
障も多いという問題があった。
2. Description of the Related Art In a ceramic wiring board used in the field of electronic materials, particularly in the field of hybrid ICs, a circuit of a predetermined pattern is conventionally formed by screen printing and baking a conductive paste (copper paste, etc.) on the surface of a ceramic substrate. Thereafter, a thick resistor layer is formed by baking. However, this method has problems that it is difficult to miniaturize the circuit and that the conductive paste contains vitreous material, so that solder adhesion is poor, defective products are easily generated, and there are many failures during use.

【0003】そこで、回路形成に導電性ペーストを使わ
ずにセラミック基板の表面に無電解メッキで導体被膜を
形成し、選択エッチングを施すことにより、所定パター
ンの回路用導体層を表面に設けたセラミック基板を得て
から、厚膜の抵抗体層を焼き付け形成することが考えら
れる。この場合、導体層が基本的に金属であることから
回路の抵抗値が低く、しかも、フォトリソグラフィ技術
を利用した微細パターン化技術の適用で回路の微細化も
図れる。
Therefore, a conductive film is formed by electroless plating on the surface of a ceramic substrate without using a conductive paste to form a circuit, and selective etching is performed to provide a ceramic conductive layer having a predetermined pattern of a circuit conductive layer on the surface. After obtaining the substrate, a thick resistor layer may be formed by baking. In this case, since the conductor layer is basically made of metal, the resistance of the circuit is low, and the circuit can be miniaturized by applying a fine patterning technique using a photolithography technique.

【0004】ただ、この場合、次の問題がある。抵抗体
層を形成した後、導体層の表面に金属被膜をメッキ法で
形成することがある。例えば、導体層が銅である場合、
チップダイボンド性あるいはワイヤーボンド性を付与す
るために、導体層に金メッキを行う。その後、チップダ
イボンドやワイヤーボンドを行うと、導体層がセラミッ
ク基板の表面から剥がれフクレが発生し、回路損傷とい
う事態を招くのである。
However, in this case, there is the following problem. After forming the resistor layer, a metal film may be formed on the surface of the conductor layer by a plating method. For example, if the conductor layer is copper,
Gold plating is performed on the conductor layer in order to impart chip die bondability or wire bondability. Thereafter, when chip die bonding or wire bonding is performed, the conductor layer is peeled off from the surface of the ceramic substrate, causing blisters, thereby causing a circuit damage.

【0005】[0005]

【発明が解決しようとする課題】この発明は、上記事情
に鑑み、セラミック基板の表面の導体層に抵抗体層の形
成後に金属被膜をメッキ法で形成することで得るプリン
ト配線板を、その後の高温処理で導体層のフクレが生じ
難いように製造することのできる方法を提供することを
課題とする。
SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a printed wiring board obtained by forming a metal film by plating after forming a resistor layer on a conductor layer on the surface of a ceramic substrate. It is an object of the present invention to provide a method which can be manufactured so that blisters of a conductor layer are hardly generated by high-temperature treatment.

【0006】[0006]

【課題を解決するための手段】前記課題を解決するた
め、この発明にかかるプリント配線板の製造方法では、
導体層が表面に設けられているセラミック基板に抵抗体
層を焼き付け形成してから、前記導体層の表面にメッキ
法により金属被膜を形成するにあたり、前記セラミック
基板として、メッキ法で形成された導体層であって、
ラミック粒子または金属粒子のうちの少なくとも一つが
分散されている導体層が設けられたセラミック基板を用
いるようにしている。
In order to solve the above problems, a method for manufacturing a printed wiring board according to the present invention comprises:
After baking and forming a resistor layer on a ceramic substrate provided with a conductor layer on the surface, and then forming a metal film on the surface of the conductor layer by a plating method, a conductor formed by a plating method as the ceramic substrate is used. a layer, a conductor layer at least one of the ceramic particles or metal particles are dispersed is to use a ceramic substrate provided.

【0007】以下、この発明をより具体的に説明する。
この発明で用いるセラミック基板自体は、焼結セラミッ
クタイプのものが適当であり、材質としては、アルミ
ナ、フォルステナイト、ジルコニア、ムライト、コージ
ェライト、チタニア、チタン酸バリウム、チタン酸カル
シウムなどの酸化物系のセラミックが主に使用される
が、炭化ケイ素などの炭化物系のセラミック、窒化アル
ミニウムなどの窒化物系のセラミックが使用されてもよ
く、複数種のセラミックが併用されてもよい。
Hereinafter, the present invention will be described more specifically.
The ceramic substrate itself used in the present invention is suitably of a sintered ceramic type, and the material is an oxide based material such as alumina, forstenite, zirconia, mullite, cordierite, titania, barium titanate, and calcium titanate. Are mainly used, but carbide-based ceramics such as silicon carbide, nitride-based ceramics such as aluminum nitride may be used, or a plurality of types of ceramics may be used in combination.

【0008】セラミック基板は表面の導体層の密着力が
高まるように、予め粗面化処理が施されていることが好
ましい。粗面化処理としては、サンドブラスト等を用い
る機械的な粗面化処理や、熱リン酸等の処理剤を用いる
化学的な粗面化処理がある。この発明では、粗面化処理
したあとセラミック粒子や金属粒子を含む導電被膜をセ
ラミック基板の表面に形成するのであるが、この場合の
メタライズ方法は特定の方法に限定されない。ただ、メ
ッキ浴中にセラミック粒子や金属粒子を添加することで
粒子を導電被膜中に分散させられる無電解メッキや電解
メッキが利用し易い。電解メッキの場合は下地金属層を
予め形成する必要がある。
The ceramic substrate is preferably preliminarily subjected to a surface roughening treatment so as to increase the adhesion of the conductor layer on the surface. Examples of the surface roughening include mechanical surface roughening using sandblasting or the like and chemical surface roughening using a processing agent such as hot phosphoric acid. In the present invention, a conductive film containing ceramic particles and metal particles is formed on the surface of the ceramic substrate after the surface roughening treatment, but the metallization method in this case is not limited to a specific method. However, electroless plating or electrolytic plating in which ceramic particles or metal particles are added to a plating bath to disperse the particles in a conductive film is easy to use. In the case of electrolytic plating, it is necessary to form a base metal layer in advance.

【0009】導電被膜の主材たる金属の種類には、銅や
ニッケルなどが挙げられる。一方、導電被膜中に分散さ
せるセラミック粒子や金属粒子としては、加熱時におけ
る回路用の導体層での結晶成長を抑制させる機能を有す
る粒子であり、特定の粒子に限らないが、平均粒径が3
0μm以下の粒子が好ましく、例えば、アルミナ粒子な
どのセラミック粒子やニッケル粒子などの金属粒子が例
示される。導電被膜におけるセラミック粒子や金属粒子
の含有量は、普通、40%以下の範囲、後述の実施例に
もみるように、約10〜30%程度である。40%を越
すと、被膜接着性や導電性の低下が大きくなるなどの傾
向があるからである。
[0009] Examples of the kind of metal which is a main material of the conductive film include copper and nickel. On the other hand, ceramic particles and metal particles dispersed in the conductive film are particles having a function of suppressing crystal growth in a conductor layer for a circuit during heating, and are not limited to specific particles, but have an average particle size. 3
Particles having a particle size of 0 μm or less are preferable, and examples thereof include ceramic particles such as alumina particles and metal particles such as nickel particles. The content of the ceramic particles and the metal particles in the conductive coating is usually in the range of 40% or less, and about 10 to 30% as seen in Examples described later. If it exceeds 40%, there is a tendency that the film adhesion and the conductivity are greatly reduced.

【0010】セラミック粒子や金属粒子を含む導電被膜
の厚みは、特定の厚みに限らないが、2μm以上である
ことが好ましい。セラミック粒子や金属粒子は導電被膜
全体に分散している必要はない。例えば、セラミック基
板の表面から一定の高さまでの部分(下層)は粒子が分
散しており、その上の部分(上層)は粒子が分散してお
らず純金属層である複数層構造の導電被膜であってもよ
い。やはり、粒子分散部分の形成は粒子未分散部分の形
成に比べて面倒なので必要域だけ粒子分散部分とする方
が製造し易い。
[0010] The thickness of the conductive coating containing ceramic particles and metal particles is not limited to a specific thickness, but is preferably 2 µm or more. The ceramic particles and metal particles need not be dispersed throughout the conductive coating. For example, a portion (lower layer) from the surface of the ceramic substrate to a certain height has particles dispersed therein, and a portion above the upper portion (upper layer) has no particles dispersed therein and is a conductive film having a multilayer structure of a pure metal layer. It may be. After all, the formation of the particle-dispersed portion is more troublesome than the formation of the non-dispersed portion of the particle, so that it is easier to produce the particle-dispersed portion only in the required area.

【0011】このようにして形成された導電被膜をフォ
トリソグラフィ技術等を利用して選択エッチング処理す
ることによりパターン化し回路用の導電層をセラミック
基板の表面に設けるようにする。この回路用の導体層の
形成方法は、いわゆるサブトラクティブ法と呼ばれる
が、この発明の場合、導体層は、サブトラクティブ法に
より設けられたものに限らず、いわゆるアディティブ法
やセミアディティブ法など他の方法により設けられたも
のであってもよい。
The conductive film thus formed is patterned by selective etching using a photolithography technique or the like, and a conductive layer for a circuit is provided on the surface of the ceramic substrate. This method of forming a conductor layer for a circuit is called a subtractive method, but in the case of the present invention, the conductor layer is not limited to that provided by the subtractive method, and may be formed by another method such as a so-called additive method or a semi-additive method. It may be provided by a method.

【0012】このようにして、回路用の導体層を設けた
後、抵抗体層を形成する。抵抗体層は、抵抗体用ペース
トを塗布・焼き付けすることで形成できる。焼き付け
後、必要に応じてトリミングを行い抵抗値調整してもよ
い。抵抗体用ペーストとしては、窒素雰囲気中の焼成で
焼き付けを行うLaB6 系、SnO2 系等のペースト、
あるいは、空気中の焼成で焼き付けを行うRuO2 系等
のペーストが主として使用されるが、特に限定するもの
ではない。前者のペーストは特に問題ないが、後者の空
気中の焼成のRuO2 系等のペーストを使用するとき
は、導電層が銅などの酸化される金属である場合には、
還元性雰囲気(例えば、水素と窒素の混合雰囲気)下に
て、酸化した銅を還元させる必要がある。これらのペー
ストは、焼成温度が、普通、800〜950℃程度であ
る。
After the circuit conductor layer is thus provided, the resistor layer is formed. The resistor layer can be formed by applying and baking a resistor paste. After baking, trimming may be performed as necessary to adjust the resistance value. Examples of the resistor paste include pastes of LaB 6 type, SnO 2 type, etc., which are baked by firing in a nitrogen atmosphere.
Alternatively, a paste such as a RuO 2 paste that is baked by baking in air is mainly used, but is not particularly limited. The former paste is not particularly problematic, but when using the latter paste such as RuO 2 based firing in air, when the conductive layer is a metal to be oxidized such as copper,
It is necessary to reduce oxidized copper in a reducing atmosphere (for example, a mixed atmosphere of hydrogen and nitrogen). These pastes usually have a firing temperature of about 800 to 950 ° C.

【0013】抵抗体層の形成に続いて、導体層の上にメ
ッキ法により金属被膜を形成する。金属被膜の種類も、
特定の金属に限らないが、例えば、ニッケル、金などが
挙げられる。金属被膜が種類の異なる複数の金属層から
なる複合被膜の場合もある。金属被膜形成用のメッキ法
におけるメッキ浴種、めっき方法、操作条件等について
は特に限定しない。
After the formation of the resistor layer, a metal film is formed on the conductor layer by plating. The type of metal coating,
Although not limited to a specific metal, for example, nickel, gold and the like can be mentioned. The metal coating may be a composite coating comprising a plurality of different types of metal layers. The type of plating bath, plating method, operating conditions, and the like in the plating method for forming a metal film are not particularly limited.

【0014】[0014]

【作用】この発明のセラミック配線板の製造方法では、
抵抗体層の形成後にセラミック基板の表面の導体層に金
属被膜をメッキ法で形成することでプリント配線板を得
るのであるが、導体層にセラミック粒子や金属粒子が分
散されているため、その後の高温処理で導体層のフクレ
が生じ難くなっている。
According to the method for manufacturing a ceramic wiring board of the present invention,
After forming the resistor layer, a printed wiring board is obtained by forming a metal coating on the conductor layer on the surface of the ceramic substrate by plating, but since the ceramic particles and metal particles are dispersed in the conductor layer, the subsequent Swelling of the conductor layer is hardly caused by the high-temperature treatment.

【0015】抵抗体層形成用の焼成の際、セラミック粒
子や金属粒子で導体層の結晶成長の速度が抑えられるた
め、結晶粒径が余り変わらず、結晶粒界が多く存在す
る。こに対し、粒子の分散のない場合は結晶成長が進み
結晶粒径が大きくなり、結晶粒界は少なくなる。一方、
その後、導体層の上にメッキ法で金属被膜を形成する際
に導体層の表面付近にメッキ液等が吸蔵されており、吸
蔵されているメッキ液等がガス化し結晶粒界に侵入する
が、この発明のプリント配線板の場合、結晶粒界が多く
存在し侵入するガスが四方八方に分散してうまく吸収さ
れるため、導体層とセラミック基板の界面にはガスが達
せず、フクレが生じ難い。これに対し、従来の場合、結
晶粒界が少ないため、ガスは余り分散せず吸収されずに
導体層とセラミック基板の界面に達してしまい、フクレ
が生じ易かったのである。
In the firing for forming the resistor layer, the crystal growth rate of the conductor layer is suppressed by ceramic particles and metal particles, so that the crystal grain size does not change much and many crystal grain boundaries exist. On the other hand, when the particles are not dispersed, the crystal growth proceeds and the crystal grain size increases, and the crystal grain boundaries decrease. on the other hand,
Thereafter, when a metal film is formed on the conductor layer by a plating method, a plating solution or the like is occluded near the surface of the conductor layer, and the occluded plating solution or the like gasifies and penetrates into crystal grain boundaries. In the case of the printed wiring board of the present invention, a large number of crystal grain boundaries are present, and the invading gas is dispersed and dispersed well in all directions, so that the gas does not reach the interface between the conductor layer and the ceramic substrate, and blisters are unlikely to occur . On the other hand, in the conventional case, since the crystal grain boundaries are small, the gas does not diffuse much and is not absorbed, but reaches the interface between the conductor layer and the ceramic substrate, so that blisters are easily generated.

【0016】したがって、この発明の場合、製造したプ
リント配線板において、チップダイボンド時やワイヤボ
ンディング時の加熱でフクレが発生するということが回
避できることになる。
Therefore, in the case of the present invention, it is possible to avoid occurrence of blisters in the manufactured printed wiring board due to heating during chip die bonding or wire bonding.

【0017】[0017]

【実施例】以下、この発明の実施例を説明する。勿論、
この発明は、下記の実施例に限らないことは言うまでも
ない。図1は、実施例1,2で得られるプリント配線板
の要部構成をあらわし、図2は、実施例3で得られるプ
リント配線板の要部構成をあらわす。
Embodiments of the present invention will be described below. Of course,
It goes without saying that the present invention is not limited to the following embodiments. FIG. 1 shows a configuration of a main part of the printed wiring board obtained in the first and second embodiments, and FIG. 2 shows a main configuration of the printed wiring board obtained in the third embodiment.

【0018】−実施例1− セラミック基板として、平均粒径1μmのアルミナ粒子
が20%の含有率で分散している厚み6μmの無電銅解
メッキ銅被膜(導電被膜)が形成されているアルミナ基
板1を用いた。このアルミナ基板1の銅被膜に対して選
択エッチング処理を施すことにより、所望のパターン化
を行い、回路用の銅導電層2を形成した。
Example 1 As a ceramic substrate, an alumina substrate having a 6 μm-thick electroless copper-plated copper coating (conductive coating) in which alumina particles having an average particle size of 1 μm are dispersed at a content of 20% was formed. 1 was used. By subjecting the copper film of the alumina substrate 1 to a selective etching process, a desired pattern was formed, and a copper conductive layer 2 for a circuit was formed.

【0019】続いて、LaB6 系の抵抗体ペーストを所
定の位置に印刷し、窒素雰囲気下、900℃にて焼成し
焼き付けて抵抗体層3を形成した後、回路用の銅導電層
2の表面にメッキ法で厚み5μmのニッケル層4aの上
に厚み1μmの金層4bからなる金属被膜4を形成し、
セラミック配線板を得た。このようにして得たセラミッ
ク配線板の耐熱性を500℃、10分間の加熱処理によ
って評価した結果、被膜表面にフクレ等の異常は観察さ
れなかった。
Subsequently, a LaB 6 -based resistor paste is printed at a predetermined position, baked and baked at 900 ° C. in a nitrogen atmosphere to form a resistor layer 3, and then a copper conductive layer 2 for a circuit is formed. Forming a metal coating 4 consisting of a 1 μm thick gold layer 4 b on a 5 μm thick nickel layer 4 a by plating on the surface,
A ceramic wiring board was obtained. The heat resistance of the ceramic wiring board thus obtained was evaluated by a heat treatment at 500 ° C. for 10 minutes. As a result, no abnormality such as blisters was observed on the surface of the coating.

【0020】−実施例2− セラミック基板として、平均粒径1μmのニッケル粒子
が15%の含有率で分散している厚み6μm無電銅解メ
ッキ銅被膜(導電被膜)が形成されているアルミナ基板
1を用いた。図1にみるように、このアルミナ基板の銅
被膜に対して選択エッチング処理を施すことにより、所
望のパターン化を行い、回路用の銅導電層2を形成し
た。
Example 2 As a ceramic substrate, an alumina substrate 1 having a 6 μm-thick electroless copper-plated copper coating (conductive coating) in which nickel particles having an average particle size of 1 μm are dispersed at a content of 15%. Was used. As shown in FIG. 1, by subjecting the copper film on the alumina substrate to a selective etching process, a desired patterning was performed, and a copper conductive layer 2 for a circuit was formed.

【0021】続いて、LaB6 系の抵抗体ペーストを所
定の位置に印刷し、窒素雰囲気下、900℃にて焼成し
焼き付けて抵抗体層3を形成した後、回路用の銅導電層
2の表面にメッキ法で厚み5μmのニッケル層4aの上
に厚み1μmの金層4bからなる金属被膜4を形成し、
セラミック配線板を得た。このようにして得たセラミッ
ク配線板の耐熱性を500℃、10分間の加熱処理によ
って評価した結果、被膜表面にフクレ等の異常は観察さ
れなかった。
Subsequently, a LaB 6 -based resistor paste is printed at a predetermined position, baked and baked at 900 ° C. in a nitrogen atmosphere to form a resistor layer 3, and then a copper conductive layer 2 for a circuit is formed. Forming a metal coating 4 consisting of a 1 μm thick gold layer 4 b on a 5 μm thick nickel layer 4 a by plating on the surface,
A ceramic wiring board was obtained. The heat resistance of the ceramic wiring board thus obtained was evaluated by a heat treatment at 500 ° C. for 10 minutes. As a result, no abnormality such as blisters was observed on the surface of the coating.

【0022】−実施例3− セラミック基板として、平均粒径1μmのアルミナ粒子
が20%の含有率で分散している厚み3μmの無電銅解
メッキ銅被膜(下導電被膜)の上に粒子が分散していな
い厚み3μmの無電銅解メッキ銅被膜(純銅被膜、上導
電被膜)が積層されてなる導電被膜が表面に形成されて
いるアルミナ基板1を用いており、導電層2が、アルミ
ナ粒子が20%の含有の銅導電層2aとアルミナ粒子未
含有の銅導電層2bの積層構成となる他は、実施例1と
同様にしてセラミック配線板を得た。
Example 3 As a ceramic substrate, particles were dispersed on a 3 μm-thick electroless copper-plated copper coating (lower conductive coating) in which alumina particles having an average particle size of 1 μm were dispersed at a content of 20%. An alumina substrate 1 having a conductive film formed by laminating a 3 μm-thick electroless copper electroplated copper film (pure copper film, upper conductive film) is used. The conductive layer 2 is made of alumina particles. A ceramic wiring board was obtained in the same manner as in Example 1, except that a copper conductive layer 2a containing 20% and a copper conductive layer 2b containing no alumina particles were laminated.

【0023】このようにして得たセラミック配線板の耐
熱性を500℃、10分間の加熱処理によって評価した
結果、被膜表面にフクレ等の異常は観察されなかった。 −比較例1− セラミック基板として、アルミナ粒子が分散していない
無電銅解メッキ銅被膜(純銅被膜、膜厚み;6μm)が
形成されているアルミナ基板を用いた他は、実施例1と
同様にして、セラミック配線板を得た。
The heat resistance of the ceramic wiring board thus obtained was evaluated by heat treatment at 500 ° C. for 10 minutes. As a result, no abnormality such as blisters was observed on the surface of the coating. Comparative Example 1 The same procedure as in Example 1 was carried out except that an alumina substrate having an electroless copper-deplated copper film (pure copper film, film thickness: 6 μm) in which alumina particles were not dispersed was used as a ceramic substrate. Thus, a ceramic wiring board was obtained.

【0024】このようにして得たセラミック配線板の耐
熱性を500℃、10分間の加熱処理によって評価した
結果、被膜表面にフクレが生じている箇所のあることが
観察された。実施例と比較例の観察結果から、この発明
の場合、セラミック粒子や金属粒子の導電層への分散に
より、フクレの発生が防げるようになったことがよく分
かる。
The heat resistance of the ceramic wiring board thus obtained was evaluated by heat treatment at 500 ° C. for 10 minutes. As a result, it was observed that blisters occurred on the surface of the coating. From the observation results of the examples and the comparative examples, it is clearly understood that in the case of the present invention, the occurrence of blisters can be prevented by dispersing the ceramic particles and metal particles in the conductive layer.

【0025】[0025]

【発明の効果】この発明では、抵抗体層の形成後にセラ
ミック基板の表面の導体層に金属被膜をメッキ法で形成
することでプリント配線板を得るのであるが、得られた
プリント配線板は、導体層にセラミック粒子や金属粒子
が分散されていて、抵抗体層形成用の焼成では、結晶粒
径が余り変わらず、結晶粒界が多く存在するため、金属
被膜のメッキ形成後の高温処理において、吸蔵されてい
るメッキ液等が四方八方に分散してうまく吸収されて導
体層とセラミック基板の界面には達せず、フクレが生じ
難く、非常に有用である。
According to the present invention, a printed wiring board is obtained by forming a metal coating on the conductor layer on the surface of the ceramic substrate by plating after the formation of the resistor layer. Ceramic particles and metal particles are dispersed in the conductor layer, and in firing for forming the resistor layer, the crystal grain size does not change much and there are many crystal grain boundaries, so in high temperature treatment after plating formation of the metal film, The absorbed plating solution or the like is dispersed in all directions and is well absorbed, does not reach the interface between the conductor layer and the ceramic substrate, and is less likely to cause blisters, which is very useful.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例1,2で得られたプリント配線板の要部
構成をあらわす断面図である。
FIG. 1 is a cross-sectional view illustrating a main configuration of a printed wiring board obtained in Examples 1 and 2.

【図2】実施例3で得られたプリント配線板の要部構成
をあらわす断面図である。
FIG. 2 is a cross-sectional view illustrating a configuration of a main part of a printed wiring board obtained in Example 3.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 銅導電層(導電層) 3 抵抗体層 4 金属被膜 REFERENCE SIGNS LIST 1 ceramic substrate 2 copper conductive layer (conductive layer) 3 resistor layer 4 metal coating

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小山 雅也 大阪府門真市大字門真1048番地松下電工 株式会社内 (56)参考文献 特開 平1−313803(JP,A) 特開 昭58−71507(JP,A) (58)調査した分野(Int.Cl.7,DB名) C04B 41/80 - 41/91 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Masaya Koyama 1048 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Works, Ltd. (56) References JP-A-1-313803 (JP, A) JP-A-58-71507 ( JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) C04B 41/80-41/91

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 導体層が表面に設けられているセラミッ
ク基板に抵抗体層を焼き付け形成してから、前記導体層
の表面にメッキ法により金属被膜を形成するセラミック
配線板の製造方法において、前記セラミック基板とし
て、メッキ法で形成された導体層であって、セラミック
粒子または金属粒子のうちの少なくとも一つが分散され
ている導体層が設けられたセラミック基板を用いること
を特徴とするセラミック配線板の製造方法。
1. A method for manufacturing a ceramic wiring board, comprising: forming a resistor layer on a ceramic substrate having a conductor layer provided on a surface thereof by baking; and forming a metal coating on a surface of the conductor layer by plating. As the ceramic substrate, a conductive layer formed by a plating method, wherein a ceramic substrate provided with a conductive layer in which at least one of ceramic particles or metal particles is dispersed is used. Production method.
JP22178092A 1992-08-20 1992-08-20 Manufacturing method of ceramic wiring board Expired - Fee Related JP3242459B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22178092A JP3242459B2 (en) 1992-08-20 1992-08-20 Manufacturing method of ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22178092A JP3242459B2 (en) 1992-08-20 1992-08-20 Manufacturing method of ceramic wiring board

Publications (2)

Publication Number Publication Date
JPH0664989A JPH0664989A (en) 1994-03-08
JP3242459B2 true JP3242459B2 (en) 2001-12-25

Family

ID=16772091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22178092A Expired - Fee Related JP3242459B2 (en) 1992-08-20 1992-08-20 Manufacturing method of ceramic wiring board

Country Status (1)

Country Link
JP (1) JP3242459B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013087347A (en) * 2011-10-20 2013-05-13 Ngk Insulators Ltd Noble metal coating and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013087347A (en) * 2011-10-20 2013-05-13 Ngk Insulators Ltd Noble metal coating and method for manufacturing the same

Also Published As

Publication number Publication date
JPH0664989A (en) 1994-03-08

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