JP3239445B2 - Dielectric element, method of manufacturing the same, and semiconductor memory device - Google Patents
Dielectric element, method of manufacturing the same, and semiconductor memory deviceInfo
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- JP3239445B2 JP3239445B2 JP14952192A JP14952192A JP3239445B2 JP 3239445 B2 JP3239445 B2 JP 3239445B2 JP 14952192 A JP14952192 A JP 14952192A JP 14952192 A JP14952192 A JP 14952192A JP 3239445 B2 JP3239445 B2 JP 3239445B2
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- oxygen
- dielectric
- dielectric element
- lower electrode
- metal oxide
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Description
【０００１】[0001]
【産業上の利用分野】本発明は金属酸化物誘電体を基質
とする薄膜を用いた誘電体素子あるいは誘電体素子の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric element using a thin film having a metal oxide dielectric as a substrate and a method of manufacturing the dielectric element.
【０００２】[0002]
【従来の技術】金属酸化物誘電体を基質とする薄膜に一
個、もしくは複数個の電極を接触させた構造を有する誘
電体素子において、小面積の大容量誘電素子、あるいは
強誘電性容量素子を得るために、従来は例えばジャーナ
ル・オブ・アプライド・フィジックス（Ｊ．Ａｐｐｌ．
Ｐｈｙｓ）、１９９１年、第７０巻、第１号、３８２頁
〜３８８頁に記載されていたように、電極材料として白
金（Pt）、誘電体材料としてはペロブスカイト型の結晶
構造をもつ強誘電体であるＰＺＴ（Pb(ZrxTi1-x)O3）を
用いていた。2. Description of the Related Art In a dielectric element having a structure in which one or a plurality of electrodes are brought into contact with a thin film made of a metal oxide dielectric as a substrate, a small-area large-capacitance element or a ferroelectric capacitance element is used. In order to obtain it, it is conventionally possible to use, for example, the Journal of Applied Physics (J. Appl.
Phys., 1991, Vol. 70, No. 1, pp. 382-388, as an electrode material, platinum (Pt), and as a dielectric material, a ferroelectric material having a perovskite crystal structure. PZT (Pb (Zr x Ti 1-x ) O 3 ) was used.
【０００３】図３にシリコン基板上に強誘電体と二つの
電極を積層した構造の、誘電体素子の一例を示す。図３
において、３０１はシリコン基板であり、３０２は二酸
化シリコン（SiO2）の絶縁層である。３０４がＰＺＴを
用いた強誘電体膜であり、白金を用いた下部電極３０３
と上部電極３０５により挟まれ、容量素子を構成してい
る。３０６は素子保護膜である。FIG. 3 shows an example of a dielectric element having a structure in which a ferroelectric substance and two electrodes are stacked on a silicon substrate. FIG.
In the figure, 301 is a silicon substrate, and 302 is an insulating layer of silicon dioxide (SiO 2 ). Reference numeral 304 denotes a ferroelectric film using PZT, and a lower electrode 303 using platinum.
And an upper electrode 305 to form a capacitive element. 306 is an element protection film.
【０００４】[0004]
【発明が解決しようとする課題】このように下部電極３
０３、強誘電体膜３０４、上部電極３０５を積層した構
造においては、強誘電体膜３０４の膜形成条件によっ
て、また、分極を反転させる印加電圧のサイクルを繰り
返したり、弾性限界内で繰り返し力を加えた場合、強誘
電体膜３０４の電極近傍においては、酸素空乏が生じて
強誘電性を示さなくなったり、絶縁不良を起こしてリー
ク電流が増大する。As described above, the lower electrode 3
03, in the structure in which the ferroelectric film 304 and the upper electrode 305 are laminated, depending on the film forming conditions of the ferroelectric film 304, the cycle of the applied voltage for inverting the polarization is repeated, or the repetitive force is within the elastic limit. In this case, oxygen depletion occurs in the vicinity of the electrode of the ferroelectric film 304 so that ferroelectricity is no longer exhibited, or insulation failure occurs, and leakage current increases.
【０００５】本発明は、このような課題を解決するもの
で、その目的とするところは、金属酸化物誘電体の、電
極近傍での酸素空乏を防ぎ、膜疲労現象やリーク電流の
少ない誘電体素子を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent a metal oxide dielectric from being depleted of oxygen in the vicinity of an electrode and to reduce a film fatigue phenomenon and a leak current. It is to provide an element.
【０００６】[0006]
【課題を解決するための手段】本発明の誘電体素子は、 （１）下部電極と、該下部電極上に形成された金属酸化
物誘電体薄膜と、該金属酸化物誘電体薄膜上に形成され
た上部電極を有する誘電体素子において、前記下部電極
が金属からなり、前記金属酸化物誘電体薄膜に接する側
の界面で、前記下部電極の他の部分よりも多くの酸素が
含まれていて、前記上部電極が金属からなり、前記金属
酸化物誘電体薄膜に接する側の界面で酸素が含まれてい
ることを特徴とする。 （２） 前記金属酸化物誘電体がペロブスカイト型の結
晶構造を有することを特徴とする。 （３） 前記電極が、白金族元素、及び金のうち１もし
くは２種類以上を主成分とすることを特徴とする。 （４） 前記金属酸化物誘電体は、ＰＺＴ（Ｐｂ(Ｚｒx
Ｔｉ1-x)Ｏ3）およびＰＬＺＴ（(Ｐｂ0.9Ｌａ0.1)(Ｔｉ
0.6Ｚｒ0.4)Ｏ3）のいずれか一方であることを特徴とす
る。また、本発明の半導体記憶装置は、 （５） 上述のいずれかに記載の誘電体素子を用いてな
ることを特徴とする。また、本発明の誘電体素子の製造
方法は、 （６）金属酸化物誘電体薄膜が上部電極および下部電極
の一対の電極に挟まれた構造を有する誘電体素子の製造
方法において、前記下部電極を形成する工程と、前記下
部電極の表面の少なくとも一部に酸素を含む領域を形成
する工程と、前記酸素を含む領域上に金属酸化物誘電体
薄膜を形成する工程と、前記金属酸化物誘電体薄膜上に
前記上部電極を形成する工程と、前記上部電極に酸素を
注入する工程とを少なくとも含むことを特徴とする。 （７）前記下部電極の表面の少なくとも一部に酸素を含
む領域を形成する工程が、特に前記電極のうち少なくと
も一つの電極に酸素イオンを打ち込む工程を含むことを
特徴とする。 （８）前記下部電極の表面の少なくとも一部に酸素を含
む領域を形成する工程が、特に前記電極のうち少なくと
も一個の電極を酸素プラズマもしくはオゾンプラズマ中
にさらす工程を含むことを特徴とする。The dielectric element of the present invention comprises: (1) a lower electrode and a metal oxide formed on the lower electrode.
Dielectric thin film, and formed on the metal oxide dielectric thin film
A dielectric element having an upper electrode, wherein the lower electrode
Is made of metal and is in contact with the metal oxide dielectric thin film.
At the interface, more oxygen than the rest of the lower electrode
Wherein the upper electrode comprises a metal,
Oxygen is contained at the interface in contact with the oxide dielectric thin film.
It is characterized by that. (2) The metal oxide dielectric has a perovskite crystal structure. (3) The electrode is characterized in that one or more of a platinum group element and gold are the main components. (4) The metal oxide dielectric is PZT (Pb (Zr x
Ti 1-x ) O 3 ) and PLZT ((Pb 0.9 La 0.1 ) (Ti
0.6 Zr 0.4 ) O 3 ). According to a fifth aspect of the present invention, there is provided a semiconductor memory device including the dielectric element described above. (6) The method for manufacturing a dielectric element according to the present invention, wherein: (6) the method for manufacturing a dielectric element having a structure in which a metal oxide dielectric thin film is sandwiched between a pair of an upper electrode and a lower electrode; Forming a region containing oxygen on at least a part of the surface of the lower electrode; forming a metal oxide dielectric thin film on the region containing oxygen; Forming the upper electrode on a body thin film; and supplying oxygen to the upper electrode.
And injecting . (7) The step of forming a region containing oxygen on at least a part of the surface of the lower electrode includes a step of implanting oxygen ions into at least one of the electrodes. (8) The step of forming a region containing oxygen on at least a part of the surface of the lower electrode includes a step of exposing at least one of the electrodes to oxygen plasma or ozone plasma.
【０００７】[0007]
【０００８】[0008]
【実施例】図１は本発明の誘電体素子の一実施例（以
下、第１の実施例とする）を示す主要断面図である。図
２は本発明の誘電体素子の製造方法の一実施例（以下、
第２の実施例とする）を示す主要工程断面図である。FIG. 1 is a main sectional view showing one embodiment (hereinafter referred to as a first embodiment) of a dielectric element of the present invention. FIG. 2 shows one embodiment of a method for manufacturing a dielectric element according to the present invention (hereinafter, referred to as a “element”).
FIG. 9 is a main process sectional view showing a second embodiment).
【０００９】以下、まず図１にしたがい、第１の実施例
について、本発明による誘電体素子を用いた、強誘電性
容量素子を説明する。First, a ferroelectric capacitor using a dielectric element according to the present invention will be described with reference to FIG. 1 for a first embodiment.
【００１０】図１において、１０１はシリコン基板であ
る。１０２は誘電体素子の下地となる絶縁層であり、例
えば、シリコン基板１０１を熱酸化して１μｍの二酸化
シリコン（SiO2）を形成する。In FIG. 1, reference numeral 101 denotes a silicon substrate. Reference numeral 102 denotes an insulating layer serving as a base of the dielectric element. For example, the silicon substrate 101 is thermally oxidized to form 1 μm silicon dioxide (SiO 2 ).
【００１１】１０３は本発明の趣旨による、容量素子の
一方の電極（以下、下部電極とする）であり、例えば白
金を０．５μｍ、スパッタ法により形成した後、例えば
酸素プラズマ中にさらすことにより、下部電極１０３の
表面から酸素を注入し、酸素を含んだ領域１０４を形成
する。Reference numeral 103 denotes one electrode (hereinafter referred to as a lower electrode) of the capacitive element according to the gist of the present invention, which is formed, for example, by forming 0.5 μm of platinum by a sputtering method and then exposing it to, for example, oxygen plasma. Then, oxygen is implanted from the surface of the lower electrode 103 to form a region 104 containing oxygen.
【００１２】１０５は金属酸化物誘電体であり、例えば
強誘電体であるＰＬＺＴ（(Pb0.9La0.1)(Ti0.6Zr0.4)
O3）をゾル−ゲル法により０．５μｍ形成する。１０６
は容量素子のもう一方の電極（以下、上部電極とする）
であり、例えば金を０．５μｍ、スパッタ法により形成
する。１０７は素子保護膜であり、例えば１μｍの二酸
化シリコンを化学気相成長法によって形成する。Reference numeral 105 denotes a metal oxide dielectric, for example, a ferroelectric PLZT ((Pb 0.9 La 0.1 ) (Ti 0.6 Zr 0.4 )
O 3 ) is formed to a thickness of 0.5 μm by a sol-gel method. 106
Is the other electrode of the capacitor (hereinafter referred to as the upper electrode)
For example, gold is formed in a thickness of 0.5 μm by a sputtering method. Reference numeral 107 denotes an element protection film formed of, for example, 1 μm silicon dioxide by a chemical vapor deposition method.
【００１３】以上をもって、本発明の第１の実施例とす
る。The above is a first embodiment of the present invention.
【００１４】従来の技術のように、酸素を含んだ領域１
０４が無い場合においては、初期の自発分極が１０μＣ
／ｃｍ2であったものが、下部電極を接地し上部電極に
＋５Ｖと−５Ｖを交互にかけるサイクルを１０5回繰り
返すと５μＣ／ｃｍ2となり、自発分極の減少が５０％
あった。ところが、本発明の第１の実施例のように、下
部電極１０３の表面に、酸素を含んだ領域１０４を形成
したことにより、同様な電圧サイクルをかけた後でも、
その自発分極は８μＣ／ｃｍ2であり、自発分極の減少
は２０％であった。As in the prior art, the region 1 containing oxygen
04, the initial spontaneous polarization was 10 μC
/ Cm 2 , the cycle in which the lower electrode is grounded and +5 V and −5 V are alternately applied to the upper electrode is repeated 10 5 times, resulting in 5 μC / cm 2 , and a decrease in spontaneous polarization of 50%
there were. However, since the region 104 containing oxygen is formed on the surface of the lower electrode 103 as in the first embodiment of the present invention, even after a similar voltage cycle is applied,
Its spontaneous polarization was 8 μC / cm 2 and the decrease in spontaneous polarization was 20%.
【００１５】次に、図２にしたがい、第２の実施例につ
いて、本発明による誘電体素子、及びその製造方法を用
いた、強誘電性容量素子を説明する。Next, with reference to FIG. 2, a description will be given of a dielectric element according to a second embodiment of the present invention and a ferroelectric capacitive element using the manufacturing method thereof according to the present invention.
【００１６】図２において、２０１はシリコン基板であ
る。２０２は誘電体素子の下地となる絶縁層であり、例
えば、シリコン基板２０１を熱酸化して１μｍの二酸化
シリコン（SiO2）を形成する。２０３は本発明の趣旨に
よる、容量素子の一方の電極（以下、下部電極とする）
であり、例えば白金を０．５μｍ、スパッタ法により形
成する（以上、図２（ａ））。In FIG. 2, reference numeral 201 denotes a silicon substrate. Reference numeral 202 denotes an insulating layer serving as a base of the dielectric element. For example, the silicon substrate 201 is thermally oxidized to form 1 μm silicon dioxide (SiO 2 ). Reference numeral 203 denotes one electrode of a capacitor (hereinafter, referred to as a lower electrode) according to the gist of the present invention.
For example, 0.5 μm of platinum is formed by a sputtering method (FIG. 2A).
【００１７】次に、イオン注入法により、例えば、３０
ｋｅＶで加速した酸素イオン（O2 +）を、注入量１０12
ｃｍ-2で下部電極２０３に注入し、下部電極表面に酸素
を含んだ領域２０４を形成する（以上、図２（ｂ））。Next, for example, 30
Oxygen ions (O 2 + ) accelerated at keV are implanted at a dose of 10 12
Injection into the lower electrode 203 is performed at a density of cm −2 to form a region 204 containing oxygen on the surface of the lower electrode (FIG. 2B).
【００１８】次に、誘電体膜２０５として、例えばペロ
ブスカイト型結晶構造を持つ強誘電性の金属酸化物誘電
体であるＰＺＴ（Pb(Ti0.55Zr0.45)O3）をスパッタ法に
より、０．５μｍ形成し、容量素子のもう一方の電極
（以下、上部電極とする）２０６として、例えば白金を
０．４μｍ、スパッタ法により形成する（以上、図２
（ｃ））。Next, as the dielectric film 205, for example, PZT (Pb (Ti 0.55 Zr 0.45 ) O 3 ), which is a ferroelectric metal oxide dielectric having a perovskite crystal structure, is formed to a thickness of 0.5 μm by sputtering. Then, as another electrode (hereinafter referred to as an upper electrode) 206 of the capacitor, for example, platinum is formed to a thickness of 0.4 μm by sputtering (see FIG. 2).
(C)).
【００１９】最後に、イオン・ドーピング法（質量分析
をしないイオン注入法）により、例えば１００ｋｅＶで
加速した酸素イオン（O+、O2 +、O3 +等）を上部電極２０
６表面から注入する。この時、注入された酸素が、上部
電極２０６と誘電体膜２０５との界面近傍まで到達する
よう、６０ｋｅＶ以上のエネルギーに加速された酸素イ
オンを用いることが望ましい（以上、図２（ｄ））。[0019] Finally, the ion doping method (ion implantation method that does not mass spectrometry), an acceleration oxygen ions 100keV (O +, O 2 + , O 3 + etc.) the upper electrode 20
6 Inject from the surface. At this time, it is desirable to use oxygen ions accelerated to an energy of 60 keV or more so that the implanted oxygen reaches the vicinity of the interface between the upper electrode 206 and the dielectric film 205 (FIG. 2 (d)). .
【００２０】以上をもって、本発明の第２の実施例とす
る。The above is a second embodiment of the present invention.
【００２１】このように、下部電極２０３、及び上部電
極２０６と、誘電体膜２０５との接する領域に、酸素を
含む領域を形成した場合、初期の自発分極は２０μＣ／
ｃｍ2であり、＋５Ｖ、−５Ｖの電圧サイクルを１０5回
印加した後は１６μＣ／ｃｍ2であったが、下部電極２
０３、及び上部電極２０６ともに酸素を含む領域を形成
しなかった場合は、自発分極は初期で２０μＣ／ｃ
ｍ2、同様な電圧サイクル後で８μＣ／ｃｍ2であった。As described above, when a region containing oxygen is formed in a region where the lower electrode 203 and the upper electrode 206 are in contact with the dielectric film 205, the initial spontaneous polarization is 20 μC /
cm 2 , and 16 μC / cm 2 after applying a voltage cycle of +5 V and −5 V 10 5 times.
03 and the upper electrode 206 did not form an oxygen-containing region, the spontaneous polarization was initially 20 μC / c
m 2 , 8 μC / cm 2 after similar voltage cycling.
【００２２】[0022]
【発明の効果】以上述べたように、本発明の誘電体素
子、及びその製造方法によれば、前記誘電体素子に、繰
り返し電圧、あるいは応力を印加した後での、自発分極
の減少やリーク電流の増大を防止し、高い信頼性をもっ
た強誘電体素子を実現することができる。As described above, according to the dielectric element of the present invention and the method of manufacturing the same, the spontaneous polarization is reduced or the leakage is reduced after the voltage or the stress is repeatedly applied to the dielectric element. An increase in current can be prevented, and a highly reliable ferroelectric element can be realized.
【図１】 本発明の第１の実施例の主要断面図。FIG. 1 is a main cross-sectional view of a first embodiment of the present invention.
【図２】 本発明の第２の実施例の主要工程断面図。FIG. 2 is a sectional view of a main process according to a second embodiment of the present invention.
【図３】 従来の技術による、誘電体素子の主要断面
図。FIG. 3 is a main sectional view of a dielectric element according to a conventional technique.
１０１ シリコン基板 １０２ 絶縁層 １０３ 下部電極 １０４ 酸素を含んだ領域 １０５ 誘電体膜 １０６ 上部電極 ２０１ シリコン基板 ２０２ 絶縁層 ２０３ 下部電極 ２０４ 酸素を含んだ領域 ２０５ 誘電体膜 ２０６ 上部電極 ３０１ シリコン基板 ３０２ 絶縁層 ３０３ 下部電極 ３０４ 誘電体膜 ３０５ 上部電極 ３０６ 素子保護膜 Reference Signs List 101 silicon substrate 102 insulating layer 103 lower electrode 104 region containing oxygen 105 dielectric film 106 upper electrode 201 silicon substrate 202 insulating layer 203 lower electrode 204 region containing oxygen 205 dielectric film 206 upper electrode 301 silicon substrate 302 insulating layer 303 Lower electrode 304 Dielectric film 305 Upper electrode 306 Device protection film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/04 H01L 21/822 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 27/04 H01L 21/822
Claims (8)
金属酸化物誘電体薄膜と、該金属酸化物誘電体薄膜上に
形成された上部電極を有する誘電体素子において、 前記下部電極が金属からなり、前記金属酸化物誘電体薄
膜に接する側の界面で、前記下部電極の他の部分よりも
多くの酸素が含まれていて、 前記上部電極が金属からなり、前記金属酸化物誘電体薄
膜に接する側の界面で酸素が含まれていることを特徴と
する誘電体素子。 And a lower electrode formed on the lower electrode.
A metal oxide dielectric thin film; and
In a dielectric element having an upper electrode formed, the lower electrode is made of metal and the metal oxide dielectric thin film is formed.
At the interface on the side in contact with the film, compared to other parts of the lower electrode
The upper electrode is made of a metal and contains a large amount of oxygen ;
The feature is that oxygen is contained at the interface in contact with the film
Dielectric element.
型の結晶構造を有することを特徴とする請求項１記載の
誘電体素子。2. The dielectric element according to claim 1, wherein said metal oxide dielectric has a perovskite crystal structure.
１もしくは２種類以上を主成分とすることを特徴とする
請求項１記載の誘電体素子。3. The dielectric element according to claim 1, wherein the electrode contains one or more of a platinum group element and gold as main components.
(ＺｒxＴｉ1-x)Ｏ3）およびＰＬＺＴ（(Ｐｂ0.9Ｌ
ａ0.1)(Ｔｉ0.6Ｚｒ0.4)Ｏ3）のいずれか一方であるこ
とを特徴とする請求項1記載の誘電体素子。4. The method according to claim 1, wherein the metal oxide dielectric is PZT (Pb
(Zr x Ti 1-x ) O 3 ) and PLZT ((Pb 0.9 L
2. The dielectric element according to claim 1, wherein the dielectric element is any one of a 0.1 ) (Ti 0.6 Zr 0.4 ) O 3 ).
体素子を用いてなることを特徴とする半導体記憶装置。5. A semiconductor memory device using the dielectric element according to claim 1.
下部電極の一対の電極に挟まれた構造を有する誘電体素
子の製造方法において、 前記下部電極を形成する工程と、 前記下部電極の表面の少なくとも一部に酸素を含む領域
を形成する工程と、 前記酸素を含む領域上に金属酸化物誘電体薄膜を形成す
る工程と、 前記金属酸化物誘電体薄膜上に前記上部電極を形成する
工程と、前記上部電極に酸素を注入する工程と を少なくとも含む
ことを特徴とする誘電体素子の製造方法。6. A method for manufacturing a dielectric element having a structure in which a metal oxide dielectric thin film is sandwiched between a pair of an upper electrode and a lower electrode, wherein: a step of forming the lower electrode; and a surface of the lower electrode. Forming a region containing oxygen in at least a part thereof; forming a metal oxide dielectric thin film on the oxygen containing region; forming the upper electrode on the metal oxide dielectric thin film And a step of injecting oxygen into the upper electrode .
において、 前記下部電極の表面の少なくとも一部に酸素を含む領域
を形成する工程が、特に前記電極のうち少なくとも一つ
の電極に酸素イオンを打ち込む工程を含むことを特徴と
する誘電体素子の製造方法。7. The method of manufacturing a dielectric element according to claim 6, wherein the step of forming an oxygen-containing region on at least a part of the surface of the lower electrode includes the step of forming oxygen on at least one of the electrodes. A method for manufacturing a dielectric element, comprising a step of implanting ions.
において、前記下部電極の表面の少なくとも一部に酸素
を含む領域を形成する工程が、特に前記電極のうち少な
くとも一個の電極を酸素プラズマもしくはオゾンプラズ
マ中にさらす工程を含むことを特徴とする誘電体素子の
製造方法。8. The method for manufacturing a dielectric element according to claim 6, wherein the step of forming an oxygen-containing region on at least a part of the surface of the lower electrode includes the step of forming at least one of the electrodes using oxygen. A method for manufacturing a dielectric element, comprising a step of exposing to plasma or ozone plasma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14952192A JP3239445B2 (en) | 1992-06-09 | 1992-06-09 | Dielectric element, method of manufacturing the same, and semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14952192A JP3239445B2 (en) | 1992-06-09 | 1992-06-09 | Dielectric element, method of manufacturing the same, and semiconductor memory device |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11163064A Division JP2000003999A (en) | 1999-06-09 | 1999-06-09 | Dielectric element, its manufacture and semiconductor storage device |
| JP11163062A Division JP2000003997A (en) | 1999-06-09 | 1999-06-09 | Dielectric element and semiconductor storage device |
| JP11163063A Division JP2000003998A (en) | 1999-06-09 | 1999-06-09 | Dielectric element and its manufacture and semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05343616A JPH05343616A (en) | 1993-12-24 |
| JP3239445B2 true JP3239445B2 (en) | 2001-12-17 |
Family
ID=15476959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14952192A Expired - Lifetime JP3239445B2 (en) | 1992-06-09 | 1992-06-09 | Dielectric element, method of manufacturing the same, and semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3239445B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3048652A1 (en) * | 2015-01-26 | 2016-07-27 | TDK Corporation | Piezoelectric thin film element, actuator, sensor, hard-disk drive and ink jet printer incorporating said element |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW322635B (en) * | 1996-04-19 | 1997-12-11 | Matsushita Electron Co Ltd | |
| US6078072A (en) * | 1997-10-01 | 2000-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a capacitor |
| TW483156B (en) * | 1997-11-05 | 2002-04-11 | Ibm | Structure of a material/noble metal substrate laminate and semiconductor memory element |
| KR100277845B1 (en) * | 1998-01-14 | 2001-02-01 | 김영환 | Nonvolatile ferroelectric memory device and method for manufacturing the same |
| JP3830652B2 (en) | 1998-02-27 | 2006-10-04 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR100318457B1 (en) * | 1998-10-28 | 2002-02-19 | 박종섭 | A method for forming ferroelectric film using plasma |
| JP4342131B2 (en) * | 2001-10-30 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | Capacitance element manufacturing method and semiconductor device manufacturing method |
| US20040201049A1 (en) * | 2003-04-11 | 2004-10-14 | Stefan Gernhardt | Suppression of electrode re-crystallisation in a ferrocapacitor |
| JP2007242847A (en) * | 2006-03-08 | 2007-09-20 | Seiko Epson Corp | Capacitor, and manufacturing method thereof |
-
1992
- 1992-06-09 JP JP14952192A patent/JP3239445B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3048652A1 (en) * | 2015-01-26 | 2016-07-27 | TDK Corporation | Piezoelectric thin film element, actuator, sensor, hard-disk drive and ink jet printer incorporating said element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05343616A (en) | 1993-12-24 |
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