JP3139491B2 - Ferroelectric element and semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric element or a structure of a ferroelectric element using a thin film having a ferroelectric substrate.

[0002]

2. Description of the Related Art In a dielectric element having a structure in which a ferroelectric substance is sandwiched between two electrodes, in order to obtain a large-capacity dielectric element having a small area or a ferroelectric capacitive element, conventionally, for example, the journal of Applied Physics (J. Appl. Phys), 1991, Vol. 70,
No. 1, pages 382 to 388,
Platinum (Pt) was used as the electrode material and PZT (Pb (Zr _x Ti _{1 -x} ) O ₃ ) was used as the ferroelectric material.

FIG. 3 shows an example of a ferroelectric element having a structure in which a ferroelectric is laminated on a silicon substrate. In FIG.
Reference numeral 301 denotes a silicon substrate, and 302 denotes an insulating layer of silicon dioxide (SiO ₂ ). Reference numeral 304 denotes a ferroelectric film using PZT, which is sandwiched between a lower electrode 303 and an upper electrode 305 to constitute a capacitive element. 306 is an element protection film.

[0004]

As described above, the lower electrode 3
03, in the structure in which the ferroelectric film 304 and the upper electrode 305 are stacked, when a voltage is applied to the electrodes, the electric field concentrates on the smaller electrode, in this case, the periphery of the upper electrode 305. Therefore, when the positive and negative voltages are alternately applied, the ferroelectric film 305 particularly in the portion where the electric field is concentrated.
The film fatigue (fatigue) progresses, and the device characteristics such as spontaneous polarization deteriorate. When a high voltage is applied, the upper electrode 3
05 in the region where the electric field is concentrated around the periphery of the ferroelectric film 304
Causes dielectric breakdown.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to prevent an electric field from being concentrated around an electrode and to improve the fatigue characteristics and dielectric strength of a ferroelectric element.

[0006]

A ferroelectric element having a structure in which a ferroelectric thin film of the present invention is sandwiched between two electrodes, wherein at least one of the electrodes and the ferroelectric thin film are provided. With a paraelectric layer between
The paraelectric layer is formed such that the thickness of the paraelectric layer decreases from a peripheral portion on the electrode toward a central portion. Further, a semiconductor memory device of the present invention is characterized by using the above ferroelectric element.

[0007]

FIG. 1 is a main sectional view showing a first embodiment of a ferroelectric element according to the present invention. FIG. 2 is a main sectional view showing a second embodiment of the ferroelectric element of the present invention.

First, referring to FIG. 1, as a first embodiment, a structure in which a paraelectric layer is interposed between a peripheral portion of an upper electrode and a ferroelectric film according to the present invention will be described. Will be described.

In FIG. 1, reference numeral 101 denotes a silicon substrate. Reference numeral 102 denotes an insulating layer serving as a base of the ferroelectric element,
For example, the silicon substrate 101 is thermally oxidized to form 1 μm silicon dioxide (SiO ₂ ). Reference numeral 103 denotes one electrode (hereinafter, referred to as a lower electrode) of the ferroelectric element, which is formed, for example, of 0.5 μm of platinum by a sputtering method. 104
Is a ferroelectric film, for example, PZT (Pb (Zr _0.4 Ti _0.6 )
O ₃ ) is formed to a thickness of 0.5 μm by a sol-gel method.
And sinter.

Reference numeral 105 denotes a paraelectric layer according to the gist of the present invention. The paraelectric layer is made of, for example, 0.3 μm of silicon dioxide by chemical vapor deposition (hereinafter referred to as CVD) and has a predetermined size. Reference numeral 106 denotes another electrode (hereinafter, referred to as an upper electrode) of the ferroelectric element.
μm, formed by a sputtering method to form a pattern larger than the opening of the paraelectric layer 105.

The above is a first embodiment of the present invention.

In the ferroelectric device having the structure according to the prior art shown in FIG. 3, the initial spontaneous polarization is 18 μC / cm ² , and the distance between the lower electrode 303 and the upper electrode 305 is ± 30.
After performing a voltage cycle of applying an electric field of 0 kV / cm ² alternately 10 ⁵ times, the voltage was 6 μC / cm ^2. However, as in this embodiment, the peripheral portion of the upper electrode 106 and the ferroelectric film 1
In a case where the paraelectric layer 105 was sandwiched between the first and fourth layers, the initial spontaneous polarization was 18 μC / cm ² , and 13 μC / cm ² even after applying a similar electric field cycle.

Further, in the ferroelectric element having the structure according to the prior art shown in FIG. 3, the lower electrode 303 and the upper electrode 305
Is about 3 MV / cm, but in the structure of this embodiment, the electric field around the upper electrode 106 is relaxed, and the insulation between the lower electrode 103 and the upper electrode 106 is reduced. The withstand voltage was about 3.5 MV / cm.

Next, referring to FIG. 2, as a second embodiment, between the peripheral portion of the lower electrode and the ferroelectric film, the thickness is reduced from the peripheral portion of the lower electrode toward the center portion. The ferroelectric element of the present invention will be described with respect to a structure having a paraelectric layer interposed therebetween.

In FIG. 2, reference numeral 201 denotes a silicon substrate. Reference numeral 202 denotes an insulating layer serving as a base of the ferroelectric element,
For example, the silicon substrate 201 is thermally oxidized to form 1 μm silicon dioxide (SiO ₂ ). Reference numeral 203 denotes one electrode (hereinafter, referred to as a lower electrode) of the ferroelectric element, which is formed, for example, of 0.5 μm of platinum by a sputtering method.

Reference numeral 204 denotes a paraelectric layer according to the gist of the present invention, which is formed, for example, of 0.5 μm silicon dioxide by a chemical vapor deposition method (hereinafter, referred to as CVD), and is opened to a predetermined size. At this time, if the isotropic etching, for example, etching using hydrofluoric acid diluted 1:10 with pure water, the thickness of the paraelectric layer 204 is continuously reduced toward the center of the opening. be able to.

Reference numeral 205 denotes a ferroelectric film, for example, PZT
(Pb (Zr _0.4 Ti _0.6 ) O ₃ ) by a sol-gel method
Form and sinter at 600 ° C. Reference numeral 206 denotes another electrode (hereinafter, referred to as an upper electrode) of the ferroelectric element, which is formed, for example, of 0.5 μm of platinum by a sputtering method.

The above is a second embodiment of the present invention.

As described above, by reducing the thickness of the opening of the paraelectric layer 204 toward the center of the opening, the electric field around the opening is also reduced, and the initial spontaneous polarization there shall was 18μC / cm ² is not only reduced to 16μC / cm ² even after the voltage cycles applied. The withstand voltage between the lower electrode 203 and the upper electrode 206 was about 5 MV / cm.

[0020]

As described above, according to the structure of the ferroelectric element of the present invention, the paraelectric layer is interposed between the peripheral portion of at least one electrode and the ferroelectric film. By continuously reducing the thickness of the paraelectric layer from the periphery of the electrode toward the center, electric field concentration in the periphery of the electrode is reduced, and the fatigue characteristics of the ferroelectric element and the ferroelectric The withstand voltage between the two electrodes of the body element can be improved.

[Brief description of the drawings]

FIG. 1 is a main cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a main cross-sectional view of a second embodiment of the present invention.

FIG. 3 is a main cross-sectional view of a ferroelectric element according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 101 silicon substrate 102 insulating layer 103 lower electrode 104 ferroelectric film 105 paraelectric layer 106 upper electrode 201 silicon substrate 202 insulating layer 203 lower electrode 204 paraelectric layer 205 ferroelectric film 206 upper electrode 301 silicon substrate 302 insulating layer 303 Lower electrode 304 Ferroelectric film 305 Upper electrode 306 Device protection film

Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/108 29/788 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/10 451 H01L 21/822 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/108 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A ferroelectric element having a structure in which a ferroelectric thin film is sandwiched between two electrodes, wherein a paraelectric substance is provided between at least one of the electrodes and the ferroelectric thin film. A ferroelectric element having a layer, wherein the paraelectric layer is formed such that the thickness of the paraelectric layer decreases from a peripheral portion on the electrode toward a central portion. 2. A semiconductor memory device comprising the ferroelectric element according to claim 1.