JP3226989B2 - Ferroelectric memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a ferroelectric thin film as a storage medium, and more particularly to a ferroelectric memory using a bidirectional silicon diode having a non-linear current-voltage characteristic as a switching element.

[0002]

2. Description of the Related Art A ferroelectric memory using a ferroelectric as a recording medium has attracted attention as a new nonvolatile memory.
As a typical structure example of the ferroelectric memory, there is an example described in Japanese Patent Application No. 4-67275. As shown in FIG. 6, the ferroelectric memory cell is roughly divided into a ferroelectric portion a serving as an information recording area, and a switching element portion b including a transistor for preventing read / write selection and crosstalk. You.

For use as a general memory device, a memory device is constructed by arranging the ferroelectric memory cells in a two-dimensional matrix. And
The switching element of the selected memory cell is turned on / off to write / read information.

Further, in order to realize integration of a ferroelectric memory, switching of a two-terminal structure as disclosed in Japanese Patent Application Nos. 3-314508 and 4-67275 by the present applicant has been proposed. A ferroelectric memory having a laminated structure in which elements are formed in upper (lower) layers of a ferroelectric portion has been proposed.

[0005]

However, in the structure of a ferroelectric memory using the above-described transistor as a switching element, as shown in FIG. 6, the switching element section b is replaced with the ferroelectric section a for recording information. Depends on the surface.

Therefore, when a ferroelectric memory cell is integrated to form a large-capacity memory device, the area occupied by the switching element part b is reduced even if the area of the ferroelectric part a is reduced. Without this, it is impossible to increase the storage capacity.

Further, the ferroelectric memory proposed in Japanese Patent Application Nos. 3-314508 and 4-67275 uses a ferroelectric thin film in order to improve characteristics such as current capacity and breakdown voltage. An oxide thin film varistor using a polycrystalline semiconductor to which zinc oxide, barium titanate, and strontium titanate are added is used. However, when actually manufacturing a memory device, the manufacturing steps are complicated and complicated.
Further, since a heat treatment process at a high temperature is required, the polarization characteristics of the ferroelectric thin film also deteriorate.

That is, if a two-terminal switching element can be constituted by a silicon-based material, the consistency of the manufacturing process can be achieved, so that the process can be simplified and the cost is useful.

Accordingly, the present invention provides a ferroelectric memory in which a two-terminal element having a non-linear current-voltage characteristic is made of a silicon material, and a non-linear resistor and a ferroelectric cell with matching are stacked in layers. The purpose is to:

[0010]

According to the present invention, there is provided a semiconductor device comprising: a lower stripe electrode provided on a semiconductor substrate; an upper stripe electrode provided in a direction orthogonal to the lower stripe electrode; A ferroelectric layer provided on the lower stripe electrode in a region where the lower stripe electrode and the upper stripe electrode intersect, a square electrode provided on the ferroelectric layer, and a fourth electrode provided on the square electrode. A first gold alloy electrode layer, a second gold alloy electrode layer provided on the first gold alloy electrode layer, and one surface in contact with the second gold alloy electrode layer, and the other surface in contact with the upper stripe electrode. A bidirectional silicon diode layer provided so as to be in contact with the semiconductor substrate, and an interlayer insulating film is provided on the semiconductor substrate except for an intersection region between the lower stripe electrode and the upper stripe electrode. To provide a dielectric memory.

[0011]

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the structure of a ferroelectric memory according to a first embodiment of the present invention. In this ferroelectric memory, a silicon oxide layer (SiO ₂ ) 2 is formed on the surface of a silicon semiconductor substrate 1, and a lower stripe electrode 3 made of metal or the like is formed thereon. An upper stripe electrode 4 is formed above the lower stripe electrode 3 in a direction orthogonal to each other. A cell portion in which a ferroelectric layer 5 and a bidirectional silicon diode layer 6 are laminated on the lower stripe electrode 3 is formed in a region where the lower stripe electrode 3 intersects and overlaps with the lower stripe electrode 3. Is formed so as to be filled with an interlayer insulating film 7 of PSG or the like for electrically insulating the substrate. FIG. 2 shows an equivalent circuit of such a ferroelectric memory.

Here, the above-described bidirectional silicon diode layer (cell) 6 will be described with reference to FIG. This bidirectional silicon diode cell is formed on each of the ferroelectric layers 5 arranged in a matrix as shown in FIGS.

The bidirectional silicon diode cell has an n
From both main surface sides of the silicon substrate 8, the vicinity of the junction is set to a dopant density of 1 × so as to correspond to the ferroelectric layer 5.
Impurities are diffused to about 10 ²⁰ cm ⁻³ to form p-type semiconductor regions 9 and 10. Further, guard rings 11a, 11b, 11c, 11d are formed by a usual method so that electric field concentration does not occur at the edge portions e of the p-type semiconductor regions 9, 10.

Further, a silicon oxide layer (SiO ₂ ) 12
After opening a via hole, an AuSb electrode 13 is formed on the main surface side which is thermocompressed and in contact with the ferroelectric layer 5, and an Al electrode 14 is formed on the main surface side on which the upper stripe electrode is formed. Is subjected to a flattening process such as polishing to make it a mirror surface. Next, FIGS. 4 and 5 show the steps of manufacturing the ferroelectric memory according to the first embodiment and will be described.

First, in FIG. 4A, the silicon semiconductor substrate 1 is thermally diffused in an oxygen atmosphere, and the S
An iO ₂ layer 2 is formed. For example, a metal film (lower stripe electrode) 3 is formed thereon by a sputtering device or the like, and a ferroelectric thin film 5 such as PZT is formed.

In FIG. 4B, platinum is formed on the entire surface of the ferroelectric thin film 5 using a sputtering device or the like, and is selectively removed using a photolithography technique to reduce the size to one memory size. The square electrode 15 is obtained by etching to a corresponding shape and size.

Then, an insulating film 16 of PSG, SiO ₂ or the like is formed.
Is formed on the entire surface by a plasma CVD apparatus or the like, and a via hole is opened at a predetermined position. Further, after forming an alloy thin film of gold, AuSb, or the like on the entire surface, it is selectively removed to form a square Au / Ti alloy electrode 17.

Further, in the thermocompression bonding performed in the next step, in order to enhance the adhesion between the substrates to be bonded, an insulating polyimide is applied onto the substrate by a spin coater until the Au / Ti alloy electrode layer 17 is completely covered. After baking in a nitrogen atmosphere to evaporate the solvent to form a polyimide layer 18, the polyimide layer 18 is removed by oxygen plasma etching (ashing) until the Au / Ti alloy electrode layer 17 is exposed. Thereafter, the surface is flattened (mirror state) by polishing or the like.

Next, in FIG. 5A, the bidirectional silicon diode layer 6 shown in FIG. 3 is mounted on a substrate, and the AuSb electrode 13 and the Au / Ti alloy electrode 17 are connected by the off-axis method. Make sure that they match each other. Next, while heating, pressurization is performed for a certain period of time, and the final curing of the polyimide layer 18 is performed. It should be noted that such a lamination technique is known as EL
VIC (Elemental Level Vertically

Integrated Circuit)
It is known as a technology, and is used in a manufacturing process or the like in which two LSI chips produced by a conventional LSI technology are faced to each other and bonded, and upper and lower circuits are electrically connected by diffusion welding.

Next, referring to FIG. 5B, a stripe having a width of one side of the memory cell is set so as to expose the surface of the SiO ₂ film 2 by an ion milling device selectively by the photolithography technique. Etch into a shape. Next, the stripes in the direction perpendicular to the stripes are selectively removed to the surface of the lower electrode 3 so as to form a square cell.

In FIG. 5C, an interlayer insulating film 7 made of an insulator such as PSG or BPSG is formed between the square cells by plasma CVD or the like, and the via hole is opened to expose the Al electrode 14. After that, the upper stripe electrodes 4 having the same width as the width of the lower stripe electrodes and perpendicular to each other are formed.

As described above, the ferroelectric memory according to the present embodiment is characterized in that the bidirectional silicon diode formed separately from the substrate is laminated on the ferroelectric layer by thermocompression bonding, so that the ferroelectric memory generated at the time of the conventional manufacturing can be obtained. Deterioration of the polarization characteristics of the dielectric, breakdown voltage of the switching element, operation failure, and the like are reduced. Further, since each memory cell is separated and electrically insulated, no crosstalk occurs with respect to an unselected memory cell near the selected memory cell, thereby preventing data destruction. In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications and applications are possible without departing from the spirit of the invention.

[0026]

As described above in detail, according to the present invention, a two-terminal element having a non-linear current-voltage characteristic is made of a silicon material, and a matched non-linear resistor and ferroelectric cell are formed in layers. A stacked ferroelectric memory can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a ferroelectric memory as a first embodiment according to the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit of the ferroelectric memory according to the first embodiment;

FIG. 3 is a diagram showing a structure of a bidirectional silicon diode cell of the ferroelectric memory of the first embodiment.

FIG. 4 is a diagram illustrating the first half of the manufacturing process of the ferroelectric memory according to the first embodiment;

FIG. 5 is a diagram illustrating the first half of the manufacturing process of the ferroelectric memory according to the first embodiment;

FIG. 6 is a diagram illustrating a structural example of a conventional ferroelectric memory.

[Explanation of symbols]

1 ... silicon semiconductor substrate, 2, 12 ... silicon oxide layer (SiO _2), 3 ... bottom stripe electrode, 4 ..., 5 ... ferroelectric layer, 6 ... top stripe electrode, 7 ..., the bidirectional silicon diode layer 6, 8 ... n-type silicon substrate, 9, 10
... p-type semiconductor regions, 11a, 11b, 11c, 11d ...
Guard ring, 13: AuSb electrode, 14: upper stripe electrode (Al electrode), 15: square electrode, 16: insulating film, 17: Au / Ti alloy electrode, 18: insulating polyimide.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-180261 (JP, A) JP-A-57-100770 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/105 G11C 11/22 H01L 29/749

Claims (1)

(57) [Claims] A lower stripe electrode provided on a semiconductor substrate; an upper stripe electrode provided in a direction orthogonal to the lower stripe electrode; and a lower stripe in a region where the lower stripe electrode and the upper stripe electrode intersect. A ferroelectric layer provided on the electrode, a square electrode provided on the ferroelectric layer, a first gold alloy electrode layer provided on the square electrode, and a first gold alloy electrode A second gold alloy electrode layer provided on the layer; and a bidirectional silicon diode layer provided such that one surface is in contact with the second gold alloy electrode layer and the other surface is in contact with the upper stripe electrode. A ferroelectric memory, wherein an interlayer insulating film is provided on the semiconductor substrate except for an intersection region between the lower stripe electrode and the upper stripe electrode.