CN1142587C - Semiconductor device - Google Patents
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- CN1142587C CN1142587C CNB971906068A CN97190606A CN1142587C CN 1142587 C CN1142587 C CN 1142587C CN B971906068 A CNB971906068 A CN B971906068A CN 97190606 A CN97190606 A CN 97190606A CN 1142587 C CN1142587 C CN 1142587C
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed.Measure to Solve: Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2. The characteristic variation of a ferroelectric capacitor of a semiconductor device is reduced and the characteristic variation, namely, the characteristic deterioration with time of the capacitor is suppressed. The capacitor is constituted of lower electrode (111a) having a planar shape which extends in a first direction D1 and having a width in a second direction D2 perpendicular to the first direction D1, a plurality of upper electrodes (112a) which are arranged above the electrode (111a) so that the electrodes (112a) are opposed to the electrodes (111a), and ferroelectric layers arranged between both electrodes (111a and 112a). The dimensions of the electrodes (112a) in the first direction D1 are smaller than those in the second direction D2.
Description
The present invention relates to semiconductor device, particularly relate in the ferroelectric storage device improvement of and performance degradation discrete characteristic.
As the conventional semiconductor device, to have developed from for example being equipped with amplifying circuit, the smaller integrated circuit of scale of oscillating circuit and power circuit etc. arrives the various devices as the large-scale integrated circuit of microprocessor or memory device.Particularly in the last few years, a kind of as nonvolatile semiconductor memory member, people have proposed a kind of ferroelectric storage device that has ferro-electric materials capacitor.
Above-mentioned ferro-electric materials capacitor is made of pair of electrodes in opposite directions and the dielectric layer that is made of the strong dielectric material that is sandwiched between this two electrode, has hysteresis characteristic for the corresponding relation between the polarizability of above-mentioned two interelectrode applied voltages and strong dielectric material.Promptly, constituting of ferro-electric materials capacitor: even if when electric field (applied voltage) is zero, in the strong dielectric layer, also can be left residual polarization with the corresponding polarity of alive hysteresis, in above-mentioned ferroelectric storage device, adopt the way of representing to store data with the residual polarization of ferro-electric materials capacitor, realized the non-volatile of storage data.
In the nonvolatile semiconductor memory member of having used this ferro-electric materials capacitor, important problem is to reduce hysteresis characteristic discrete of ferro-electric materials capacitor, and reduces the change because of using hysteresis characteristic to produce.
Below carry out specific description.Figure 14～Figure 16 is used for illustrating existing ferroelectric storage device.The plane graph of Figure 14 shows the memory cell array of this ferroelectric storage device.Figure 15 is the profile of the XV-XV line part among this Figure 14.Shown in the plane graph of Figure 16 is the upper electrode and the relation of the position between the electricity of bottom of ferro-electric materials capacitor.
In the drawings, the 200th, the memory cell array of formation ferroelectric storage device, in its silicon substrate 201 tops, be arranged with a plurality of transistor area 220a along the 1st direction D1, formed device isolation dielectric film 202 on the part beyond the transistor area 200a of this silicon substrate 201.
In addition, in the both sides along the rowed transistor of the 1st direction D1 zone 220a, being situated between is formed with lower electrode (1st electrode) 211 in device isolation film 202 tops as cell board (Cell plate) electrode with the 1st interlayer dielectric 203.This lower electrode 211 is made of the metal material of titanium or platinum etc., has the banded flat shape of extending along above-mentioned the 1st direction.On the surface of this lower electrode, formed strong dielectric layer 213.
In addition, on the strong dielectric layer 213 on lower electrode 211 surfaces, formed the upper electrode (the 2nd electrode) 212 that the metal material by titanium or platinum etc. constitutes accordingly with above-mentioned each transistor area 220a.That is,, dispose a plurality of upper electrodes 212 along above-mentioned the 1st direction D1 in above-mentioned strong dielectric layer 213 top.The flat shape of each upper electrode 212 has become to being the rectangular shape of long side direction with above-mentioned the 1st direction D1, and in addition, as shown in Figure 14, it is littler than the area of lower electrode 211 that the area of this each upper electrode 212 has become.Here, ferro-electric materials capacitor 210, be made of above-mentioned lower electrode 211, upper electrode 212 and the strong dielectric layer 213 between them, the surface of the surface of above-mentioned strong dielectric layer 213 and above-mentioned lower electrode 211 is covered by the 2nd interlayer dielectric 204.
In addition, in the drawings, above-mentioned upper electrode 212 has been configured in the middle body of lower electrode 211, make and the side 211a1 of a side's of lower electrode 211 side 211a1 and upper electrode on the other side 212 between distance (below, being referred to as non-overlapped width) distance between the opposing party's of O11 and lower electrode 211 side 211a2 and the side 211a2 of upper electrode on the other side 212 (below, be referred to as non-overlapped width) O12 equates.
In addition, between a pair of lower electrode 211 that above-mentioned transistor 220a is clipped in the middle in opposite directions, being configured to a pair of word line that is made of polysilicon (the 2nd wiring) 223a, 223b across lining up is a plurality of transistor area 220a top of row.This word line 223a in this each transistor area 220a, the both sides of 223b have formed the source diffusion zone 222 of the memory transistor 220 that constitutes memory cell and have leaked diffusion zone 221.Be positioned at the part of each transistor area 220a top of above-mentioned word line 223a and 223b, constituted the gate electrode of above-mentioned memory transistor 220, be positioned at the substrate surface top by gate insulating film 202a.The surface of above-mentioned diffusion zone 221,222 and word line 223a, 223b is covered by the above-mentioned the 1st and the 2nd interlayer dielectric 203 and 204.In addition, in Figure 14, these interlayer dielectrics are omitted.
The source diffusion zone 222 between a pair of word line 223a and 223b among above-mentioned each transistor area 202a, the contact hole 205b of Jie to have formed on above-mentioned the 1st, the 2nd interlayer dielectric 203,204 is connected to along on the bit line 233b of the 2nd direction extension vertical with above-mentioned the 1st direction D1.In addition, be arranged in the leakage diffusion zone 221 in the outside of in opposite directions word line 223a, the 223b of above-mentioned each transistor area 220a, be connected wiring 233a and be connected on the above-mentioned upper electrode 212.Promptly, the end of above-mentioned connecting wiring 233a is connected on the above-mentioned upper electrode 212 by the contact hole 204a that forms on above-mentioned the 2nd dielectric film 204, and the other end of above-mentioned connecting wiring 233a is by being connected at the contact hole 205a that forms on above-mentioned the 1st, the 2nd dielectric film 203,204 Lou on the diffusion zone 221.
Here, above-mentioned upper electrode 211 and strong dielectric layer 213 are to form the metal material of titanium or platinum etc. and the film of strong dielectric material successively in above-mentioned interlayer dielectric 203 tops, make this film form figure then and constitute.212 of above-mentioned upper electrodes are the films that forms the metal material of titanium or platinum etc. in above-mentioned strong dielectric layer 213 top earlier, make this film form figure then and constitute.In addition, above-mentioned bit line 233b and connecting wiring 233a make the metal film of the aluminium that forms in above-mentioned interlayer dielectric 204 tops etc. scribe into figure and form.Above-mentioned word line 223a, 223b then make the polysilicon film that forms on gate insulating film 202a and device isolation dielectric film 202 scribe into figure and constitute.
Above-mentioned the 1st interlayer dielectric 203 is made of the insulating material of NSG (silica system) or BPSG (boron phosphorus doping silica) etc., and the 2nd interlayer dielectric 204 is made of for example PSG (mixing phosphor silicon oxide).
In addition, the strong dielectric material as the strong dielectric layer 213 that constitutes ferro-electric materials capacitor has KNO as everybody knows
3, PbLa
2O
3-ZrO
2-TiO
2, and PbTiO
3-PbZrO
3Deng.In addition, disclose in the WO93/12542 communique in that PCT is international, announced be suitable for doing ferroelectric storage device and PbTiO
3-PbZrO
3Compare tired extreme little strong dielectric material.
Secondly, simply action is described.
In the ferroelectric storage device that constitutes like this, when selecting for example word line 223a, (for example then drive one of lower electrode 211, when the lower electrode of the top shown in Figure 14) making its voltage level become to the level corresponding with logic voltage " H ", the storage data of the ferro-electric materials capacitor 210 that forms in this lower electrode top will be read each bit line by connecting wiring 233a and transistor 220.
The principle of action is read in explanation simply.Figure 17 shows the hysteresis characteristic of ferro-electric materials capacitor with the form of curve, and the longitudinal axis is corresponding with the amount of polarizing charge P of ferro-electric materials capacitor, transverse axis then be added to ferro-electric materials capacitor on applied voltage E corresponding.In addition, P1, P2 be respectively add electric field E1, E2 to ferro-electric materials capacitor (=-amount of polarizing charge that produced in E1), Pr1 is the residual charge amount corresponding with applied voltage E1, Pr2 be with applied voltage E2 (=-E1) corresponding residual charge amount, Ec1 is and the corresponding coercive electric field of residual charge amount Pr2, and Ec2 is and the corresponding coercive electric field of residual charge amount Pr1.In addition, in this ferroelectric storage device, when sense data, the read-out voltage (promptly being added in the voltage on the lower electrode) that is added on the ferro-electric materials capacitor is decided by that the extra electric field of above-mentioned ferro-electric materials capacitor will become the voltage of E2.
In above-mentioned ferroelectric storage device, in each memory cell, write into the storage data of regulation, the residual charge amount that constitutes the ferro-electric materials capacitor of this memory cell become for these storage data " 1 " or " 0 " corresponding residual charge amount Pr1 or Pr2.Under this state, when the word line that drives regulation, and when the lower electrode of the regulation of ferro-electric materials capacitor added above-mentioned read-out voltage, the ferro-electric materials capacitor from the lower electrode top that is arranged in this regulation read into the electric charge corresponding with residual charge amount Pr1 or Pr2 on the bit line.
For example, be the ferro-electric materials capacitor of Pr2 from the residual charge amount, the poor Δ P2 between amount of polarizing charge P2 corresponding and the residual charge amount Pr2 with applied voltage E2 (=Pr2-P2), as reading on the bit line 233b with the corresponding signal charge of storage data.In addition, be the ferro-electric materials capacitor of Pr1 from the residual charge amount, the poor Δ P1 between amount of polarizing charge P2 corresponding and the residual charge amount Pr1 with applied voltage E2 (=Pr1-P2), as reading on the bit line with the corresponding signal charge of storage data.In this case, because the quantity of electric charge of being read on the bit line (Pr1-P2) is different with (Pr2-P2), so, can discern the data that are stored in the memory cell by means of the difference of this quantity of electric charge.So, in the formation of sense data from ferro-electric materials capacitor, be the memory cell of residual charge amount Pr1 for the residual charge amount of ferro-electric materials capacitor, will produce data corruption because of reading action.Therefore, this ferroelectric storage device has following circuit and constitutes: carrying out the storage data before the sense data being written to the data of going to repair memory cell in each ferro-electric materials capacitor after data read.
The signal charge corresponding with the storage data on reading into each bit line 233b then is read out the outside of transporting to ferroelectric storage device after amplifier (not drawing) amplifies.Afterwards, make the voltage level of above-mentioned lower electrode 211 become for the corresponding level of logic voltage " L ", above-mentioned word line 223a is become to not selecting state to finish to read.
Yet, in existing ferro-electric materials capacitor 210, exist the discrete of characteristic, promptly the polarizability of strong dielectric layer is discrete big, and flutter promptly is easy to produce the problem of the time to time change of polarizability.
Promptly, in the lag curve of the above-mentioned ferro-electric materials capacitor that is shown in Figure 17, the amount of polarizing charge P1 to extra electric field E1, E2, P2, coercivity electric field ec 1, Ec2, the perhaps initial value of residual charge amount Pr1, Pr2, between the memory cell in a device (ferroelectric storage device) or between device, to form big discrete, the change (from the variation of the characteristic of normal characteristic after the degeneration shown in the curve Lb shown in the usefulness curve La) that produces the hysteresis characteristic of passing of the time that is accompanied by in perhaps between short-term.
The present invention invents for solving problem as described above, its objective is provides the discrete of a kind of characteristic that can suppress ferro-electric materials capacitor, and can reduce semiconductor device flutter, that durable years is long, fabrication yield is high along with the institute's association of passing of time.
The semiconductor device of the present invention the 1st aspect is to possess: have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction; Be configured to and the 1st electrode a plurality of the 2nd electrodes in opposite directions, have size and equal flat shape or the flat shape shorter of the size on above-mentioned the 1st direction of the size on above-mentioned the 2nd direction on above-mentioned the 1st direction than the size on above-mentioned the 2nd direction; And be configured in strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode, constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode, become the row configuration along above-mentioned the 1st direction with being adjacent to each other corresponding to above-mentioned a plurality of ferro-electric materials capacitors of above-mentioned the 1st electrode.
The semiconductor device of the present invention the 2nd aspect, be aspect the 1st in the described semiconductor device, above-mentioned the 2nd electrode is to make the conductive material layer of regulation scribe into figure and the electrode that forms, and the configuration space of the 2nd electrode that this is adjacent is the minimum dimension of the opening figure that can form on above-mentioned conductive material.
The semiconductor device of the present invention the 3rd aspect is aspect the 1st in the described semiconductor device, and the flat shape of above-mentioned the 2nd electrode is four polygonals after the chamfering of angle, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
The semiconductor device of the present invention the 4th aspect, be aspect the 1st, in the described semiconductor device, also to possess: each of above-mentioned a plurality of ferro-electric materials capacitors be connected to a plurality of memory transistors each formation, be arranged in rectangular a plurality of memory cell; Be used to drive the unit printed line of this ferro-electric materials capacitor; Each that constitutes with above-mentioned a plurality of memory cell is listed as corresponding multiple bit lines; Each row many word lines corresponding, that be used to select above-mentioned memory transistor with above-mentioned a plurality of memory cell formations; And be connected on the above-mentioned bit line, amplify the sense amplifier of the data-signal on the bit line of stipulating.
The semiconductor device of the present invention the 5th aspect, be aspect the 1st in the described semiconductor device, also possess: cover the dielectric film of the surface formation of above-mentioned the 2nd electrode, have on the surface of the 2nd electrode the contact hole that forms from the position that its central position deviation comes.
The semiconductor device of the present invention the 6th aspect is in the described semiconductor device, also to possess aspect the 1st: cover the dielectric film of the surface formation of the 2nd electrode, have the contact hole of the 2nd electrode relatively; Above-mentioned the 2nd electrode constitutes and makes it all, is divided into a plurality of electrodes structure partly by the breach that excises from side one side of its regulation, and above-mentioned contact hole is arranged on a part of electrode of a plurality of electrodes parts that constitute the 2nd electrode.
The semiconductor device of the present invention the 7th aspect is aspect the 1st in the described semiconductor device, and above-mentioned the 2nd electrode is littler than the width of the 2nd electrode on the 1st direction at the configuration space on the 1st direction.
The semiconductor device of the present invention the 8th aspect is to possess: have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction; With the 1st electrode a plurality of the 2nd electrodes in opposite directions, above-mentioned the 2nd electrode has size and equal flat shape or the flat shape shorter than the size on above-mentioned the 2nd direction of the size on above-mentioned the 1st direction of the size on above-mentioned the 2nd direction on above-mentioned the 1st direction; And be configured in strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode, constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode, it is rectangular to be with above-mentioned the 1st direction and the 2nd direction that column direction and line direction are configured to respectively corresponding to above-mentioned a plurality of ferro-electric materials capacitors of above-mentioned the 1st electrode, makes the 2nd electrode of the ferro-electric materials capacitor arranged along this column direction be adjacent to each other.
The semiconductor device of the present invention the 9th aspect is to possess: have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction; Be configured to and the 1st electrode in opposite directions and have with a plurality of the 2nd electrodes of the direction between the 1st direction and the 2nd direction for the flat shape of its long side direction; And be configured in strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode, constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode, become the row configuration along above-mentioned the 1st direction with being adjacent to each other corresponding to above-mentioned a plurality of ferro-electric materials capacitors of above-mentioned the 1st electrode.
The semiconductor device of the present invention the 10th aspect is aspect the 9th in the described semiconductor device, and the flat shape of above-mentioned the 2nd electrode is a polygonal, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
The semiconductor device of the present invention the 11st aspect is to possess: have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction; Be configured to the 1st electrode in opposite directions and have the 2nd electrode of and in opposite directions 1st side the most contiguous and and in opposite directions 2nd side the most contiguous with the 2nd side parallel with the 1st direction of the 1st electrode with the 1st side parallel with the 1st direction of the 1st electrode; And be clipped in strong dielectric layer between above-mentioned the 1st electrode and the 2nd electrode, and, constitute ferro-electric materials capacitor with above-mentioned the 1st, the 2nd electrode and this two interelectrode strong dielectric layer, do the length of the 1st side of above-mentioned the 2nd electrode also longlyer, and make distance till the 1st side of the 1st side to the 1 electrode of the 2nd electrode do to become also bigger than the distance till the 1st side of the 2nd side to the 1 electrode of the 2nd electrode than its 2nd side.
The semiconductor device of the present invention the 12nd aspect is aspect the 11st in the described semiconductor device, and the flat shape of above-mentioned the 2nd electrode is the polygonal shape, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
The plane graph of Fig. 1 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 1.
Fig. 2 is the profile of the II-II line part among Fig. 1.
Shown in the plane graph of Fig. 3 is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of the foregoing description 1.
The plane graph of Fig. 4 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 2.
Shown in the plane graph of Fig. 5 is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of the foregoing description 2.
The plane graph of Fig. 6 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 3.
Shown in the plane graph of Fig. 7 is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of the foregoing description 3.
Fig. 8 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 4, and what this illustrated is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device.
Fig. 9 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 5, and what this illustrated is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device.
Figure 10 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 6, and what Figure 10 (a) illustrated is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device; Figure 10 (b) is the key diagram of shape that is used to illustrate the upper electrode of present embodiment 6, and what Figure 10 (c) illustrated is the shape of the upper electrode of present embodiment 6.
The plane graph of Figure 11 shows the upper electrode structure of having used the ferro-electric materials capacitor in the foregoing description 6, has effectively utilized the formation of the memory cell array of device area.
The plane graph of Figure 12 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 7.
Shown in the plane graph of Figure 13 is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of the foregoing description 7.
The plane graph of Figure 14 shows the memory cell array that constitutes existing ferroelectric storage device.
Figure 15 is the profile of the XV-XV line part of Figure 14.
Shown in Figure 16 is the lower electrode and the relation of the position between the upper electrode of the ferro-electric materials capacitor in the existing ferroelectric storage device.
The curve chart of Figure 17 shows the hysteresis characteristic of above-mentioned ferro-electric materials capacitor with curve.
At first, the starting point of the present invention and basic principle are described.
The result that this patent inventor etc. deliberately studies for achieving the above object finds above-mentioned The change of the discrete or characteristic of the characteristic of ferro-electric materials capacitor is owing to forming formation by force Behind the strong dielectric layer of dielectric capacitor, carry out all processing and make the material of strong dielectric layer The material quality degradation.
That is, above-mentioned lower electrode and strong dielectric layer have formed platinum etc. in the interlayer dielectric top Metal film and strong dielectric film after, scribe into them after the figure and form, so advancing Row is when being carved into figure, and etching agent etc. will be from because carrying out strong dielectric that etching processing exposes The side is invaded as impurity, will produce quality of materials at the lateral section of strong dielectric layer and move back Change. In addition, when carrying out this etching, because between strong dielectric layer and the lower electrode Also expose at the interface, so because the intrusion of impurity will form resistive layer etc. on this part.
In addition, upper electrode is owing to want earlier the platinum that has formed in above-mentioned strong dielectric layer top Deng metal film form after scribing into figure, so when this scribes into figure, strong dielectric Layer, revealed the part of coming out and be exposed within the etching processing because removing metal film, because of This will produce the quality of materials degeneration on the part of upper electrode of the layer of strong dielectric.
Also have, the part on the upper electrode of optionally removing interlayer dielectric forms contact hole When, impurity will be invaded the strong dielectric layer via the upper electrode that exposes in this contact hole, When forming connecting wiring, this also will be via above-mentioned as the titanium of the constituent material of this connecting wiring etc. Upper electrode invades in the strong dielectric and goes. Therefore, with the contact hole part of strong dielectric layer To produce quality of materials in the corresponding part degenerates.
From above-mentioned situation as can be known, adopt the wide of the increasing direction vertical with the long side direction of lower electrode The degree size is configured to make it to leave as best one can the lateral section of lower electrode to upper electrode, and Strengthen the way of the area of upper electrode, although can reduce because of the forceful electric power in the strong dielectric electric capacity The Impurity Diffusion of dielectric layer is to the impact of deterioration part, if but merely strengthen upper electrode or lower The size of section's electrode, for example, above-mentioned non-overlapped width O11 shown in Figure 16, O12 expands Big to greater than the width W 2 of upper electrode 212 time, then the width W 1 of lower electrode 211 will Be wider than (W2+O11+O12), will be created in the layout on the substrate of memory cell array Area increases such new problem significantly.
So the inventor etc. also find to consist of the upper electrode shape of ferro-electric materials capacitor and upper State the relevance between characteristic discrete, and the position of the contact hole on the upper electrode with on State the relevance of characteristic between discrete, and can avoid above-mentioned new problem to send out as having it is found that The method of giving birth to.
That is, inventor herein etc. are conceived in existing ferro-electric materials capacitor 210, by Length L 2 in above-mentioned upper electrode 212 will be grown with respect to its width W 2, so be subjected to strong dielectric The impact of the quality of materials degeneration part of layer side is big, and becoming is easy to produce ferro-electric materials capacitor The discrete or flutter of characteristic, find: produce the strong dielectric that consists of ferro-electric materials capacitor The part that the quality of materials of layer is degenerated mainly is the side part nearby that is positioned at lower electrode, Adopt the flat shape of upper electrode is become width take lower electrode as long side direction Way, just can reduce the quality of materials of the strong dielectric layer that is contained in the ferro-electric materials capacitor Degenerate and partly can not cause dwindling of the area of upper electrode.
Also find, adopt the contact hole of above-mentioned upper electrode is configured in from central of upper electrode Put to side one lateral deviation of lower electrode and leave next locational way, just can inhibition of impurities From this contact hole via the diffusion of upper electrode to the strong dielectric layer.
Below, each embodiment of the present invention based on the above starting point and basic principle is described.
Fig. 1～Fig. 3 is the key diagram that is used to illustrate the ferroelectric storage device of embodiments of the invention 1, the plane graph of Fig. 1 shows the part of the memory cell array that constitutes this ferroelectric storage device, Fig. 2 is the profile of the II-II line part among Fig. 1, and shown in the plane graph of Fig. 3 is lower electrode and the relation of the position between the upper electrode that constitutes the ferro-electric materials capacitor of memory cell.
In the drawings, the 100th, constitute ferroelectric storage device memory cell array, in its silicon substrate 101 tops, dispose transistor area 120a along the 1st direction D1 with the 2nd vertical with it direction D2 rectangularly, on the surf zone beyond each transistor area of this silicon substrate 101, formed device isolation dielectric film 102.
In addition, be provided with lower electrode (the 1st electrode) 111a in each transistor area 120a both sides that are listed as cell board electrode along the 1st direction D1.This lower electrode 111a forms after the metal film of titanium or platinum etc. is scribed into figure, and Jie is disposed at device isolation dielectric film 102 tops with the 1st zone isolation dielectric film 103.In addition, above-mentioned lower electrode 111a extends along above-mentioned the 1st direction D1, and having with 2nd direction vertical with the 1st direction is the banded flat shape of wiring width direction, and has formed strong dielectric layer 113 on this surface.
In addition, scribe into figure and formed upper electrode (the 2nd electrode) 112a by means of the metal film that makes platinum etc. in strong dielectric layer 113 top on the surface of above-mentioned each lower electrode 111a.Promptly, dispose a plurality of upper electrode 112a along above-mentioned the 1st direction D1 in strong dielectric layer 113 top of above-mentioned each lower electrode 111a.In addition, the flat shape of each upper electrode 112a has become to being the rectangular shape of long side direction with above-mentioned the 2nd direction D2, and the area of this upper electrode 112a has become littler than the area of lower electrode 111a.The surface of the surface of above-mentioned strong dielectric layer 113 and upper electrode 112a is covered by the 2nd interlayer dielectric 104.Also have, in Fig. 1, strong dielectric layer 113 and the 1st, the 2nd interlayer insulating film 103,104 have omitted.
Wherein, ferro-electric materials capacitor 110a is made of above-mentioned lower electrode 111a, upper electrode 112a above it and the strong dielectric layer 113 between this lower electrode 111a and the upper electrode.Ferro-electric materials capacitor 110a is configured in the both sides of above-mentioned transistor area 120a respectively.
In addition, between the two lower electrode 111a that above-mentioned transistor area are clipped in the middle in opposite directions, configuration makes it to stride across many transistor area 120a that are aligned to row by a pair of word line 123a1,123a2 that polysilicon constitutes.Wherein, the shape of above-mentioned word line 123a1,123a2 becomes zigzag fashion, make with transistor area 120a in the formation position of contact hole 105a, 105b not overlapping.The both sides of this word line in this each transistor area have formed the transistorized source diffusion zone 122 that constitutes memory cell and have leaked diffusion zone 121.Be positioned at the part of each transistor area top of above-mentioned word line, constituted above-mentioned transistorized grid, being situated between is positioned at the surf zone top of substrate 101 with gate insulating film 102a.The surface of above-mentioned diffusion zone 121,122 and word line 123a1,123a2 is covered by above-mentioned the 1st, the 2nd interlayer dielectric 103,104.
The source diffusion zone 122 of inboard of a pair of word line that is arranged in above-mentioned each transistor 120a is via the contact hole 105b that forms on above-mentioned the 1st, the 2nd dielectric film 103,104, is connected on the bit line 113b that extends along the 2nd direction vertical with above-mentioned the 1st direction D1.In addition, the leakage diffusion zone 121 in the outside that is arranged in a pair of word line of above-mentioned each transistor area 120a is electrically connected on the upper electrode 112a of the ferro-electric materials capacitor 110a corresponding with each transistor area 120a by means of connecting wiring 113a.Promptly, the end of above-mentioned connecting wiring 113a is connected on the above-mentioned upper electrode 112a via the contact hole 104a that forms on above-mentioned the 2nd interlayer dielectric 104, and the other end of above-mentioned connecting wiring 113a is then via being connected at the contact hole 105a that forms on above-mentioned the 1st, the 2nd interlayer dielectric 103,104 Lou on the diffusion zone 121.
Here, above-mentioned the 1st interlayer dielectric 103 is made of the insulating material of NSG (silica system) or BPSG (boron phosphorus doping silica) etc., the material formation that the 2nd interlayer dielectric 104 is waited by for example PSG (mixing phosphor silicon oxide).
In addition, as the strong dielectric material of the strong dielectric layer 113 that constitutes above-mentioned ferro-electric materials capacitor 110a, people know KNO3, PbLa2O3-ZrO2-TiO2 and PbTiO3-PbZrO3 etc.In addition, according to the international disclosed WO93/12542 communique of PCT, people also know be suitable for doing ferroelectric storage device, compare tired extreme little strong dielectric material with PbTiO3-PbZrO3.
In addition, above-mentioned connecting wiring 113a and bit line 113b be make the titanium layer that forms in turn on the substrate with form after aluminium lamination is scribed into figure.Also have, above-mentioned connecting wiring 113a and bit line 113b be the monolayer constructions will of aluminium lamination also.In this case, form after both can having made same aluminium lamination scribe into figure, also can scribe into figure and form by means of different aluminium laminations.
In present embodiment 1, as shown in Figure 3, especially the flat shape of above-mentioned upper electrode 112a is become the size L2 flat shape shorter than the size W2 of the 2nd direction D2 that makes above-mentioned the 1st direction D1.In addition, the area that is configured to upper electrode 112a on the other side in lower electrode 111a becomes littler than the area of above-mentioned lower electrode 111a.Wherein, distance between the 1st side 112a1 of the 1st side 111a1 of above-mentioned lower electrode 111a and adjacent and relative with it upper electrode 112a (below, be referred to as the 1st non-overlapped width) O11, and between the 1st side 112a2 of the 1st side 111a2 of above-mentioned lower electrode 111a and contiguous with it relative upper electrode 112a apart from O12 (below, be referred to as the 2nd non-overlapped width) equate that these the 1st, the 2nd non-overlapped width O11 and O12 have been set at the size W2 of the 2nd direction (Width of the lower electrode) D2 less than above-mentioned upper electrode 112a.
Secondly, illustration effect.
It is identical with the action of existing ferroelectric storage device that the data of the ferroelectric storage device of present embodiment 1 are read action.
In present embodiment 1, in ferroelectric storage device, Jie is with strong dielectric layer 113, has the lower electrode of banded flat shape (cell board electrode) 111a top, long side direction along this lower electrode 111a disposes a plurality of upper electrode 112a, constitute a plurality of ferro-electric materials capacitor 110a, and because above-mentioned upper electrode 112a, the size L2 of the long side direction of lower electrode has become shorter than the size W2 of vertical with it direction, thus can reduce with upper electrode 112a in, produce the lateral section overlapping areas of the strong dielectric layer 113 that quality of materials degenerates and do not reduced the area of upper electrode 112a.Therefore, will reduce discrete as the characteristic of ferro-electric materials capacitor integral body, the flutter that produces along with passing of time also will slow down.
In addition, in this case, because the width L2 in the zone of the influence that the quality of materials that is subjected to the strong dielectric layer of above-mentioned upper electrode 112a is degenerated is narrow, even so make above-mentioned non-overlapped width O11, the O12 stenosis is narrow, also can suppress the discrete or flutter reduction as the characteristic of ferro-electric materials capacitor integral body, the result, can the width W 1 of lower electrode 111a (=W1+O11+O12) do narrowly, can also reduce the profile area of memory cell array.
In addition, in this embodiment 1, since be configured at the contact hole 104a that forms on the upper electrode upper electrode 112a, from its middle position on the position of secund side one side, suppress for not feeding through to the central corresponding part with upper electrode 112a so can degenerate the quality of materials of the strong dielectric layer 113 of the diffusion of impurities that comes from contact hole.
That is, the result becomes to when the formation of contact hole 104a and during the formation of connecting line 113a, and impurity is situated between and invades in the strong dielectric layer 113 with the upper electrode 112a that exposes in this contact hole 104a, makes the material generation deterioration of this strong dielectric layer 113.Though the characteristic of such quality of materials degeneration will causing ferro-electric materials capacitor is discrete, the quality of materials that produced with side one side from lower electrode 111a is degenerated and is lumped together but this quality of materials is degenerated, and becomes to reaching the boundless scope of strong dielectric layer.
To this, shown in above-mentioned embodiment 1, be formed at contact hole 104a on the upper electrode 112a be configured to upper electrode 112a, from the locational ferro-electric materials capacitor of side one side of its middle position deflection one side, can make the generation zone of degenerating because of the quality of materials of the strong dielectric layer 113 that diffusion produced of the impurity that comes from contact hole 104a, stress to be laminated to from the side one of lower electrode 111a and produce the zone that quality of materials degenerates and get on, guarantee not produce the zone that the quality of materials of strong dielectric layer 113 is degenerated in can broad range.Discrete or the performance degradation that so, just can suppress the characteristic of ferro-electric materials capacitor effectively.
In addition, in the foregoing description 1, what illustrate is the situation of doing the width of upper electrode 112a (size among the 2nd direction D2) W2 also shortlyer than its length (size among the 1st direction D1) L2, and still, the width W 2 of above-mentioned upper electrode 112a and length L 2 also can be same sizes.In this case, also can the discrete or flutter as the characteristic of strong dielectric integral body be suppressed for little.
Embodiment 2
Fig. 4 or Fig. 5 are the key diagrams that is used for illustrating the ferroelectric storage device of embodiments of the invention 2, and the plane graph of Fig. 4 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 2.Shown in the plane graph of Fig. 5 is upper electrode and the relation of the position between the lower electrode that constitutes the ferro-electric materials capacitor of the foregoing description 2.
In the memory cell array of the ferroelectric storage device of this embodiment 2, the configuration space of upper electrode in the foregoing description 1, adjacent is become minimum dimension (minimum process size) S2b of the opening figure that on the conductive material layer that constitutes this upper electrode, can form, simultaneously, the configuration of each contact hole of the transistor area among the embodiment 1 is changed.
Below describe in detail.In Fig. 4 and Fig. 5, it is identical with the part of the foregoing description 1 that the label identical with Fig. 1～Fig. 3 represented, 100b is the memory cell array that constitutes ferroelectric storage device.In this memory cell array 100b, in silicon substrate 101 tops, dispose transistor area 120b along the 1st direction D1 with the 2nd vertical with it direction D2 rectangularly, on surf zone this silicon substrate 101, beyond each transistor area, formed device isolation dielectric film 102.In addition, in the respectively both sides of the transistor area 102b of row along the 1st direction D1, the same with the foregoing description 1, lower electrode (the 1st electrode) 111a that has formed strong dielectric layer 113 in its surface is set to cell board electrode.
In addition, upper electrode (the 2nd electrode) 112b that figure forms is scribed into along a plurality of metal films with platinum etc. of above-mentioned the 1st direction D1 configuration in strong dielectric 113 tops on the surface of above-mentioned each lower electrode 111a.Wherein, the configuration space of adjacent upper electrode 112b is become above-mentioned minimum process size S2b.The flat shape of this each upper electrode 112b, identical with the flat shape of the foregoing description 1, become to being the oblong-shaped of long side direction with above-mentioned the 2nd direction D2, and, the area of this upper electrode 112b become for the area than lower electrode 111a little.A plurality of ferro-electric materials capacitor 110b have been constituted with above-mentioned lower electrode 111a and a plurality of upper electrode 112b above it and the strong dielectric layer 113 between this lower electrode and the upper electrode here.Ferro-electric materials capacitor 110b then is disposed at the both sides of above-mentioned transistor area 120b respectively.
Between the two lower electrode 111a that above-mentioned transistor area are clipped in the middle in opposite directions, dispose a pair of word line 123b1, the 123b2 that constitutes by polysilicon, make it to stride across a plurality of transistor area 120b that are arranged in row.Wherein, to have become be a linearity to the flat shape of word line 123b1,123b2.In the both sides of this word line of this each transistor area, the same with the foregoing description 1, form the transistorized source diffusion zone that constitutes memory cell and leaked diffusion zone.Be positioned at the part of each transistor area top of above-mentioned word line, constituted above-mentioned transistorized gate electrode, and Jie is positioned on the surf zone of substrate 101 with gate insulating film.In addition, the surface of above-mentioned diffusion zone and word line, the same with the foregoing description 1, covered by the above-mentioned the 1st and the 2nd interlayer dielectric (not drawing).
The source diffusion zone of inboard that is arranged in a pair of word line of above-mentioned each transistor area 120b is connected on the connecting wiring 113c of the contact hole 105 that forms on above-mentioned the 1st, the 2nd interlayer dielectric, and this connecting wiring 113c goes up the contact hole 105c that forms via the 3rd interlayer dielectric (not drawing) above that, is connected to along on the bit line 115 of the 2nd direction extension vertical with above-mentioned the 1st direction D1.In addition, be arranged in the outer side leakage diffusion zone of a pair of word line of above-mentioned each transistor area 102b,, be electrically connected on the upper electrode 112b of the ferro-electric materials capacitor corresponding with each transistor area by means of connecting wiring 113a.Promptly, the end of above-mentioned connecting wiring 113a is via being connected on the above-mentioned upper electrode 112b at the contact hole 104a that forms on above-mentioned the 2nd dielectric film, the other end of above-mentioned connecting wiring 113b is then via on the contact hole 105a that forms on above-mentioned the 1st, the 2nd interlayer dielectric is connected to Lou diffusion zone.
Wherein, by means of the way of the configuration space of above-mentioned upper electrode 112b being done narrower than the foregoing description 1, in transistor area 120b, the contact hole 120a that leaks on the diffusion zone 121 (with reference to Fig. 2) is configured to be arranged in parallel straight line with contact hole 105b on the source diffusion zone 122 (with reference to Fig. 2) on the 2nd direction.In addition, above-mentioned connecting wiring 113a, 113c, the same with the foregoing description 1, become 2 layers of structure of titanium and aluminium.Above-mentioned bit line 115 usefulness are constituting after the aluminium lamination that forms on the conductor layer upside of these 2 layers of structures etc. is scribed into figure.Other formation is identical with the above embodiments 1, above-mentioned the 1st, the 2nd interlayer dielectric is used with the interlayer dielectric identical materials of the foregoing description 1 and is constituted, and the strong dielectric layer 113 of above-mentioned ferro-electric materials capacitor also uses the strong dielectric material identical with the foregoing description 1 to constitute.
In the embodiments of the invention 2 of such formation, owing to make the configuration space of a plurality of upper electrode 112b that on lower electrode 111a, are arranged in row processing dimension become minimum, so except that the effect of the foregoing description 1, also have the shared chip area of memory cell and this embodiment 1 than the effect that can dwindle about 60%.
Embodiment 3
Fig. 6 and Fig. 7 are the key diagrams that is used for illustrating the ferroelectric storage device of present embodiment 3, and the plane graph of Fig. 6 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 3.Shown in the plane graph of Fig. 7 is upper electrode and the relation of the position between the lower electrode that constitutes the ferro-electric materials capacitor of the foregoing description 3.
In the drawings, 100c is the memory cell array of the ferroelectric storage device of present embodiment 3, and shown in the label identical with Fig. 1～Fig. 3 is the part identical with embodiment 1.
This memory cell 100c has replaced the lower electrode 111a among the embodiment 1, with this lower electrode 111a ratio, have the lower electrode 111c that width (size of the 2nd direction D2) W2 has been enlarged,, disposed two along above-mentioned the 1st direction and listed the electrode 112a of portion in this lower electrode 111c top.
Wherein, in above-mentioned bottom wiring 111c top, configuration space along the upper electrode 112a of the 1st direction D1 configuration, become for the foregoing description 1 in the S2 of the same size of configuration space, and the configuration space of the upper electrode 112a that arranges along the 2nd direction then becomes minimum process size S22c.Other formation is identical with the memory cell 100a of embodiment 1.
In the embodiment 3 that constitutes like this, because the flat shape that is disposed at the upper electrode 112a of lower electrode 111c top is become the size L2 shape littler than the size W2 of Width that makes length direction, so even the width L2 in the zone of the influence that quality of materials above-mentioned upper electrode, that be subjected to the strong dielectric layer is degenerated shortens, distance (non-overlapped width) O11, O12 between the side of above-mentioned lower electrode side and adjacent with it upper electrode narrow down, and still can suppress the discrete or flutter as the characteristic of ferro-electric materials capacitor integral body very lowly.
In addition, because lower electrode 111c is become the wide structure of width, and on this lower electrode 111c, list the electrode 112a of portion along above-mentioned the 1st direction D1 configuration two, so compare with the foregoing description 1, can dwindle and be equivalent to two areas that list the lower electrode of the electrode 112a of portion, can obtain the high density layouts on the substrate of memory cell array.
In addition, in this embodiment, because in lower electrode 111c top, the configuration space of the upper electrode 112a that disposes on its Width becomes processing minimum dimension S22c, so on the result, memory cell array shared area on substrate, with embodiment 1 than dwindling about 10%.
Embodiment 4
Fig. 8 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 4, and this illustrates is the flat shape of upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device.
In the drawings, 112d is the upper electrode of the formation ferro-electric materials capacitor in the present embodiment 4, and this upper electrode 112d is the same with the upper electrode of the foregoing description 1, has disposed a plurality of with the interval of stipulating in lower electrode 111a upper edge the 2nd direction.Wherein, this upper electrode 112d has become 4 jiaos of flat shapes of cutting away and constituting the upper electrode 112a of the rectangular shape in the foregoing description 1.That is, this upper electrode 112d becomes to being 8 angular shape of the lengthwise of long side direction with above-mentioned the 2nd direction D2, and though become for which interior angle all greater than the shapes of 90 degree.Other formation is identical with the foregoing description 1.
In the embodiment 4 that constitutes like this, no matter owing to which interior angle upper electrode 112d is become all is the polygonal shape of spending greater than 90, so can be reduced in carry out above-mentioned upper electrode 112d make figure the time, discrete in the shape at place, this upper electrode bight, therefore, with the generation of the effect of the foregoing description 1 than the discrete or flutter of the characteristic that can also further suppress ferro-electric materials capacitor.In this case, though the capacitance that the area that the area of above-mentioned upper electrode 112d if reduce than some with the corresponding area of embodiment 1, can make the corner cut because of the upper electrode 112a of rectangular shape cause reduces to become to ferro-electric materials capacitor does not almost have effect.
In addition, in the foregoing description 4, though what illustrate is upper electrode after in the memory cell array of the foregoing description 14 angles of upper electrode 112a being cut away, but, this also can be in the memory cell array 100b or 110c of embodiment 2 or 3, cut away the upper electrode at 4 angles of upper electrode 112b and 112a, in this case, also can obtain the effect same with the foregoing description 4.
Embodiment 5
Fig. 9 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 5, and this illustrates is the flat shape of upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device.
In the drawings, 112e is the upper electrode of the formation ferro-electric materials capacitor in the present embodiment 5, this upper electrode 112e is the same with the upper electrode of the foregoing description 1, along with the 1st direction D1 on the lower electrode 111a top of extending, a plurality of along the step pitch configuration with regulation on the 2nd direction vertical with the 1st direction D1.Wherein, the upper electrode 112a of the rectangular shape in this upper electrode 112e and the foregoing description 1 is different, and its flat shape has become to being 6 angular shape of long side direction so that above-mentioned the 1st direction D1 is become the direction D3 of 45 degree.
Promptly, 6 angular shape of this upper electrode 112e by in opposite directions 2 the horizontal edge 112e1s parallel with above-mentioned the 1st direction D1 with 112e2, link to each other with these horizontal edges respectively, parallel with above-mentioned the 2nd direction D2 2 longitudinal edge 112e3 and 112e4 in opposite directions constitutes the hypotenuse 112e6 that couples together between this longitudinal edge 112e4 and the horizontal edge 112e2 and the hypotenuse 112e5 that couples together between this longitudinal edge 112e3 and the horizontal edge 112e1.Wherein, above-mentioned hypotenuse 112e6 becomes to parallel with above-mentioned the 3rd direction D3 with 112e5.Other formation is identical with the foregoing description 1.
In the embodiment 5 that constitutes like this, because the shape of upper electrode 112e is become with to above-mentioned the 1st direction D1, promptly becoming the direction D3 of 45 degree with the long side direction to lower electrode 111a is 6 angular shape of long side direction, so the same with embodiment 1, as can to reduce the material degradation that is subjected on the two side portions parallel zone influence, upper electrode 112e with the 1st direction D1 of strong dielectric layer.
In addition, in this embodiment 5, because Width (the 2nd direction) D2 that the long side direction of upper electrode 112e is decided to be lower electrode becomes the 45 incline direction D3 that spend, so if compare with the foregoing description 1, can be in the lower electrode 111a top of the width dimensions W1 that has determined, the length of lengthening upper electrode 112e.Consequently in present embodiment 5, can be discrete in the characteristic that suppresses ferro-electric materials capacitor or the generation of flutter in, the area that strengthens ferro-electric materials capacitor is to strengthen capacitance.Specifically, with the capacitor of the ferro-electric materials capacitor of embodiment 1 than increasing about 25% to the capacitance of ferro-electric materials capacitor.
Also have, in embodiment 5, even the distance of the hypotenuse in opposite directions of adjacent upper electrode 112e is become for example minimum process size, also will become on part near the dual-side between adjacent upper electrode 112e, lower electrode 111a, form white space 116e.On this white space 116e, for example can dispose the wiring layer or the semiconductor device of polysilicon, therefore, can effectively utilize device area, i.e. Substrate Area in the ferroelectric storage device.
Embodiment 6
Figure 10 is the plane graph that is used to illustrate the ferroelectric storage device of embodiments of the invention 6, and this illustrates is the flat shape of upper electrode that constitutes the ferro-electric materials capacitor of this ferroelectric storage device.
In the drawings, 112f is the upper electrode of the formation ferro-electric materials capacitor in the present embodiment 6, and this upper electrode 112f is the same with the upper electrode of the foregoing description 1, and is in lower electrode 111a top, a plurality of with the step pitch configuration of regulation along the 1st direction D1.Wherein, the upper electrode 112a of the rectangular shape in this upper electrode 112f and the foregoing description 1 is different, has become to being the flat shape F (Figure 10 (c)) that the angle fc of the rectangular shape F0 (Figure 10 (b)) of long side direction scales off formation to the 1st direction D1.
That is, the 6 angular shape F of this upper electrode 112f have in opposite directions grow crosswise limit 112f1 and the 1st horizontal minor face 112f2 parallel with above-mentioned the 1st direction D1, with in opposite directions longitudinal edge 112f3 and the vertical minor face 112f4 parallel with vertical the 2nd direction D2 of above-mentioned the 1st direction.Wherein, this limit 112f1 that grows crosswise that one end has linked up to each other is consistent with horizontal edge a1 and the longitudinal edge b1 of above-mentioned rectangular shape F0 respectively with longitudinal edge 112f3, this horizontal minor face 112f2 links to each other with the above-mentioned other end of growing crosswise limit 112f1 and longitudinal edge 112f3 with a vertical minor face 112f4 end separately, and is positioned at longitudinal edge a2 and the minor face b2 top of above-mentioned rectangular shape F0.Above-mentioned shape F, having the one end links to each other with the other end of above-mentioned vertical minor face 112f4, and the 2nd horizontal minor face 112f5 parallel with the above-mentioned limit 112f1 that grows crosswise, link to each other with the other end of an end with the above-mentioned the 2nd horizontal minor face 112f2, the other end links to each other with the other end of the above-mentioned the 2nd horizontal minor face 112f5, and the obtuse-angulate hypotenuse 112f6 of angle that is constituted with above-mentioned horizontal minor face 112f2.
In this embodiment 6,, arrange the figure of the sort of configuration shown in Figure 10 (c) alternately and it rotation is moved the figure of 180 degree back configurations along above-mentioned the 1st direction D1 in above-mentioned lower electrode 111a top.At this moment, make the limit 112f1 that grows crosswise of a side the 2nd horizontal minor face 112f5 of figure of two adjacent upper electrode 112f and the opposing party's the figure limit that is located along the same line.And the distance between the longitudinal edge of two adjacent upper electrode 112f becomes above-mentioned minimum process size.Other formation is identical with the above embodiments 1.
In the embodiment 6 that constitutes like this, for example upper electrode 112f (upper electrode of the configuration shown in Figure 10 (c)), with the contiguous horizontal minor face 112f2 part of the side 111a2 of lower electrode 111a in, owing to made non-overlapped width O22, interval between the side 111a2 of the horizontal minor face 112f2 of this upper electrode 112f and lower electrode 111a is narrowed down, so can play the effect of the electric capacity of ferro-electric materials capacitor.In addition, upper electrode 112f (upper electrode of the configuration shown in Figure 10 (c)), with the contiguous limit 112f1 part of growing crosswise of the side 111a1 of lower electrode 111a in, owing to made non-overlapped width O21, interval between the side 111a1 of grow crosswise limit 112f1 and lower electrode 111a of this upper electrode 112f is broadened, so can be suppressed at the influence that the quality of materials of the side portion office of the strong dielectric layer that this lower electrode 111a top forms is degenerated, make it not reach in the ferro-electric materials capacitor and go.Therefore, have the generation of the discrete or flutter of the characteristic that can suppress ferro-electric materials capacitor, the area that can strengthen ferro-electric materials capacitor simultaneously strengthens the effect of capacitance.
In addition, in this embodiment 6, ferro-electric materials capacitor is not to arrange point-blank, but be configured to how many indentations, so can improve the layout of memory cell array, be the degree of freedom of the configuration between memory transistor and the ferro-electric materials capacitor, and then, the degree of freedom of the configuration of bit line or word line can be improved.
In addition, in this embodiment 6, distance upper electrode 112f, that become between the side of short more then the 1st horizontal minor face 112f2 and lower electrode 111a in the length of the 1st horizontal minor face 112f2 adjacent with the side of lower electrode 111a is just short more, therefore, can suppress to make the discrete or difficult generation of flutter of characteristic of ferro-electric materials capacitor, simultaneously, can increase capacitance.
Also have, in above-mentioned the 6th embodiment, adopting the interior angle in the flat shape of upper electrode 112f is that cut away at 90 4 angles spending, makes the ways of its interior angle greater than 90 degree, also can influence capacitance ground hardly and further reduce the discrete of characteristic, make flutter more be difficult to take place.
In addition, in the foregoing description 6, also has following effect: the zone between the horizontal edge of the upper electrode 112f that vertical minor face 112f4 is close to each other in opposite directions and the side of lower electrode 111a, promptly by among the folded white space 116f of the side of grow crosswise limit 112f1 and the opposing party's thereof of the side of this two upper electrode 112f the 2nd horizontal minor face 112f5 and lower electrode 111a, can dispose such as the wiring layer or the semiconductor device of polysilicon, thereby can effectively utilize device area.
Figure 11 shows above-mentioned white space 116f is effectively utilized formation into the memory cell array 100f of the configuring area of the polysilicon layer that constitutes word line.
In this memory cell array 100f, it is that growing crosswise of long side direction is square that transistor area 120f becomes with the 1st direction D1, and the contact hole 105a on the leakage diffusion zone among each transistor area 120f is configured on the straight line parallel with the 1st direction D1 with contact hole 105b on the diffusion zone of source.Both sides at the transistor area 120f that arranges along above-mentioned the 1st direction D1 dispose a pair of word line 123f1 and 123f2 along the 1st direction.Above-mentioned word line 123f1 and 123f2 have source that lays respectively at above-mentioned each transistor area 120f and grid part 123f11 and the 123f22 that leaks the formation gate electrode between the diffusion zone.This grid part 123f11 and 123f22 and above-mentioned word line form an integral body, this word line and grid part between the coupling part and the positive following part of the white space 116f that is configured in above-mentioned lower electrode 111a of part nearby on.
Usually, the part that constitutes the ferro-electric materials capacitor of lower electrode 111a should be smooth, can not dispose other member of formation at the downside of this part, but, in present embodiment 6, in the part beyond positive bottom lower electrode 111a, upper electrode 112f, but can dispose for example part of word line 123f1 and 123f2 as described above, therefore, just can effectively utilize device area, i.e. the occupied area of the memory cell array on substrate.
In addition, except that the said embodiment 1～6 in top, realization also is the formation of the memory cell array that they combine possible.
Also have, in the above-described embodiments, structure as ferro-electric materials capacitor, though what enumerate is the structure that constitutes in the memory cell array of ferroelectric storage device, but the structure that is shown in the ferro-electric materials capacitor among each embodiment also can be applied to go in the memory cell array circuit in addition.
Figure 12 and Figure 13 are the plane graphs that is used to illustrate the ferroelectric storage device of embodiments of the invention 7, and the plane graph of Figure 12 shows the memory cell array of the ferroelectric storage device that constitutes embodiments of the invention 7.Shown in the plane graph of Figure 13 is upper electrode and the relation of the position between the lower electrode that constitutes the ferro-electric materials capacitor in the said memory cells array.
In the drawings, 100g is the memory cell array that constitutes the ferroelectric storage device of this embodiment 7.In this memory cell array 100g, the shape of upper electrode 112g is become the shape of having put otch 112g1 from the middle body of the both sides of the 2nd direction D2 of the upper electrode 112b along the foregoing description 2 into, other formation is the same with the foregoing description 2.
In the embodiment 7 that constitutes like this, with above-mentioned otch 112g1, just can prevention to a certain degree degenerate, feed through in the part corresponding and go with the middle body of upper electrode 112a because of the quality of materials that the diffusion of impurities that comes from the contact hole 104a that forms in upper electrode 112a top produces.The generation zone that the quality of materials that promptly can prevent to come from the diffusion of impurities of the contact hole 104a that forms in the upper electrode top and produce is degenerated can guarantee to do the zone that the quality of materials that does not produce the strong dielectric layer is degenerated roomyly to the middle body one side expansion of upper electrode 112a.Discrete or the performance degradation of characteristic that so, just can suppress ferro-electric materials capacitor effectively.
As mentioned above, if adopt the semiconductor device of the 1st aspect of the present invention, be long side direction then because have with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, and the flat shape of the 2nd electrode become with above-mentioned the 1st direction on size and the flat shape that equates of the size on above-mentioned the 2nd direction, or the flat shape shorter of the size on above-mentioned the 1st direction than the size on above-mentioned the 2nd direction, so be positioned at along the zone of the side of the 1st electrode that the whole shared ratio for the 2nd electrode reduces in above-mentioned the 2nd electrode, therefore, ferro-electric materials capacitor just will become the structure of the influence of degenerating for the quality of materials that does not subject on the corresponding zone of the lateral section with the 1st electrode of above-mentioned strong dielectric layer.The result is that it is discrete to have the characteristic that can suppress ferro-electric materials capacitor, and can be so that be difficult to produce the effect of flutter.
In addition, in this case, the area that does not need to dwindle the 2nd electrode just can reduce the distance between the side of the side of the 1st electrode and adjacent with it the 2nd electrode, reduces the effect that just can reduce the layout area of memory cell array thereby have the capacitance that can not cause strong dielectric electric capacity.
If adopt the semiconductor device of the 2nd aspect of the present invention, then aspect the 1st in the described semiconductor device, above-mentioned the 2nd electrode arrangement for arrange along the 1st direction a plurality of make it with above-mentioned the 1st electrode in opposite directions, and the 2nd adjacent interelectrode configuration space is set at the minimum process size of the opening figure of the conductive material layer that constitutes the 2nd electrode, so can reduce to carry the layout area of the memory cell array of a plurality of ferro-electric materials capacitors.
If adopt the semiconductor device of the 3rd aspect of the present invention, then because aspect the 1st in the described semiconductor device, the flat shape of the 2nd electrode is made polygonal, interior angle in the flat shape of the 2nd electrode has all been made greater than 90 degree, so just can carry out the processing of the 2nd electrode with better repeatability, therefore, the effect that has the discrete or flutter of the characteristic that can further suppress ferro-electric materials capacitor.
If adopt the semiconductor device of the 4th aspect of the present invention, be long side direction then owing to having with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode with the strong dielectric layer in the 1st electrode top and constitute a plurality of ferro-electric materials capacitors, and the 2nd electrode become in length and breadth the rectangular configuration of arranging, so the result becomes the number for the ferro-electric materials capacitor that increases the unit are on the memory cell array, having the high density layouts that makes the memory cell array on substrate becomes possible effect.
If adopt the semiconductor device of the 5th aspect of the present invention, then because aspect the 4th in the described semiconductor device, above-mentioned the 2nd electrode is made it to arrange a plurality of along the 1st direction opposite to each other with above-mentioned the 1st electrode, and the 2nd adjacent interelectrode configuration space is set at the minimum process size of the opening figure of the conductive material that constitutes the 2nd electrode, so can reduce to carry the layout area of the memory cell array of a plurality of ferro-electric materials capacitors.
If adopt the semiconductor device of the 6th aspect of the present invention, be long side direction then owing to having with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, and to become the flat shape of the 2nd electrode with the direction between above-mentioned the 1st direction and above-mentioned the 2nd direction be the flat shape of long side direction, so be positioned at along the zone of the side of the 1st electrode that the whole shared ratio for the 2nd electrode reduces in above-mentioned the 2nd electrode, therefore, ferro-electric materials capacitor just will become the structure of the influence of degenerating for the quality of materials that does not subject on the corresponding zone of the lateral section with the 1st electrode of above-mentioned strong dielectric layer.The result has the characteristic that can suppress ferro-electric materials capacitor to disperse, and can be so that be difficult to produce the effect of flutter.
In addition, in this case, the area that does not need to dwindle the 2nd electrode just can reduce the distance between the side of the side of the 1st electrode and adjacent with it the 2nd electrode, reduces the effect that just can reduce the layout area of memory cell array thereby also have the capacitance that can not cause strong dielectric electric capacity.
If adopt the semiconductor device of the 7th aspect of the present invention, then because aspect the 6th in the described semiconductor device, the flat shape of the 2nd electrode is made polygonal, interior angle in the flat shape of the 2nd electrode has all been made greater than 90 degree, so just can carry out the processing of the 2nd electrode with better repeatability, therefore, the effect that has the discrete or flutter of the characteristic that can further suppress ferro-electric materials capacitor.
If adopt the semiconductor device of the 8th aspect of the present invention, be long side direction then owing to having with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, with above-mentioned the 1st electrode parallel the 2nd side of the 1st direction from recently and the length of the 1st side of the 2nd electrode in opposite directions, make than 2nd side parallel with the 1st direction of above-mentioned the 1st electrode from recently and the length of the 2nd side of the 2nd electrode in opposite directions also long, distance from the 1st side of the 1st side to the 1 electrode of the 2nd electrode, become also bigger than distance from the 1st side of the 2nd side to the 1 electrode of the 2nd electrode, so, it is the 1st of the 2nd electrode that the result becomes, a side long in the 2nd side is far away from the side of the 1st electrode, and ferro-electric materials capacitor becomes and is difficult to be subjected to the influence of the quality of materials degeneration on the corresponding zone of the lateral section with the 1st electrode of above-mentioned strong dielectric layer.In addition, a side of weak point becomes near from the side of the 1st electrode within the 1st, the 2nd side of the 1st electrode, and the result becomes to increasing the capacitance of ferro-electric materials capacitor.Consequently, have the discrete or flutter of the characteristic that can suppress ferro-electric materials capacitor, the area that strengthens ferro-electric materials capacitor increases the effect of capacitance.
In addition, in the present invention, becoming is easy to ferro-electric materials capacitor is configured to zigzag, therefore, can improve simply memory array layout, i.e. the degree of freedom of the configuration between memory transistor and the ferro-electric materials capacitor, and can improve the configuration degree of freedom of bit line or word line.
If adopt the semiconductor device of the 9th aspect of the present invention, then because aspect the 8th in the described semiconductor device, the flat shape of the 2nd electrode is made polygonal, interior angle in the flat shape of the 2nd electrode has all been made greater than 90 degree, so just can carry out the processing of the 2nd electrode with better repeatability, therefore, the effect that has the discrete or flutter of the characteristic that can further suppress ferro-electric materials capacitor.
If adopt the semiconductor device of the 10th aspect of the present invention, owing to possess a plurality of memory cell that constitute by ferro-electric materials capacitor and memory transistor respectively, multiple bit lines, many word lines and sense amplifier, having with the 1st direction D1 is long side direction, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, and the flat shape of the 2nd electrode become with above-mentioned the 1st direction on size and the flat shape that equates of the size on above-mentioned the 2nd direction, or the flat shape shorter of the size on above-mentioned the 1st direction than the size on above-mentioned the 2nd direction, so be positioned at along the zone of the side of the 1st electrode that the whole shared ratio for the 2nd electrode reduces in above-mentioned the 2nd electrode, therefore, ferro-electric materials capacitor just will become the structure of the influence of degenerating for the quality of materials that does not subject on the corresponding zone of the lateral section with the 1st electrode of above-mentioned strong dielectric layer.The result has the characteristic that can suppress ferro-electric materials capacitor to disperse, and can be so that be difficult to produce the effect of flutter.
In addition, in this case, do not need to dwindle the area of the 2nd electrode, just can reduce the distance between the side of the side of the 1st electrode and adjacent with it the 2nd electrode, reduce the effect that just can reduce the layout area of memory cell array thereby have the capacitance that can not cause strong dielectric electric capacity.
If adopt the semiconductor device of the 11st aspect of the present invention, be long side direction then owing to having with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, and being offset to along the position of the side of a side of the 1st direction of above-mentioned the 1st electrode from the middle position of its 2nd electrode of dielectric film that has formed the surface that covers the 2nd electrode formed contact hole, go so the area coincidence of generating material quality degradation of the strong dielectric layer that diffusion produced of the impurity that comes from contact hole is produced on the zone that quality of materials degenerates to the 1st side one side, can guarantee not produce the zone of strong dielectric material quality degradation largo.Discrete or the performance degradation of characteristic that therefore, can suppress ferro-electric materials capacitor effectively.
If adopt the semiconductor device of the 12nd aspect of the present invention, be long side direction then owing to having with the 1st direction D1, when with 2nd direction vertical being the 1st electrode of banded flat shape of Width with the 1st direction, also be situated between and dispose the 2nd electrode formation ferro-electric materials capacitor in the 1st electrode top with the strong dielectric layer, and the 2nd electrode become make its integral body be cut the structure that into otch is divided into a plurality of electrodes parts by side one side of its regulation, via contact hole wiring is connected on a part of electrode in the above-mentioned a plurality of electrode part, so, can stop the diffusion of the impurity that comes from the contact hole that on the 2nd electrode, forms in a way and the quality of materials of the strong dielectric layer that produces is degenerated to involve in its broad scope and gone with above-mentioned otch.That is, can guarantee not take place the zone that the quality of materials of strong dielectric is degenerated commodiously.Discrete or the deterioration in characteristics of characteristic that therefore, can suppress ferro-electric materials capacitor effectively.
Claims (12)
1, a kind of semiconductor device is characterized in that:
Possess:
Have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction;
Be configured to and the 1st electrode a plurality of the 2nd electrodes in opposite directions, have size and equal flat shape or the flat shape shorter of the size on above-mentioned the 1st direction of the size on above-mentioned the 2nd direction on above-mentioned the 1st direction than the size on above-mentioned the 2nd direction; And
Be configured in the strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode,
Constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode,
Above-mentioned a plurality of ferro-electric materials capacitors corresponding to above-mentioned the 1st electrode become the row configuration along above-mentioned the 1st direction with being adjacent to each other.
2, semiconductor device according to claim 1 is characterized in that: above-mentioned the 2nd electrode is to make the conductive material layer of regulation scribe into figure and the electrode that forms,
The configuration space of the 2nd electrode that this is adjacent is the minimum dimension of the opening figure that can form on above-mentioned conductive material.
3, semiconductor device according to claim 1 is characterized in that: the flat shape of above-mentioned the 2nd electrode is four polygonals after the chamfering of angle, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
4, semiconductor device according to claim 1 also possesses: each of above-mentioned a plurality of ferro-electric materials capacitors be connected to a plurality of memory transistors each formation, be arranged in rectangular a plurality of memory cell; Be used to drive the unit printed line of this ferro-electric materials capacitor; Each that constitutes with above-mentioned a plurality of memory cell is listed as corresponding multiple bit lines; Each row many word lines corresponding, that be used to select above-mentioned memory transistor with above-mentioned a plurality of memory cell formations; And be connected on the above-mentioned bit line, amplify the sense amplifier of the data-signal on the bit line of stipulating.
5, semiconductor device according to claim 1 also possesses:
Cover the dielectric film of the surface formation of above-mentioned the 2nd electrode, have on the surface of the 2nd electrode the contact hole that forms from the position that its central position deviation comes.
6, semiconductor device according to claim 1 also possesses:
Cover the dielectric film of the surface formation of above-mentioned the 2nd electrode, have the contact hole of the 2nd electrode relatively,
Above-mentioned the 2nd electrode constitutes and makes it all, is divided into a plurality of electrodes structure partly by the breach that excises from side one side of its regulation,
Above-mentioned contact hole is arranged on a part of electrode of a plurality of electrode parts that constitute the 2nd electrode.
7, semiconductor device according to claim 1 is characterized in that:
Above-mentioned the 2nd electrode is littler than the width of the 2nd electrode on the 1st direction at the configuration space on the 1st direction.
8, a kind of semiconductor device is characterized in that:
Possess:
Have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction;
With the 1st electrode a plurality of the 2nd electrodes in opposite directions, above-mentioned the 2nd electrode has size and equal flat shape or the flat shape shorter than the size on above-mentioned the 2nd direction of the size on above-mentioned the 1st direction of the size on above-mentioned the 2nd direction on above-mentioned the 1st direction; And
Be configured in the strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode,
Constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode,
It is rectangular to be with above-mentioned the 1st direction and the 2nd direction that column direction and line direction are configured to respectively corresponding to above-mentioned a plurality of ferro-electric materials capacitors of above-mentioned the 1st electrode, makes the 2nd electrode of the ferro-electric materials capacitor arranged along this column direction be adjacent to each other.
9, a kind of semiconductor device is characterized in that:
Possess:
Have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction;
Be configured to and the 1st electrode in opposite directions and have with a plurality of the 2nd electrodes of the direction between the 1st direction and the 2nd direction for the flat shape of its long side direction; And
Be configured in the strong dielectric layer between above-mentioned the 1st electrode and above-mentioned the 2nd electrode,
Constitute a plurality of ferro-electric materials capacitor independent of each other with above-mentioned the 1st electrode, strong dielectric layer and a plurality of the 2nd electrode,
Above-mentioned a plurality of ferro-electric materials capacitors corresponding to above-mentioned the 1st electrode become the row configuration along above-mentioned the 1st direction with being adjacent to each other.
10, semiconductor device according to claim 9 is characterized in that: the flat shape of above-mentioned the 2nd electrode is a polygonal, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
11, a kind of semiconductor device is characterized in that:
Possess:
Have along the 1st direction and extend and be the 1st electrode of the flat shape of Width with the 2nd direction vertical with the 1st direction;
Be configured to the 1st electrode in opposite directions and have the 2nd electrode of and in opposite directions 1st side the most contiguous and and in opposite directions 2nd side the most contiguous with the 2nd side parallel with the 1st direction of the 1st electrode with the 1st side parallel with the 1st direction of the 1st electrode; And
Be clipped in the strong dielectric layer between above-mentioned the 1st electrode and the 2nd electrode,
And, constitute ferro-electric materials capacitor with above-mentioned the 1st, the 2nd electrode and this two interelectrode strong dielectric layer,
Do the length of the 1st side of above-mentioned the 2nd electrode also longlyer, and make distance till the 1st side of the 1st side to the 1 electrode of the 2nd electrode do to become also bigger than the distance till the 1st side of the 2nd side to the 1 electrode of the 2nd electrode than its 2nd side.
12, semiconductor device according to claim 11 is characterized in that: the flat shape of above-mentioned the 2nd electrode is the polygonal shape, and the size of the interior angle in the flat shape of the 2nd electrode is all greater than 90 degree.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP98267/1996 | 1996-04-19 | ||
| JP98267/96 | 1996-04-19 | ||
| JP9826796 | 1996-04-19 |
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| CN1194723A CN1194723A (en) | 1998-09-30 |
| CN1142587C true CN1142587C (en) | 2004-03-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB971906068A Expired - Fee Related CN1142587C (en) | 1996-04-19 | 1997-04-18 | Semiconductor device |
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| US (2) | US6163043A (en) |
| EP (1) | EP0836226A4 (en) |
| JP (1) | JP4386210B2 (en) |
| KR (1) | KR100303682B1 (en) |
| CN (1) | CN1142587C (en) |
| TW (1) | TW322635B (en) |
| WO (1) | WO1997040531A1 (en) |
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| TW322635B (en) * | 1996-04-19 | 1997-12-11 | Matsushita Electron Co Ltd | |
| US6452776B1 (en) * | 2000-04-06 | 2002-09-17 | Intel Corporation | Capacitor with defect isolation and bypass |
| JP3901432B2 (en) * | 2000-08-22 | 2007-04-04 | セイコーエプソン株式会社 | Memory cell array having ferroelectric capacitor and manufacturing method thereof |
| TWI224578B (en) * | 2001-01-18 | 2004-12-01 | Ibm | Fabrication of silicon micro mechanical structures |
| JP2002270788A (en) * | 2001-03-14 | 2002-09-20 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2002324852A (en) * | 2001-04-26 | 2002-11-08 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| US20030001188A1 (en) * | 2001-06-27 | 2003-01-02 | Nakagawa Osamu Samuel | High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems |
| JP2004047943A (en) | 2002-03-20 | 2004-02-12 | Fujitsu Ltd | Semiconductor device |
| DE10308927A1 (en) * | 2003-02-28 | 2004-09-16 | Infineon Technologies Ag | Integrated semiconductor circuit with a transistor and with a conductor track |
| EP1793367A3 (en) * | 2005-12-02 | 2009-08-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US20100308390A1 (en) * | 2007-12-21 | 2010-12-09 | Nxp B.V. | Memory cell suitable for dram memory |
| KR101037501B1 (en) * | 2008-10-30 | 2011-05-26 | 주식회사 하이닉스반도체 | High integrated semiconductor memory device |
| JP6142710B2 (en) * | 2013-07-24 | 2017-06-07 | 富士通セミコンダクター株式会社 | Semiconductor device and design method thereof |
| TWI550830B (en) * | 2014-05-23 | 2016-09-21 | 旺宏電子股份有限公司 | Semiconductor structure and method for manufacturing the same |
| CN105226061B (en) * | 2014-06-10 | 2018-04-24 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacture method |
| US9252155B2 (en) * | 2014-06-20 | 2016-02-02 | Macronix International Co., Ltd. | Memory device and method for manufacturing the same |
| CN110164489B (en) * | 2019-05-28 | 2021-05-07 | 珠海创飞芯科技有限公司 | Correlation method and system for optimizing Nor Flash memory array area |
| CN110349960B (en) * | 2019-07-08 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | Layout structure of embedded flash memory, embedded flash memory and forming method thereof |
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| WO1992006498A1 (en) * | 1990-09-28 | 1992-04-16 | Seiko Epson Corporation | Semiconductor device |
| JPH04144282A (en) * | 1990-10-05 | 1992-05-18 | Seiko Epson Corp | Semiconductor device |
| JPH04225510A (en) * | 1990-12-27 | 1992-08-14 | Tosoh Corp | Capacitor array |
| JPH0590489A (en) * | 1991-09-30 | 1993-04-09 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPH05182857A (en) * | 1991-12-27 | 1993-07-23 | Rohm Co Ltd | Thin film capacitor |
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| JP3239445B2 (en) * | 1992-06-09 | 2001-12-17 | セイコーエプソン株式会社 | Dielectric element, method of manufacturing the same, and semiconductor memory device |
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| JPH0669418A (en) * | 1992-08-21 | 1994-03-11 | Fujitsu Ltd | Semiconductor device |
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1997
- 1997-04-18 TW TW086105036A patent/TW322635B/zh not_active IP Right Cessation
- 1997-04-18 US US08/981,265 patent/US6163043A/en not_active Expired - Fee Related
- 1997-04-18 EP EP97917434A patent/EP0836226A4/en not_active Withdrawn
- 1997-04-18 JP JP53791597A patent/JP4386210B2/en not_active Expired - Lifetime
- 1997-04-18 KR KR1019970709552A patent/KR100303682B1/en not_active IP Right Cessation
- 1997-04-18 WO PCT/JP1997/001347 patent/WO1997040531A1/en not_active Application Discontinuation
- 1997-04-18 CN CNB971906068A patent/CN1142587C/en not_active Expired - Fee Related
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2000
- 2000-08-11 US US09/637,723 patent/US6420743B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW322635B (en) | 1997-12-11 |
| EP0836226A4 (en) | 2001-09-05 |
| JP4386210B2 (en) | 2009-12-16 |
| EP0836226A1 (en) | 1998-04-15 |
| US6420743B1 (en) | 2002-07-16 |
| CN1194723A (en) | 1998-09-30 |
| KR19990028241A (en) | 1999-04-15 |
| KR100303682B1 (en) | 2001-11-02 |
| WO1997040531A1 (en) | 1997-10-30 |
| US6163043A (en) | 2000-12-19 |
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