CN110349960B - Layout structure of embedded flash memory, embedded flash memory and forming method thereof - Google Patents
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a layout structure of an embedded flash memory, the embedded flash memory and a forming method thereof, wherein the layout structure of the embedded flash memory comprises the following steps: a word line layout having a plurality of word line patterns; the block layout is provided with a plurality of block patterns, the word line patterns and the block patterns are provided with overlapping regions, and the overlapping regions are Z-shaped; and the contact hole layout is provided with a plurality of contact hole patterns, every two contact hole patterns are overlapped with one block pattern, and the two contact hole patterns are respectively positioned at two sides of the overlapped region. According to the invention, the overlapping area is Z-shaped, so that the process window of the contact hole is increased, and the occurrence of abnormal connection between the contact hole and the control gate of the adjacent word line is reduced.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a layout structure of an embedded flash memory, the embedded flash memory and a forming method thereof.
Background
Flash memory (flash) is a safe and fast memory bank, and becomes the most main carrier of data and programs in embedded systems due to a series of advantages of small volume, large capacity, low cost, no loss of power-down data and the like.
In recent years, with the rapid development of the intelligent electronic product market, the use of various MCUs (micro controller units) and socs (System-on-Chip) has been advanced to various aspects of daily life such as automotive electronics, industrial control, and medical products. And the high-performance MCU or SoC product cannot be supported by an embedded flash (E-flash) kernel. Embedded flash memory has an increasing dominance on SoC designs, both in terms of chip area, system performance and power consumption, and in terms of manufacturing yield and design cycle. Embedded flash combines existing flash with logic modules from a physical or electrical perspective, providing more versatile performance.
When forming contact holes on control gates on both sides of a word line, a problem of bridging between a plug formed in the contact hole and a control gate of an adjacent word line is easily caused due to limitation of a photolithography capability. Therefore, how to increase the process window of the contact hole and avoid the problem that the contact hole cannot cause abnormal connection between the contact hole and the control gates on two sides of the adjacent word line when the contact hole is subjected to position deviation under the influence of photoetching alignment accuracy becomes a problem which cannot be ignored.
Disclosure of Invention
The invention aims to provide a layout structure of an embedded flash memory, the embedded flash memory and a forming method thereof, and aims to solve the problem that in the prior art, due to the influence of alignment precision, the position of a contact hole is deviated, so that the connection between the contact hole and control gates on two sides of adjacent word lines is abnormal.
In order to solve the above problems, the present invention provides a layout structure of an embedded flash memory, including:
a word line layout having word line patterns;
the block layout is provided with a block pattern, the word line pattern and the block pattern are provided with an overlapping region, and the shape of the overlapping region is Z-shaped;
a contact hole layout having a contact hole pattern;
and each two contact hole patterns are overlapped with one block pattern, and the two contact hole patterns are respectively positioned at two sides of the overlapped area.
Optionally, each of the word line patterns has a first portion, a second portion and a third portion, the first portion and the third portion are connected to both ends of the second portion, the second portion is located in the overlapping area, and the second portion has a zigzag shape.
Further, the line width of the second portion of the word line pattern is 0.18 μm to 0.25 μm.
Furthermore, the line widths of the ends of the first portion and the third portion of the word line pattern, which are respectively connected with the second portion, are both 0.18 μm to 0.25 μm.
Further, the word line pattern includes:
a plurality of first word line patterns periodically arranged in a direction perpendicular to an extending direction thereof;
a plurality of second word line patterns periodically arranged in a direction perpendicular to an extending direction thereof, and the extending direction of the first and second word line patterns is the same; and
the first word line pattern and the second word line pattern are arranged adjacently, and the shape of the second part of the first word line pattern is a mirror image of the shape of the second part of the second word line pattern.
Furthermore, the second portion of the first word line pattern is offset from the second portion of the second word line pattern.
Further, a line width at a first portion of the second word line pattern adjacent to a second portion of the first word line pattern is 0.18 to 0.25 μm; a line width at a third portion of the first word line pattern adjacent to the second portion of the second word line pattern is 0.18 to 0.25 μm.
Optionally, a distance between the contact hole pattern and the adjacent word line pattern is 0.19 μm to 0.25 μm.
On the other hand, the invention also provides a method for forming the embedded flash memory, which comprises the following steps:
providing a semiconductor substrate;
forming a word line using a first mask, wherein the first mask has a word line pattern;
forming a block by using a second photomask, wherein the block and the word line have an overlapping area, and the shape of the word line in the overlapping area is Z-shaped, and the second photomask has a block pattern; and
and forming contact holes by using a third photomask, wherein two contact holes are formed in each block, the two contact holes are respectively positioned at two sides of the word line, and plugs are formed in the contact holes, and the third photomask is provided with a contact hole pattern.
Optionally, the semiconductor substrate includes a base, and an oxide layer, a floating gate layer, a dielectric layer, a control layer and a passivation layer sequentially formed on the base.
Further, the step of forming the word line includes:
forming a first photoresist layer on the semiconductor substrate;
patterning the first photoresist layer by using a first photomask to form a patterned first photoresist layer; and
taking the first patterned photoresist layer as a mask, sequentially etching the passivation layer, the control gate layer, the dielectric layer and the floating gate layer and exposing the oxide layer to form a word line; and
and removing the first photoresist layer.
Further, the step of forming the block includes:
forming a second photoresist layer on the semiconductor substrate;
patterning the second photoresist layer by using a second photomask to form a patterned second photoresist layer; and
taking the patterned second photoresist layer as a mask, sequentially etching the passivation layer, the control gate layer, the dielectric layer, the floating gate layer and the oxide layer to expose the substrate to form a block; and
and removing the second photoresist layer.
Further, the step of forming the plug includes:
forming a third photoresist layer on the semiconductor substrate;
patterning the third photoresist layer by using a third photomask to form a patterned third photoresist layer;
etching the passivation layer and exposing the control gate by taking the patterned third photoresist layer as a mask to form a contact hole;
filling metal in the contact hole to form a plug; and
and removing the third photoresist layer.
Further, the word line pattern has a first portion, a second portion and a third portion, the first portion and the third portion are connected to both ends of the second portion, the second portion is located in the overlapping area, the second portion is zigzag-shaped, and a line width of the second portion of the word line pattern is 0.18 μm to 0.25 μm.
In another aspect, the invention further provides an embedded flash memory, which is prepared by the method for forming the embedded flash memory.
Compared with the prior art, the method has the following beneficial effects:
the invention provides a layout structure of an embedded flash memory, the embedded flash memory and a forming method thereof, wherein the layout structure of the embedded flash memory comprises the following steps: a word line layout having a plurality of word line patterns; the block layout is provided with a plurality of block patterns, the word line patterns and the block patterns are provided with overlapping regions, and the overlapping regions are Z-shaped; and the contact hole layout is provided with a plurality of contact hole patterns, every two contact hole patterns are overlapped with one block pattern, and the two contact hole patterns are respectively positioned at two sides of the overlapped region. The invention increases the process window of the contact hole by the shape of the overlapping area in a Z shape;
furthermore, the line width of the second part of the word line pattern is adjusted, the distance between the block pattern and the adjacent word line pattern is increased, the process window of the contact hole can be further increased, and the occurrence of abnormal connection between the contact hole and the control gates on two sides of the adjacent word line is reduced.
Drawings
FIG. 1 is a layout diagram of a layout structure of an embedded flash memory;
fig. 2 is a schematic structural diagram of a layout structure of an embedded flash memory according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a method for forming an embedded flash memory according to an embodiment of the invention.
Description of reference numerals:
10' -word line pattern; 20' -block pattern; 21' -an overlapping region; 30' -contact hole pattern;
10-word line pattern; 11-first word line pattern; 12-a second wordline pattern; 10 a-a first part; 10 b-a second part; 10 c-a third portion;
20-block pattern; 21-an overlap region;
30-contact hole pattern.
Detailed Description
The existing embedded flash memory adopts a simple stacked gate structure, for example, the existing embedded flash memory comprises a floating gate layer and a control gate layer which are sequentially overlapped, and a word line which divides the floating gate layer and the control gate layer into two floating gates and two control gates along the thickness direction, wherein the word line is positioned between the two floating gates and the two control gates, and contact holes are formed above the two control gates. The contact hole is used for forming a bit line for connecting the control gate and the storage region of the embedded flash memory and a plug for realizing the electric connection of a peripheral circuit.
Fig. 1 is a schematic structural diagram of a layout structure of an embedded flash memory. As shown in fig. 1, the layout structure of the embedded flash memory includes a control gate pattern, a word line pattern 10 ' and a block pattern 20 ', the word line pattern 10 ' covers the control gate pattern, the word line pattern 10 ' and the block pattern 20 ' are arranged in a cross manner, an overlapping region 21 ' of the word line pattern 10 ' and the block pattern 20 ' is formed, and the shape of the overlapping region 21 ' is, for example, a straight bar shape. Each of the block patterns 20 ' has two contact hole patterns 30 ', and the two contact hole patterns 30 ' are respectively located at both sides of the overlap region 21 ', and at this time, a distance between the contact hole pattern 30 ' and an adjacent control gate pattern is small, for example, 0.13 μm. Therefore, in the actual process, under the influence of the photoetching alignment precision, the position of the contact hole is easy to deviate from the block, and the problem of abnormal connection between the contact hole and the adjacent block or the control gates at two sides of the adjacent word line is caused.
Based on the research, the invention provides a layout structure of an embedded flash memory, the embedded flash memory and a forming method thereof, wherein the layout structure of the embedded flash memory comprises word line patterns and block patterns, the word line patterns and the block patterns are arranged in a crossed manner to form an overlapping area of the block patterns and the word line patterns, the overlapping area is in a Z shape, each block pattern is provided with two contact hole patterns, and the two contact hole patterns are respectively positioned at two sides of the overlapping area. The invention increases the process window of the contact hole by the shape of the overlapping area in a Z shape;
furthermore, the line width of the second part of the word line pattern is adjusted, the distance between the block pattern and the adjacent word line pattern is increased, the process window of the contact hole can be further increased, and the occurrence of abnormal connection between the contact hole and the control gates on two sides of the adjacent word line is reduced.
The layout structure of an embedded flash memory, the embedded flash memory and the forming method thereof according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 2 is a schematic diagram of a layout structure of the embedded flash memory according to this embodiment. As shown in fig. 2, the layout structure of the embedded flash memory provided in this embodiment has a storage region, where the layout structure of the embedded flash memory in the storage region includes a word line layout, a block layout, and a contact hole layout, where the word line layout has a plurality of word line patterns, and each word line pattern may form a word line, the block layout has a plurality of block patterns 20, and the block patterns 20 and the word line patterns 10 have an overlap region 21.
Each of the overlapping regions 21 divides the word line pattern 10 into three portions, namely, a first portion 10a, a second portion 10b and a third portion 10c, the second portion 10b is located in the overlapping region 21, the first portion 10a and the third portion 10c are respectively connected to two ends of the second portion 10b, and the shape of the overlapping region 21 is, for example, zigzag, that is, the shape of the second portion 10b is, for example, zigzag, which increases a process window for forming contact holes on a block during a manufacturing process. The line width of the overlap region 21 is 0.18 to 0.25 μm, that is, the line width of the second portion 10b of the word line pattern 10 is 0.18 to 0.25 μm. The first portion 10a and the third portion 10c of the word line pattern 10 are substantially straight, and the line widths of the end portions of the first portion 10a and the third portion 10c of the word line pattern 10, which are respectively connected to the second portion 10b, are both 0.18 μm to 0.25 μm, which is beneficial to increasing the distance between the second portion 10b and the adjacent word line pattern 10.
The word line pattern 10 includes, for example, a plurality of first word line patterns 11 and second word line patterns 12, the first word line patterns 11 are periodically arranged in a direction perpendicular to an extending direction thereof, the second word line patterns 12 are periodically arranged in a direction perpendicular to the extending direction thereof, the extending directions of the first word line patterns 11 and the second word line patterns 12 are the same, the first word line patterns 11 and the second word line patterns 12 are adjacently disposed, a shape of a second portion 10b of the first word line pattern 11 is a mirror image of a shape of a second portion 10b of the second word line pattern 12, that is, a shape of the second portion 10b of the first word line pattern 11 and a shape of the second portion 10b of the second word line pattern 12 after being overlapped are "i" h "shaped. The second portion 10b of the first word line pattern 11 and the second portion 10b of the second word line pattern 12 are arranged in a staggered position, that is, the second portion 10b of the first word line pattern 11 and the second portion 10b of the second word line pattern 12 are located at different positions of the word line pattern 10 along the extending direction of the word line pattern 10, for example, the second portion 10b of the first word line pattern 11 is adjacent to the first portion 10a of the second word line pattern 12, and the third portion 10c of the first word line pattern 11 is adjacent to the second portion 10b of the second word line pattern 12, which also helps to increase the distance between the second portion and the adjacent word line pattern. Meanwhile, the distance between the second portion 10b of the first word line pattern 11 and the first portion 10a of the second word line pattern 12, the line width of the first portion 10a of the second word line pattern 12 adjacent to the second portion 10b of the first word line pattern 11 is designed to be, for example, 0.18 μm to 0.25 μm; similarly, the line width of the third portion 10c of the first word line pattern 11 adjacent to the second portion 10b of the second word line pattern 12 is designed to be, for example, 0.18 μm to 0.25 μm. The line widths of the first and third portions 10a and 10c of the first word line pattern 11 and the first and third portions 10a and 10c of the second word line pattern 12 away from the adjacent overlapping area 21 are each designed to be, for example, 0.2 μm to 0.3 μm.
The block pattern 20 may have a square shape, for example, a rectangular shape. The longer side of the rectangle is, for example, the same as the extending direction along the first portion or the third portion of the word line, the length of the side of the block pattern 20 perpendicular to the extending direction of the first portion or the third portion of the word line is, for example, equal to or greater than the length of the overlapping region 21 in that direction, and the length of the side of the block pattern 20 perpendicular to the extending direction of the first portion or the third portion of the word line is, for example, equal to the length of the overlapping region 21 in that direction, at this time, the distance between the block pattern 20 and the adjacent word line pattern 10 is large, and the distance between the adjacent block patterns 20 is also large, and the distances are, for example, between 0.19 μm and 0.25 μm.
The contact hole layout has a plurality of contact hole patterns 30, each two of the contact hole patterns 30 overlap one of the block patterns 20, and the two contact hole patterns 30 are respectively located at both sides of the overlap region 21. The contact holes are used to form plugs for electrically connecting control gates, and two of the contact hole patterns 30 are located on diagonal lines of the block pattern 20. At this time, the distance between the contact hole pattern 30 and the adjacent word line pattern 10 is large, for example, 0.19 μm to 0.25 μm, which increases the process window of a plug to be formed in the contact hole later, and avoids the problem of abnormal connection between the contact hole and the adjacent block pattern 10.
Fig. 3 is a flowchart illustrating a method for forming an embedded flash memory according to the present embodiment. As shown in fig. 3, the embodiment further provides a method for forming an embedded flash memory, including the following steps:
step S10: providing a semiconductor substrate;
step S20: forming a word line using a first mask, wherein the first mask has a word line pattern;
step S30: forming a block by using a second photomask, wherein the block and the word line have an overlapping area, and the shape of the word line in the overlapping area is Z-shaped, and the second photomask has a block pattern; and
step S40: and forming contact holes by using a third photomask, wherein two contact holes are formed in each block, the two contact holes are respectively positioned at two sides of the word line, and plugs are formed in the contact holes, and the third photomask is provided with a contact hole pattern.
Specifically, the method comprises the following steps:
first, step S10 is executed to provide a semiconductor substrate, where the semiconductor substrate includes a base, and an oxide layer, a floating gate layer, a dielectric layer, a control layer and a passivation layer sequentially formed on the base, where the dielectric layer is, for example, an ONO stack.
Next, step S20 is executed, a first photoresist layer is formed on the semiconductor substrate; patterning the first photoresist layer by using a first photomask to form a patterned first photoresist layer; etching the passivation layer, the control gate layer, the dielectric layer and the floating gate layer by taking the patterned first photoresist layer as a mask to expose the oxide layer to form a groove; then forming a side wall in the groove; then, forming a word line in the groove, wherein the first photomask has a word line pattern 10; and finally, removing the first photoresist layer.
Then, after forming the word line, forming a hard mask layer on the word line, wherein the hard mask layer covers the word line, and the hard mask layer is used for preventing the word line from being corroded in a subsequent etching process.
Next, step S30 is performed, a second photoresist layer is formed on the semiconductor substrate, and the second photoresist layer covers the hard mask layer and the passivation layer; patterning the second photoresist layer by using a second photomask to form a patterned second photoresist layer; and taking the second patterned photoresist layer and the hard mask layer as masks, sequentially etching the passivation layer, the control gate layer, the dielectric layer, the floating gate layer and the oxide layer to expose the substrate between adjacent word lines, separating adjacent control gates and floating gates to form blocks, and finally removing the second photoresist layer. The etching process in this embodiment etches other regions except the block, the block and the word line have an overlapping region 21, and the word line located in the overlapping region 21 is in a zigzag shape, wherein the second mask has a block pattern 20. The word line comprises a first part 10a, a second part 10b and a third part 10c, the first part 10a and the third part 10c are respectively connected to two ends of the second part 10b, the second part 10b is located in the overlapping area 21, the second part 10b is in a zigzag shape along the extending direction of the second part, the zigzag overlapping area is beneficial to increasing the distance between the contact hole and the adjacent word line, control gate and block, the line width of the second part 10b is 0.18-0.25 μm, the distance between the contact hole and the adjacent word line and control gate is further increased, the process window for forming the contact hole is increased, and the occurrence of abnormal connection between the contact hole and the control gate of the adjacent word line is reduced.
Then, step S40 is executed to form a third photoresist layer on the semiconductor substrate; patterning the third photoresist layer by using a third photomask to form a patterned third photoresist layer; etching the passivation layer by taking the patterned third photoresist layer as a mask to form contact holes, wherein two contact holes are formed in each block, and the two contact holes are respectively positioned at two sides of the word line; and filling metal in the contact holes to form plugs, wherein the plugs are used for connecting out the control gates on two sides of the word line. Wherein the third photomask has a contact hole pattern 30 exposing the control gate layer; and removing the third photoresist layer.
The embodiment also provides an embedded flash memory which is prepared by the method.
In summary, the present invention provides a layout structure of an embedded flash memory, an embedded flash memory and a method for forming the same, where the layout structure of the embedded flash memory includes word line patterns and block patterns, the word line patterns and the block patterns are arranged in a cross manner to form an overlapping region of the block patterns and the word line patterns, the overlapping region is in a zigzag shape, each block pattern has two contact hole patterns, and the two contact hole patterns are respectively located at two sides of the overlapping region. The invention increases the process window of the contact hole by the shape of the overlapping area in a Z shape;
furthermore, the line width of the second part of the word line pattern is adjusted, the distance between the block pattern and the adjacent word line pattern is increased, the process window of the contact hole can be further increased, and the occurrence of abnormal connection between the contact hole and the control gates on two sides of the adjacent word line is reduced.
In addition, it should be noted that the terms "first", "second", and the like in the specification are used for distinguishing each component, element, step, and the like in the specification, and are not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (14)
1. A layout structure of an embedded flash memory, comprising:
the word line layout is provided with a plurality of word line patterns, each word line pattern is provided with a first part, a second part and a third part, the first part and the third part are connected to two ends of the second part, the word line patterns comprise a plurality of first word line patterns and a plurality of second word line patterns, the first word line patterns and the second word line patterns are arranged adjacently, the shapes of the second parts of the first word line patterns and the shapes of the second parts of the second word line patterns are mirror images, and the second parts of the first word line patterns and the second word line patterns are arranged in a staggered mode;
the block layout is provided with a plurality of block patterns, the word line patterns and the block patterns are provided with overlapping regions, and the overlapping regions are Z-shaped;
a contact hole layout having a plurality of contact hole patterns; and
and each two contact hole patterns are overlapped with one block pattern, and the two contact hole patterns are respectively positioned at two sides of the overlapped area.
2. The layout structure according to claim 1, wherein the second portion is located in the overlap region, and the second portion has a zigzag shape.
3. The layout structure according to claim 2, wherein the line width of the second portion of the word line pattern is 0.18 μm to 0.25 μm.
4. The layout structure according to claim 3, wherein the line widths of the end portions of the first portion and the third portion of the word line pattern, which are connected to the second portion, are each 0.18 μm to 0.25 μm.
5. The layout structure of claim 4, wherein the word line pattern comprises:
a plurality of the first word line patterns are periodically arranged in a direction perpendicular to an extending direction thereof; and
the second word line patterns are periodically arranged in a direction perpendicular to the extending direction of the second word line patterns, and the extending direction of the first word line patterns is the same as that of the second word line patterns.
6. The layout structure according to claim 5, wherein a line width at a first portion of the second word line pattern adjacent to a second portion of the first word line pattern is 0.18 μm to 0.25 μm; a line width at a third portion of the first word line pattern adjacent to the second portion of the second word line pattern is 0.18 to 0.25 μm.
7. The layout structure according to claim 1, wherein a distance between the contact hole pattern and the adjacent word line pattern is 0.19 μm to 0.25 μm.
8. A method for forming an embedded flash memory is characterized by comprising the following steps:
providing a semiconductor substrate;
forming word lines using a first mask, wherein the first mask has word line patterns, each of the word line patterns has a first portion, a second portion, and a third portion, the first portion and the third portion are connected to both ends of the second portion, the word line patterns include a plurality of first word line patterns and a plurality of second word line patterns, the first word line patterns and the second word line patterns are adjacently disposed, a shape of the second portion of the first word line pattern is a mirror image of a shape of the second portion of the second word line pattern, and the second portion of the first word line pattern and the second portion of the second word line pattern are positionally staggered;
forming a block by using a second photomask, wherein the block and the word line have an overlapping area, and the shape of the word line in the overlapping area is Z-shaped, and the second photomask has a block pattern; and
and forming contact holes by using a third photomask, wherein two contact holes are formed in each block, the two contact holes are respectively positioned at two sides of the word line, and plugs are formed in the contact holes, and the third photomask is provided with a contact hole pattern.
9. The method of claim 8, wherein the semiconductor substrate comprises a base, and an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a passivation layer sequentially formed on the base.
10. The method of forming an embedded flash memory of claim 9, wherein the step of forming the word line comprises:
forming a first photoresist layer on the semiconductor substrate;
patterning the first photoresist layer by using a first photomask to form a patterned first photoresist layer; and
taking the first patterned photoresist layer as a mask, sequentially etching the passivation layer, the control gate layer, the dielectric layer and the floating gate layer and exposing the oxide layer to form a word line; and
and removing the first photoresist layer.
11. The method of claim 9, wherein the step of forming the block comprises:
forming a second photoresist layer on the semiconductor substrate;
patterning the second photoresist layer by using a second photomask to form a patterned second photoresist layer; and
taking the patterned second photoresist layer as a mask, sequentially etching the passivation layer, the control gate layer, the dielectric layer, the floating gate layer and the oxide layer to expose the substrate to form a block; and
and removing the second photoresist layer.
12. The method of forming an embedded flash memory of claim 9, wherein the step of forming the plug comprises:
forming a third photoresist layer on the semiconductor substrate;
patterning the third photoresist layer by using a third photomask to form a patterned third photoresist layer;
etching the passivation layer and exposing the control gate by taking the patterned third photoresist layer as a mask to form a contact hole;
filling metal in the contact hole to form a plug; and
and removing the third photoresist layer.
13. The method of claim 9, wherein the second portion is located in the overlapping region, the second portion has a zigzag shape, and a line width of the second portion of the word line pattern is 0.18 μm to 0.25 μm.
14. An embedded flash memory prepared by the method for forming an embedded flash memory according to claims 8-13.
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