CN108695185A - The method for detecting alignment offset - Google Patents
The method for detecting alignment offset Download PDFInfo
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- CN108695185A CN108695185A CN201810482595.7A CN201810482595A CN108695185A CN 108695185 A CN108695185 A CN 108695185A CN 201810482595 A CN201810482595 A CN 201810482595A CN 108695185 A CN108695185 A CN 108695185A
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- contact hole
- control gate
- opening
- isolation structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of methods of detection alignment offset to judge whether the displacement between the contact hole and the control gate meets control and require by comparing the all-in resistance of adjacent two row contact hole.Since contact hole is located at the both ends of control gate, when displacement has occurred in the contact hole and control gate, the area contacted between contact hole and control gate will certainly be caused to change, and then change the resistance of contact hole, so whether the all-in resistance by comparing the adjacent two row contact hole is identical, it can simply and effectively judge whether the displacement between the contact hole and the control gate meets control and require, if generating displacement, board can be adjusted, avoid the generation of batch defective products.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of methods of detection alignment offset.
Background technology
Flash memory (Flash Memory) is that a kind of the non-volatile of long-life (remains to keep being stored under power blackout situation
Data information) memory, due to remained to when it is powered off preserve data, flash memory is usually used to preservation setting information, such as in electricity
Preservation data etc. in the BIOS (basic program) of brain, PDA (personal digital assistant), digital camera.
As the development of integrated circuit technology and critical size are scaled, the size of the storage unit of flash memory also into
One step reduces, when the contact hole of flash cell and the Aligning degree of polysilicon gate have deviation slightly to will result in device globality
The failure of energy or program fail.As the distance of control gate and line is more and more closer, conventional photoresist defines the side of contact hole
Method is passless, and then turns to self-aligned contact hole (Self-Aligned-Contact, SAC) technique, but now without one
The method whether effective detection contact hole of kind and control gate are aligned.
Invention content
The purpose of the present invention is to provide a kind of methods of detection alignment offset, can not effectively be examined with solving the prior art
The problems such as whether survey contact hole and control gate are aligned.
In order to achieve the above object, the present invention provides a kind of methods of detection alignment offset, including:
Substrate is provided, shallow groove isolation structure is formed in the substrate;
Multiple row control grid layer is formed on the shallow groove isolation structure, the adjacent two row control grid layer is staggered, often
It includes multiple control gates to arrange the control grid layer, and the first isolation junction being arranged alternately along line direction is formed in the control grid layer
Structure and the second isolation structure, in a column direction, the first isolation structure second isolation structure are narrow, each control
Grid are separated across first isolation structure, two adjacent control gates of same row by second isolation structure;
Be respectively formed contact hole at the both ends of each control gate, wherein a contact hole close to first isolation structure,
Another contact hole is close to second isolation structure;
All contact holes of each column control grid layer are connected, the all-in resistance of each column contact hole is detected, by comparing adjacent two
The all-in resistance of row contact hole, judges whether the displacement between the contact hole and the control gate meets control and require.
Optionally, each projected area of the contact hole on substrate relatively each control gate is over the substrate
Projected area is small.
Optionally, it when the all-in resistance of adjacent two row contact hole is equal, is aligned between the contact hole and the control gate;
When the all-in resistance of adjacent two row contact hole is unequal, there is displacement between the contact hole and the control gate.
Optionally, by comparing the size of the all-in resistance of adjacent two row contact hole, obtain each contact hole with it is each
The direction shifted between the control gate.
Optionally, the method for formation first isolation structure, the second isolation structure and control grid layer includes:
Control gate polysilicon layer is formed on the shallow groove isolation structure;
The control gate polysilicon layer is etched until exposing the shallow groove isolation structure, it is in anti-" Z " type to form multiple row
First opening;
Dielectric layer is formed, the dielectric layer covers the control gate polysilicon layer, is formed along institute in the dielectric layer
The second opening and third opening that line direction is arranged alternately are stated, the cross-sectional width third opening of second opening is cut
Face width is big;
It is respectively formed side wall, the bottom wall whole quilt of the third opening in the side wall of second opening and third opening
The bottom wall portion of the side wall covering, second opening is covered by the side wall;
Using the side wall as mask, the control gate polysilicon layer below etching the second opening bottom wall, and described in filling
Second opening;
The dielectric layer is removed, the row control gate polysilicon layer in protection first opening removes remaining described
Control gate polycrystal layer forms first isolation structure, the second isolation structure and multiple row control grid layer.
Optionally, the quantity of the first opening described in each column is multiple, and multiple first openings are arranged in array.
Optionally, the material identical of the material and the side wall of second opening is filled.
Optionally, the material of material and the side wall of the filling second opening include silica, silicon nitride or
It is one or more in silicon oxynitride.
Optionally, the width of first isolation structure is equal with the width that the third is open, second isolation junction
The width of structure is equal with the width of the second opening.
Optionally, include in the method for the both ends of each control gate formation contact hole:
Silicon oxide layer is formed, the silicon oxide layer covers the substrate and the multiple row control grid layer;
The silicon oxide layer is etched until exposing the both ends of each control gate, forms through-hole;
Conductive material is filled in the through-hole.
In the method for detection alignment offset provided by the invention, is formed and be arranged alternately on the isolation structure of the substrate
Control grid layer, control grid layer described in each column includes multiple control gates, then form on the control grid layer that width differs the
One isolation structure and the second isolation structure, each control gate is across first isolation structure, adjacent two of same row
A control gate is separated by second isolation structure;It is respectively formed contact hole at the both ends of each control gate, each column is controlled
All contact holes of grid layer are connected, and the all-in resistance of each column contact hole is detected, and by comparing the all-in resistance of adjacent two row contact hole, are sentenced
Whether the displacement between the contact hole and the control gate of breaking, which meets control, requires.Since contact hole is located at the two of control gate
End will certainly cause the area contacted between contact hole and control gate to send out when displacement has occurred with control gate in the contact hole
It is raw to change, and then change the resistance of contact hole, so whether the all-in resistance by comparing the adjacent two row contact hole is identical, it can
It is required so that whether the displacement simply and effectively judged between the contact hole and the control gate meets control, if generating displacement,
Board can be adjusted, avoid the generation of batch defective products.
Description of the drawings
Fig. 1 is the schematic diagram of the method for the detection alignment offset that embodiment provides;
Fig. 2 is the schematic diagram that the formation first that embodiment provides is open;
Fig. 3 is the another schematic diagram that the formation first that embodiment provides is open;
Fig. 4 is the schematic diagram for the formation dielectric layer that embodiment provides;
Fig. 5 is the schematic diagram of the opening of formation second that embodiment provides and third opening;
Fig. 6 is the schematic diagram for the formation side wall that embodiment provides;
Fig. 7 is the schematic diagram after the removal dielectric layer that embodiment provides;
Fig. 8 is the schematic diagram for the formation contact hole that embodiment provides;
Fig. 9 is the schematic diagram that the contact hole that embodiment provides is moved up relative to control gate;
Figure 10 is the schematic diagram that the contact hole that embodiment provides is moved down relative to control gate;
Figure 11 be embodiment provide by the concatenated schematic diagram of each column contact hole;
Figure 12 be embodiment provide by the concatenated another schematic diagram of each column contact hole;
Wherein, 1- substrates, 2- shallow groove isolation structures, 3- control gate polysilicon layer, 31- control gates, 32- contact holes, 4- the
One opening, 5- dielectric layers, 61- second are open, 62- thirds opening, 7- side walls, M- metal layers, a- line directions, b- column directions, 81-
First isolation structure, the second isolation structures of 82-, 9- silicon oxide layers.
Specific implementation mode
The specific implementation mode of the present invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Refering to fig. 1, it is the schematic diagram of the method provided in this embodiment for detecting alignment offset, as shown in Figure 1, the inspection
Survey alignment offset method include:
S1:Substrate is provided;
S2:Multiple row control grid layer is formed on the shallow groove isolation structure, the adjacent two row control grid layer is staggered,
Control grid layer described in each column includes multiple control gates, and the first isolation being arranged alternately along line direction is formed in the control grid layer
Structure and the second isolation structure, in a column direction, the first isolation structure second isolation structure are narrow, each control
Grid processed are separated across first isolation structure, two adjacent control gates of same row by second isolation structure;
S3:It is respectively formed contact hole at the both ends of each control gate, wherein a contact hole is close to first isolation junction
Structure, another contact hole is close to second isolation structure;
S4:All contact holes of each column control grid layer are connected, the all-in resistance of each column contact hole is detected, by comparing adjacent
The all-in resistance of two row contact holes, judges whether the displacement between the contact hole and the control gate meets control and require.
Wherein, since the contact hole is located at the both ends of each control gate, when the contact hole and control gate occur
When displacement, the area contacted between contact hole and control gate will certainly be caused to change, and then change the resistance of contact hole,
So whether the all-in resistance for arranging the contact hole by comparing adjacent two identical, can simply and effectively judge the contact hole with
Whether the displacement between the control gate, which meets control, requires, if generating displacement, can be adjusted to board, avoids batch not
The generation of non-defective unit.Certainly, the control requires and not exclusive, can be adjusted according to the device being actually formed, the present invention is not
It is restricted.
The wafer is divided into test section and non-test area, and the non-test area forms normal flash cell, the test
Area forms test structure using same technique and is tested, and by testing test section, can reflect the non-survey of wafer
Try the case where contact hole and control gate shift in the normal flash unit in area, if the contact hole of the test structure and control gate it
Between produce displacement, then contact hole and control gate also have displacement in normal flash unit, the board of being adapted to property adjustment at this time
Parameter improves the yield of product, and bulk defective products is avoided to generate.
(only adaptability depicts the test section of wafer in figure) includes substrate 1, the substrate 1 as shown in Fig. 2, the wafer
Material can be silicon, germanium, germanium silicon or GaAs etc., and form active area, the substrate 1 by modes such as ion implantings
In be also formed with shallow groove isolation structure 2 etc. for isolation, the test structure is both formed on the shallow groove isolation structure 2.
Specifically, forming control gate polysilicon layer 3 on the shallow groove isolation structure 2, the control gate polysilicon layer 3 covers described shallow
The material of recess isolating structure 2, the control gate polysilicon layer 3 is polycrystalline silicon material.
As shown in figure 3, the etching control gate polysilicon layer 3 is until expose the surface of the shallow groove isolation structure 2, shape
It is in first opening 4 of anti-" Z " type at multiple row, the quantity of first opening 4 in the first opening 4 described in each column is multiple, is used
In by not going together of being subsequently formed and the control gate of different lines separates.Multiple first openings 4 are arranged in array.
Please continue to refer to Fig. 4, dielectric layer 5 is formed, the dielectric layer 5 covers the control gate polysilicon layer 3, the medium
The material of layer 5 can be silicon nitride and/or titanium nitride.Then as shown in figure 5, etching the dielectric layer 5 forms multiple alternately rows
The second opening 61 and third opening 62 of cloth, along the column direction, the cross-sectional width third of second opening 61
The cross-sectional width of opening 62 is big.It is respectively formed along the line direction in the side wall of second opening 61 and third opening 62
The equal side wall 7 of cross-sectional width (side wall 7 is identical as side wall when non-test area's formation normal flash unit), it is described
The cross-sectional width of third opening 62 is less than twice of the cross-sectional width of the side wall 7, and second opening 61 is more than the side wall 7
Twice of cross-sectional width, at this time the side wall 7 completely cover the bottom wall of the third opening 62, i.e. the third opening 62
It is filled, since the cross-sectional width of the cross-sectional width third opening 62 of second opening 61 is wide, and described second
Opening 61 is more than twice of the cross-sectional width of the side wall 7, so having between two side walls of second opening 61 certain
Distance is not filled.Then, it is mask with the side wall 7, the control grid layer polysilicon of etching second opening, 61 bottom walls
3, since third opening 62 is filled, the control gate polysilicon 3 of 62 lower section of third opening is not etched, specifically such as
Shown in Fig. 6.Finally, the third opening 62 is filled to form the first isolation structure 81, and second opening 61 can also use
It is filled with the material of the material identical of the side wall 7, to form the second isolation structure 82, the material of the side wall includes oxygen
It is one or more in SiClx, silicon nitride or silicon oxynitride.From fig. 6 it can be seen that first isolation structure 81 is located at institute
The top of control gate polysilicon layer 3 is stated, and a part for second isolation structure 82 is located at the control gate polysilicon layer 3
It is interior, the control gate polysilicon layer 3 is separated.
Please continue to refer to Fig. 7, the dielectric layer 5 is removed, then uses mask by two row at the first opening 4 described in each column
Control gate polysilicon layer 3 covers, and etches the control gate polysilicon layer 3, the control gate in the region not covered by the mask
Polysilicon layer 3 is etched away, and is retained, is formed more by the control gate polysilicon layer 3 in the first 4 regions of opening that the mask covers
Row control grid layer.
Finally formed structure as shown in fig. 7, first isolation structure 81 and second isolation structure 82 along institute
Line direction a is stated to be arranged alternately;Multiple row control grid layer is arranged alternately along the column direction b, also, control grid layer described in each column has
Have staggeredly, i.e., be staggered a certain distance between adjacent two row control grid layer, and the control grid layer position of all odd columns is identical, institute
There is the control grid layer position of even column identical, since the control gate polysilicon layer 3 of second isolation structure, 82 lower section is divided
It separates, control grid layer described in each column disconnects here, and each row control grid layer includes the equal control gate 31 of quantity, each
The control gate 31 is across first isolation structure 81, and two adjacent control gates 31 of same row are by second isolation junction
Structure 82 separates.
As shown in figure 8, contact hole 32 is beaten at the both ends of each control gate 31 using self-registered technology, specifically, described
Silicon oxide layer 9 is formed on substrate 1, is etched the silicon oxide layer 9 until exposing the both ends of each control gate 31, is formed more
A through-hole fills conductive material, such as copper and/or tungsten etc. in the through-hole, forms the contact hole 32 being connect with control gate 31,
The area of the contact hole 32 is small compared with the area of the control gate 31, also, the contact hole at 31 both ends of the control gate one leans on
Nearly first isolation structure 81, another is close to the second isolation structure 82.
Refering to Fig. 9-Figure 10, the contact hole 32 is formed using self-registered technology due to being, if the contact hole 32 with
The control gate 31 is shifted, then necessarily 32 same shift of permutation contact hole, also, the contact hole 32 of each row is equal
Identical displacement has occurred, there is no single contact hole 32 displacement and remaining contact hole 32 do not shift the case where, if described
Displacement (Fig. 9 is the case where moving up, and Figure 10 is the case where moving down) has occurred with the control gate 31 in contact hole 32, will certainly cause
The area contacted between the contact hole 32 and the control gate 31 changes, in Fig. 9, one row contact hole 32 of the left side and control
Contact area becomes smaller between grid 31, and contact is deteriorated, and contact area becomes larger between one row contact hole 32 of the right and control gate 31, contact
Improve;Conversely, in Figure 10, contact area becomes larger between one row contact hole 32 of the left side and control gate 31, and contact improves, and the right one
Contact area becomes smaller between row contact hole 32 and control gate 31, and contact is deteriorated;The contact hole 32 connects with the control gate 31
Contacting surface product changes, and the resistance of contact hole 32 will certainly be caused to change.
Next 1- Figure 12 is please referred to Fig.1, all contact holes 32 of each column control grid layer is connected, specifically, can be with shape
At a metal layer M, the contact hole 32 that second isolation structure 82 disconnects is connected, convenient for forming test loop.Inspection
It measures adjacent two and arranges the all-in resistance of the contact hole 32 (since the width of each control gate 31 is equal, two row control grid layers
In the resistance of control gate 31 can cancel out each other), when the all-in resistance of adjacent two row contact hole 32 is equal, the contact hole 32
It is not shifted between the control gate 31;When the all-in resistance of adjacent two row contact hole 32 is unequal, the contact hole 32 with
The control gate 31 produces displacement.
Specifically, as shown in figure 12, when the all-in resistance R1 of one row contact hole 32 of the left side is more than one row contact hole 32 of the right
When all-in resistance R2, show that resistance increases between one row contact hole 32 of the left side and control gate 31, contact area reduces, the contact hole
Displacement between 32 and the control gate 31 is upward, conversely, described in being less than as the all-in resistance R1 of one row contact hole 32 of the left side
When the all-in resistance R2 of one row contact hole 32 of the right, show that resistance increases between one row contact hole 32 of the right and control gate 31, contact
Area reduces, and the displacement between the contact hole 32 and the control gate 31 is downward.By judging adjacent two row contact hole 32
The size of all-in resistance can easily judge displacement and displacement whether are produced between contact hole 32 and the control gate 31
Direction, so as to those skilled in the art carry out board adjusting, avoid the generation of defective products.
To sum up, in the method for detection alignment offset provided in an embodiment of the present invention, on the isolation structure of the substrate
The control grid layer being arranged alternately is formed, control grid layer includes multiple control gates described in each column, then is formed on the control grid layer
The first isolation structure and the second isolation structure that width differs, each control gate are same across first isolation structure
Two adjacent control gates of row are separated by second isolation structure;It is respectively formed contact at the both ends of each control gate
All contact holes of each column control grid layer are connected in hole, detect the all-in resistance of each column contact hole, by comparing adjacent two row contact
The all-in resistance in hole, judges whether the displacement between the contact hole and the control gate meets control and require.Due to contact hole
Positioned at the both ends of control gate, when displacement has occurred in the contact hole and control gate, will certainly cause contact hole and control gate it
Between the area that contacts change, and then change the resistance of contact hole, so by comparing the total of the adjacent two row contact hole
Whether resistance is identical, can simply and effectively judge whether the displacement between the contact hole and the control gate meets control and want
It asks, if generating displacement, board can be adjusted, avoid the generation of batch defective products.
The preferred embodiment of the present invention is above are only, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical scheme of the present invention, to the invention discloses technical solution and
Technology contents make the variations such as any type of equivalent replacement or modification, belong to the content without departing from technical scheme of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. it is a kind of detection alignment offset method, which is characterized in that it is described detection alignment offset method include:
Substrate is provided, shallow groove isolation structure is formed in the substrate;
Multiple row control grid layer is formed on the shallow groove isolation structure, the adjacent two row control grid layer is staggered, each column institute
It includes multiple control gates to state control grid layer, the control grid layer formed the first isolation structure being arranged alternately along line direction and
Second isolation structure, in a column direction, the first isolation structure second isolation structure are narrow, and each control gate is horizontal
Separated by second isolation structure across two adjacent control gates of first isolation structure, same row;
It is respectively formed contact hole at the both ends of each control gate, wherein a contact hole is another close to first isolation structure
Contact hole is close to second isolation structure;
All contact holes of each column control grid layer are connected, the all-in resistance of each column contact hole is detected, are connect by comparing adjacent two row
The all-in resistance of contact hole, judges whether the displacement between the contact hole and the control gate meets control and require.
2. the method for detection alignment offset as described in claim 1, which is characterized in that each contact hole is on substrate
Projected area is small compared with each projected area of the control gate over the substrate.
3. the method for detection alignment offset as claimed in claim 2, which is characterized in that when the all-in resistance of adjacent two row contact hole
When equal, it is aligned between the contact hole and the control gate;It is described to connect when the all-in resistance of adjacent two row contact hole is unequal
There is displacement between contact hole and the control gate.
4. the method for detection alignment offset as claimed in claim 3, which is characterized in that by comparing adjacent two row contact hole
The size of all-in resistance obtains the direction shifted between each contact hole and each control gate.
5. the method for detection alignment offset as described in claim 1, which is characterized in that form first isolation structure, the
The method of two isolation structures and control grid layer includes:
Control gate polysilicon layer is formed on the shallow groove isolation structure;
The control gate polysilicon layer is etched until exposing the shallow groove isolation structure, forms multiple row is in anti-" Z " type first
Opening;
Dielectric layer is formed, the dielectric layer covers the control gate polysilicon layer, is formed along the row in the dielectric layer
The section of the second opening and third opening that direction is arranged alternately, the cross-sectional width third opening of second opening is wide
Degree is big;
It is respectively formed side wall in the side wall of second opening and third opening, the bottom wall of the third opening is all described
Side wall covers, and the bottom wall portion of second opening is covered by the side wall;
Using the side wall as mask, the control gate polysilicon layer below etching the second opening bottom wall, and fill described second
Opening;
The dielectric layer is removed, the row control gate polysilicon layer in protection first opening removes the remaining control
Grid polycrystal layer forms first isolation structure, the second isolation structure and multiple row control grid layer.
6. as claimed in claim 5 detection alignment offset method, which is characterized in that described in each column first opening quantity be
Multiple, multiple first openings are arranged in array.
7. as claimed in claim 5 detection alignment offset method, which is characterized in that filling it is described second opening material with
The material identical of the side wall.
8. the method for detection alignment offset as claimed in claim 7, which is characterized in that the material of filling second opening
Expect that the material with the side wall includes one or more in silica, silicon nitride or silicon oxynitride.
9. as claimed in claim 7 detection alignment offset method, which is characterized in that the width of first isolation structure with
The width of the third opening is equal, and the width of second isolation structure is equal with the width of the second opening.
10. the method for detection alignment offset as claimed in claim 5, which is characterized in that at the both ends of each control gate
Formed contact hole method include:
Silicon oxide layer is formed, the silicon oxide layer covers the substrate and the multiple row control grid layer;
The silicon oxide layer is etched until exposing the both ends of each control gate, forms through-hole;
Conductive material is filled in the through-hole.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810482595.7A CN108695185B (en) | 2018-05-18 | 2018-05-18 | Method for detecting alignment shift |
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|---|---|---|---|
| CN201810482595.7A CN108695185B (en) | 2018-05-18 | 2018-05-18 | Method for detecting alignment shift |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110058486A (en) * | 2019-03-26 | 2019-07-26 | 云谷（固安）科技有限公司 | The detection method of mask plate component and mask plate component splicing precision |
| CN110349960A (en) * | 2019-07-08 | 2019-10-18 | 上海华虹宏力半导体制造有限公司 | The domain structure of embedded flash memory, embedded flash memory and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376601B (en) * | 2010-08-24 | 2013-05-29 | 中芯国际集成电路制造(上海)有限公司 | Detection method and structure for deviation of contact hole |
| CN102543740A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for improving alignment uniformity between polycrystalline silicon gate and contact hole |
| CN102723294B (en) * | 2012-06-20 | 2015-04-22 | 上海华力微电子有限公司 | Method for detecting registration between contact hole and polycrystalline silicon gate |
| CN103354211B (en) * | 2013-06-25 | 2016-01-27 | 上海华力微电子有限公司 | The method of measuring and calculating contact hole and polysilicon gate deviation of the alignment value |
| CN103346107A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon grid and contact hole |
| CN103346100B (en) * | 2013-06-27 | 2016-04-20 | 上海华力微电子有限公司 | Detect the method for contact hole and polysilicon gate Aligning degree |
| CN204045551U (en) * | 2014-09-04 | 2014-12-24 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN204216010U (en) * | 2014-09-04 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN104600032B (en) * | 2014-12-31 | 2017-10-03 | 北京兆易创新科技股份有限公司 | A kind of preparation method of nor gate flash memories |
| CN105118794B (en) * | 2015-07-22 | 2018-02-09 | 上海华力微电子有限公司 | A kind of test SRAM shares the structure of contact hole and polysilicon contact resistance |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110058486A (en) * | 2019-03-26 | 2019-07-26 | 云谷（固安）科技有限公司 | The detection method of mask plate component and mask plate component splicing precision |
| CN110058486B (en) * | 2019-03-26 | 2022-06-28 | 云谷（固安）科技有限公司 | Mask plate assembly and detection method for splicing precision of mask plate assembly |
| CN110349960A (en) * | 2019-07-08 | 2019-10-18 | 上海华虹宏力半导体制造有限公司 | The domain structure of embedded flash memory, embedded flash memory and forming method thereof |
| CN110349960B (en) * | 2019-07-08 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | Layout structure of embedded flash memory, embedded flash memory and forming method thereof |
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| CN108695185B (en) | 2020-07-17 |
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