CN108695185B - Method for detecting alignment shift - Google Patents
Method for detecting alignment shift Download PDFInfo
- Publication number
- CN108695185B CN108695185B CN201810482595.7A CN201810482595A CN108695185B CN 108695185 B CN108695185 B CN 108695185B CN 201810482595 A CN201810482595 A CN 201810482595A CN 108695185 B CN108695185 B CN 108695185B
- Authority
- CN
- China
- Prior art keywords
- control gate
- isolation structure
- contact holes
- opening
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for detecting alignment deviation, which judges whether the displacement between a contact hole and a control grid meets the control requirement or not by comparing the total resistance of two adjacent rows of contact holes. Because the contact hole is located the both ends of control gate, when contact hole and control gate had taken place to shift, will probably cause the area of contact to change between contact hole and the control gate, and then change the resistance of contact hole, so through comparing whether the total resistance of two adjacent contact holes is the same, can simple effectual judgement the contact hole with shift between the control gate satisfies the control requirement, if produce the aversion, can adjust the board, avoid the production of defective products in batches.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for detecting alignment deviation.
Background
Flash Memory (Flash Memory) is a long-life nonvolatile (data information stored in a power-off state) Memory that can store data even when power is off, and is generally used to store setting information such as data in a BIOS (basic program) of a computer, a PDA (personal digital assistant), a digital camera, and the like.
As integrated circuit processes have been developed and critical dimensions have been scaled down, the size of flash memory cells has been further reduced, and slight misalignment between the contact holes and the polysilicon gates of flash memory cells can cause failure of the overall performance of the device, or program failure. With the distance between the control gate and the connection line becoming closer, the conventional method for defining the Contact hole by using the photoresist has been changed to a Self-Aligned Contact (SAC) process, but there is no effective method for detecting whether the Contact hole and the control gate are Aligned.
Disclosure of Invention
The invention aims to provide a method for detecting alignment deviation, which aims to solve the problem that the prior art cannot effectively detect whether a contact hole and a control gate are aligned or not.
In order to achieve the above object, the present invention provides a method of detecting an alignment shift, comprising:
providing a substrate, wherein a shallow groove isolation structure is formed in the substrate;
forming a plurality of rows of control gate layers on the shallow slot isolation structure, wherein two adjacent rows of control gate layers are arranged in a staggered manner, each row of control gate layer comprises a plurality of control gates, a first isolation structure and a second isolation structure which are alternately arranged along the row direction are formed on the control gate layers, the first isolation structure is narrower than the second isolation structure in the row direction, each control gate crosses over the first isolation structure, and two adjacent control gates in the same row are separated by the second isolation structure;
forming contact holes at two ends of each control gate, wherein one contact hole is close to the first isolation structure, and the other contact hole is close to the second isolation structure;
and connecting all contact holes of each row of control gate layers in series, detecting the total resistance of each row of contact holes, and judging whether the displacement between the contact holes and the control gates meets the control requirements or not by comparing the total resistances of two adjacent rows of contact holes.
Optionally, a projection area of each contact hole on the substrate is smaller than a projection area of each control gate on the substrate.
Optionally, when the total resistance of two adjacent columns of contact holes is equal, the contact holes are aligned with the control gates; and when the total resistance of the two adjacent rows of contact holes is not equal, the contact holes and the control grid are shifted.
Optionally, the shifting direction between each contact hole and each control gate is obtained by comparing the total resistance of two adjacent columns of contact holes.
Optionally, the method for forming the first isolation structure, the second isolation structure and the control gate layer includes:
forming a control gate polysilicon layer on the shallow trench isolation structure;
etching the control gate polysilicon layer until the shallow trench isolation structure is exposed, and forming multiple rows of first openings in an inverted Z shape;
forming a dielectric layer, wherein the dielectric layer covers the control gate polysilicon layer, and second openings and third openings which are alternately arranged along the row direction are formed in the dielectric layer, and the section width of each second opening is larger than that of each third opening;
side walls are formed on the side walls of the second opening and the third opening, the bottom wall of the third opening is completely covered by the side walls, and the bottom wall part of the second opening is covered by the side walls;
etching the control gate polysilicon layer below the bottom wall of the second opening by using the side wall as a mask, and filling the second opening;
and removing the dielectric layer, protecting the row of control gate polycrystalline silicon layers in the first opening, removing the rest control gate polycrystalline layers, and forming the first isolation structure, the second isolation structure and the rows of control gate layers.
Optionally, the number of the first openings in each row is multiple, and the multiple first openings are arranged in an array.
Optionally, the material filling the second opening is the same as the material of the sidewall.
Optionally, the material filling the second opening and the material of the sidewall include one or more of silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, the width of the first isolation structure is equal to the width of the third opening, and the width of the second isolation structure is equal to the width of the second opening.
Optionally, the method for forming contact holes at two ends of each control gate includes:
forming a silicon oxide layer, wherein the silicon oxide layer covers the substrate and the multiple rows of control gate layers;
etching the silicon oxide layer until two ends of each control gate are exposed to form a through hole;
and filling a conductive material in the through hole.
In the method for detecting the alignment deviation, control gate layers which are alternately arranged are formed on isolation structures of a substrate, each row of the control gate layers comprises a plurality of control gates, first isolation structures and second isolation structures with different widths are formed on the control gate layers, each control gate crosses the first isolation structure, and two adjacent control gates in the same row are separated by the second isolation structures; and forming contact holes at two ends of each control gate, connecting all the contact holes of each row of control gate layers in series, detecting the total resistance of each row of contact holes, and judging whether the displacement between the contact holes and the control gates meets the control requirements or not by comparing the total resistances of two adjacent rows of contact holes. Because the contact hole is located the both ends of control gate, when contact hole and control gate had taken place to shift, will probably cause the area of contact to change between contact hole and the control gate, and then change the resistance of contact hole, so through comparing whether the total resistance of two adjacent contact holes is the same, can simple effectual judgement the contact hole with shift between the control gate satisfies the control requirement, if produce the aversion, can adjust the board, avoid the production of defective products in batches.
Drawings
FIG. 1 is a diagram illustrating a method for detecting an alignment shift according to an exemplary embodiment;
FIG. 2 is a schematic diagram of forming a first opening according to an embodiment;
FIG. 3 is a further schematic diagram of forming a first opening according to an embodiment;
FIG. 4 is a schematic diagram of forming a dielectric layer according to an embodiment;
FIG. 5 is a schematic diagram illustrating the formation of a second opening and a third opening according to an embodiment;
fig. 6 is a schematic diagram of forming a sidewall spacer according to an embodiment;
FIG. 7 is a schematic diagram illustrating the removal of the dielectric layer according to an embodiment;
FIG. 8 is a schematic diagram illustrating the formation of a contact hole according to an embodiment;
FIG. 9 is a schematic diagram of the contact hole being moved up relative to the control gate according to the embodiment;
FIG. 10 is a schematic diagram of the embodiment in which the contact holes are shifted down relative to the control gates;
FIG. 11 is a schematic diagram illustrating the series connection of contact holes in each column according to an embodiment;
FIG. 12 is a further schematic diagram of the series connection of contact holes in each column according to the embodiment;
the structure comprises a substrate 1, a shallow trench isolation structure 2, a control gate polycrystalline silicon layer 3, a control gate 31, a contact hole 32, a first opening 4, a dielectric layer 5, a second opening 61, a third opening 62, a side wall 7, an M-metal layer, an a-row direction, a b-column direction, a first isolation structure 81, a second isolation structure 82 and a silicon oxide layer 9.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, which is a schematic diagram of a method for detecting an alignment deviation according to the present embodiment, as shown in fig. 1, the method for detecting an alignment deviation includes:
s1: providing a substrate;
s2: forming a plurality of rows of control gate layers on the shallow slot isolation structure, wherein two adjacent rows of control gate layers are arranged in a staggered manner, each row of control gate layer comprises a plurality of control gates, a first isolation structure and a second isolation structure which are alternately arranged along the row direction are formed on the control gate layers, the first isolation structure is narrower than the second isolation structure in the row direction, each control gate crosses over the first isolation structure, and two adjacent control gates in the same row are separated by the second isolation structure;
s3: forming contact holes at two ends of each control gate, wherein one contact hole is close to the first isolation structure, and the other contact hole is close to the second isolation structure;
s4: and connecting all contact holes of each row of control gate layers in series, detecting the total resistance of each row of contact holes, and judging whether the displacement between the contact holes and the control gates meets the control requirements or not by comparing the total resistances of two adjacent rows of contact holes.
Because the contact holes are located at two ends of each control gate, when the contact holes and the control gates are shifted, the contact areas between the contact holes and the control gates are changed, and then the resistance of the contact holes is changed, so that whether the total resistance of the contact holes is the same or not is judged simply and effectively, whether the shift between the contact holes and the control gates meets the control requirement or not is judged, and if the shift is generated, a machine table can be adjusted, and the generation of batch defective products is avoided. Of course, the control requirement is not exclusive and may be adjusted according to the actually formed device, and the present invention is not limited thereto.
The wafer is divided into a test area and a non-test area, the non-test area forms a normal flash memory unit, the test area adopts the same process to form a test structure for testing, the test area is tested, the displacement condition of a contact hole and a control gate in the normal flash memory unit in the non-test area of the wafer can be reflected, if the displacement is generated between the contact hole and the control gate of the test structure, the displacement is also generated between the contact hole and the control gate in the normal flash memory unit, at the moment, the parameters of a machine table can be adaptively adjusted, the yield of products is improved, and the generation of defective products in batches is avoided.
As shown in fig. 2, the wafer (only the test area of the wafer is shown in the figure) includes a substrate 1, the material of the substrate 1 may be silicon, germanium, silicon germanium, gallium arsenide, or the like, and an active area is formed by ion implantation or the like, a shallow trench isolation structure 2 for isolation or the like is also formed in the substrate 1, and the test structures are all formed on the shallow trench isolation structure 2. Specifically, a control gate polysilicon layer 3 is formed on the shallow trench isolation structure 2, the control gate polysilicon layer 3 covers the shallow trench isolation structure 2, and the control gate polysilicon layer 3 is made of polysilicon material.
As shown in fig. 3, the control gate polysilicon layer 3 is etched until the surface of the shallow trench isolation structure 2 is exposed, and a plurality of rows of first openings 4 in an inverted "Z" shape are formed, where the number of the first openings 4 in each row of the first openings 4 is multiple, and the first openings are used for isolating control gates in different rows and different columns which are formed subsequently. The first openings 4 are arranged in an array.
Continuing to refer to fig. 4, a dielectric layer 5 is formed, wherein the dielectric layer 5 covers the control gate polysilicon layer 3, and the material of the dielectric layer 5 may be silicon nitride and/or titanium nitride. Then, as shown in fig. 5, the dielectric layer 5 is etched to form a plurality of second openings 61 and third openings 62 alternately arranged, and along the column direction, the cross-sectional width of the second openings 61 is larger than the cross-sectional width of the third openings 62. Side walls 7 with the same cross-sectional width along the row direction are formed on the side walls of the second opening 61 and the third opening 62 (the side walls 7 are the same as the side walls when the normal flash memory cell is formed in the non-test region), the cross-sectional width of the third opening 62 is smaller than twice the cross-sectional width of the side walls 7, the second opening 61 is larger than twice the cross-sectional width of the side walls 7, at this time, the bottom wall of the third opening 62 is completely covered by the side walls 7, that is, the third opening 62 is filled up, because the cross-sectional width of the second opening 61 is wider than the cross-sectional width of the third opening 62, and the second opening 61 is larger than twice the cross-sectional width of the side walls 7, a certain distance exists between the two side walls of the second opening 61, and the two side walls are not filled up. Then, the sidewall 7 is used as a mask to etch the control gate layer polysilicon 3 on the bottom wall of the second opening 61, and since the third opening 62 is filled, the control gate polysilicon 3 below the third opening 62 is not etched, as shown in fig. 6. Finally, the third opening 62 is filled to form a first isolation structure 81, and the second opening 61 may also be filled with the same material as the material of the sidewall 7 to form a second isolation structure 82, where the material of the sidewall includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. As can be seen in fig. 6, the first isolation structure 81 is located above the control gate polysilicon layer 3, and a portion of the second isolation structure 82 is located within the control gate polysilicon layer 3, separating the control gate polysilicon layer 3.
Continuing to refer to fig. 7, the dielectric layer 5 is removed, two rows of the control gate polysilicon layers 3 at the first openings 4 of each row are covered by a mask, the control gate polysilicon layers 3 are etched, the control gate polysilicon layers 3 in the regions not covered by the mask are etched, the control gate polysilicon layers 3 in the regions covered by the mask in the first openings 4 are retained, and a plurality of rows of control gate layers are formed.
The resulting structure is shown in fig. 7, in which the first isolation structures 81 and the second isolation structures 82 are alternately arranged along the row direction a; a plurality of control gate layers are alternately arranged along the column direction b, and each control gate layer is staggered, that is, a certain distance is staggered between two adjacent control gate layers, while the control gate layers of all odd columns are the same in position, and the control gate layers of all even columns are the same in position, because the control gate polysilicon layers 3 below the second isolation structures 82 are separated, each control gate layer is disconnected here, each control gate layer comprises an equal number of control gates 31, each control gate 31 crosses over the first isolation structures 81, and two adjacent control gates 31 of the same column are separated by the second isolation structures 82.
As shown in fig. 8, a self-aligned process is used to make contact holes 32 at two ends of each control gate 31, specifically, a silicon oxide layer 9 is formed on the substrate 1, the silicon oxide layer 9 is etched until two ends of each control gate 31 are exposed, a plurality of through holes are formed, conductive materials, such as copper and/or tungsten, are filled in the through holes to form the contact holes 32 connected to the control gates 31, the area of the contact holes 32 is smaller than that of the control gates 31, and one of the contact holes at two ends of the control gates 31 is close to the first isolation structure 81, and the other is close to the second isolation structure 82.
Referring to fig. 9-10, since the contact holes 32 are formed by a self-aligned process, if the contact holes 32 and the control gate 31 are shifted, the entire columns of the contact holes 32 are necessarily shifted simultaneously, and the same shift occurs in the contact holes 32 of each column, so that there is no case where a single contact hole 32 is shifted and the remaining contact holes 32 are not shifted, and if the contact holes 32 and the control gate 31 are shifted (fig. 9 is an upward shift, and fig. 10 is a downward shift), the area of contact between the contact holes 32 and the control gate 31 is inevitably changed, and in fig. 9, the area of contact between the left column of the contact holes 32 and the control gate 31 is reduced, the contact is deteriorated, and the area of contact between the right column of the contact holes 32 and the control gate 31 is increased, and the contact is improved; on the contrary, in fig. 10, the contact area between the left row of contact holes 32 and the control gate 31 becomes larger, the contact becomes better, and the contact area between the right row of contact holes 32 and the control gate 31 becomes smaller, the contact becomes worse; the contact area between the contact hole 32 and the control gate 31 changes, which inevitably causes the resistance of the contact hole 32 to change.
Referring to fig. 11-12, all the contact holes 32 of each row of control gate layers are connected in series, and specifically, a metal layer M may be formed to connect the contact holes 32 disconnected by the second isolation structure 82, so as to form a test loop. Detecting the total resistance of two adjacent columns of the contact holes 32 (since the width of each control gate 31 is equal, the resistances of the control gates 31 in two columns of control gate layers can be mutually offset), and when the total resistance of two adjacent columns of the contact holes 32 is equal, no displacement exists between the contact holes 32 and the control gates 31; when the total resistance of two adjacent columns of contact holes 32 is not equal, the contact holes 32 are shifted from the control gate 31.
Specifically, as shown in fig. 12, when the total resistance R1 of the left column of contact holes 32 is greater than the total resistance R2 of the right column of contact holes 32, it indicates that the resistance between the left column of contact holes 32 and the control gate 31 increases and the contact area decreases, and the shift between the contact holes 32 and the control gate 31 is upward, whereas when the total resistance R1 of the left column of contact holes 32 is less than the total resistance R2 of the right column of contact holes 32, it indicates that the resistance between the right column of contact holes 32 and the control gate 31 increases and the contact area decreases, and the shift between the contact holes 32 and the control gate 31 is downward. Whether the contact hole 32 and the control gate 31 are shifted or not and the shifting direction can be easily judged by judging the total resistance of two adjacent columns of contact holes 32, so that the adjustment of a machine table can be conveniently carried out by a person skilled in the art, and the generation of defective products is avoided.
In summary, in the method for detecting alignment shift provided in the embodiment of the present invention, control gate layers are formed on isolation structures of a substrate in an alternating arrangement, each row of the control gate layers includes a plurality of control gates, and then a first isolation structure and a second isolation structure with different widths are formed on the control gate layers, each control gate crosses over the first isolation structure, and two adjacent control gates in the same row are separated by the second isolation structure; and forming contact holes at two ends of each control gate, connecting all the contact holes of each row of control gate layers in series, detecting the total resistance of each row of contact holes, and judging whether the displacement between the contact holes and the control gates meets the control requirements or not by comparing the total resistances of two adjacent rows of contact holes. Because the contact hole is located the both ends of control gate, when contact hole and control gate had taken place to shift, will probably cause the area of contact to change between contact hole and the control gate, and then change the resistance of contact hole, so through comparing whether the total resistance of two adjacent contact holes is the same, can simple effectual judgement the contact hole with shift between the control gate satisfies the control requirement, if produce the aversion, can adjust the board, avoid the production of defective products in batches.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method of detecting an alignment shift, the method comprising:
providing a substrate, wherein a shallow groove isolation structure is formed in the substrate;
forming a plurality of rows of control gate layers on the shallow slot isolation structure, wherein two adjacent rows of control gate layers are arranged in a staggered manner, each row of control gate layer comprises a plurality of control gates, a first isolation structure and a second isolation structure which are alternately arranged along the row direction are formed on the control gate layers, the first isolation structure is narrower than the second isolation structure in the row direction, each control gate crosses over the first isolation structure, and two adjacent control gates in the same row are separated by the second isolation structure;
forming contact holes at two ends of each control gate, wherein one contact hole is close to the first isolation structure, the other contact hole is close to the second isolation structure, and the projection area of each contact hole on the substrate is smaller than that of each control gate on the substrate;
and connecting all contact holes of each row of control gate layers in series, detecting the total resistance of each row of contact holes, and judging whether the displacement between the contact holes and the control gates meets the control requirements or not by comparing the total resistances of two adjacent rows of contact holes.
2. The method of detecting alignment shift according to claim 1, wherein when the total resistance of two adjacent columns of contact holes is equal, the contact holes are aligned with the control gate; and when the total resistance of the two adjacent rows of contact holes is not equal, the contact holes and the control grid are shifted.
3. The method of claim 2, wherein the direction of shift between each contact hole and each control gate is obtained by comparing the total resistance of two adjacent columns of contact holes.
4. The method of detecting alignment shift of claim 1, wherein the method of forming the first isolation structure, the second isolation structure and the control gate layer comprises:
forming a control gate polysilicon layer on the shallow trench isolation structure;
etching the control gate polysilicon layer until the shallow trench isolation structure is exposed, and forming multiple rows of first openings in an inverted Z shape;
forming a dielectric layer, wherein the dielectric layer covers the control gate polysilicon layer, and second openings and third openings which are alternately arranged along the row direction are formed in the dielectric layer, and the section width of each second opening is larger than that of each third opening;
forming side walls on the side walls of the second opening and the third opening, wherein the bottom wall of the third opening is completely covered by the side walls, and part of the bottom wall of the second opening is covered by the side walls;
etching the control gate polysilicon layer below the bottom wall of the second opening by using the side wall as a mask, and filling the second opening;
and removing the dielectric layer, protecting the row of control gate polycrystalline silicon layers in the first opening, removing the rest control gate polycrystalline layers, and forming the first isolation structure, the second isolation structure and the rows of control gate layers.
5. The method of detecting alignment shift as claimed in claim 4, wherein the number of the first openings in each column is plural, and the plural first openings are arranged in an array.
6. The method of claim 4, wherein a material filling the second opening is the same as a material of the sidewall.
7. The method of claim 6, wherein the material filling the second opening and the material of the sidewall spacers comprise one or more of silicon oxide, silicon nitride, or silicon oxynitride.
8. The method of detecting alignment shift as claimed in claim 6, wherein the width of the first isolation structure is equal to the width of the third opening, and the width of the second isolation structure is equal to the width of the second opening.
9. The method of detecting alignment shift according to claim 4, wherein the method of forming contact holes at both ends of each of the control gates comprises:
forming a silicon oxide layer, wherein the silicon oxide layer covers the substrate and the multiple rows of control gate layers;
etching the silicon oxide layer until two ends of each control gate are exposed to form a through hole;
and filling a conductive material in the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810482595.7A CN108695185B (en) | 2018-05-18 | 2018-05-18 | Method for detecting alignment shift |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810482595.7A CN108695185B (en) | 2018-05-18 | 2018-05-18 | Method for detecting alignment shift |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108695185A CN108695185A (en) | 2018-10-23 |
| CN108695185B true CN108695185B (en) | 2020-07-17 |
Family
ID=63847219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810482595.7A Active CN108695185B (en) | 2018-05-18 | 2018-05-18 | Method for detecting alignment shift |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108695185B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110058486B (en) * | 2019-03-26 | 2022-06-28 | 云谷（固安）科技有限公司 | Mask plate assembly and detection method for splicing precision of mask plate assembly |
| CN110349960B (en) * | 2019-07-08 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | Layout structure of embedded flash memory, embedded flash memory and forming method thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376601A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Detection method and structure for deviation of contact hole |
| CN102543740A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for improving alignment uniformity between polycrystalline silicon gate and contact hole |
| CN102723294A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Method for detecting registration between contact hole and polycrystalline silicon gate |
| CN103346107A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon grid and contact hole |
| CN103346100A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between contact hole and polycrystalline silicon grid |
| CN103354211A (en) * | 2013-06-25 | 2013-10-16 | 上海华力微电子有限公司 | Method for measuring and calculating alignment deviation of contact holes and polycrystalline silicon gates |
| CN204045551U (en) * | 2014-09-04 | 2014-12-24 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN204216010U (en) * | 2014-09-04 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN104600032A (en) * | 2014-12-31 | 2015-05-06 | 北京兆易创新科技股份有限公司 | Manufacture method of NOR gate flash memory |
| CN105118794A (en) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | Structure for testing contact resistance of sharing contact holes of SRAM and polycrystalline silicon |
-
2018
- 2018-05-18 CN CN201810482595.7A patent/CN108695185B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376601A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Detection method and structure for deviation of contact hole |
| CN102543740A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for improving alignment uniformity between polycrystalline silicon gate and contact hole |
| CN102723294A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Method for detecting registration between contact hole and polycrystalline silicon gate |
| CN103354211A (en) * | 2013-06-25 | 2013-10-16 | 上海华力微电子有限公司 | Method for measuring and calculating alignment deviation of contact holes and polycrystalline silicon gates |
| CN103346107A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon grid and contact hole |
| CN103346100A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between contact hole and polycrystalline silicon grid |
| CN204045551U (en) * | 2014-09-04 | 2014-12-24 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN204216010U (en) * | 2014-09-04 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | Contact hole side-play amount geodesic structure |
| CN104600032A (en) * | 2014-12-31 | 2015-05-06 | 北京兆易创新科技股份有限公司 | Manufacture method of NOR gate flash memory |
| CN105118794A (en) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | Structure for testing contact resistance of sharing contact holes of SRAM and polycrystalline silicon |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108695185A (en) | 2018-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2018161832A1 (en) | Trench structures for three-dimensional memory devices | |
| US11968835B2 (en) | Vertical type semiconductor devices and methods of manufacturing the same | |
| US20050201155A1 (en) | Memory device and fabrication method thereof | |
| US8058734B2 (en) | Semiconductor device and method of manufacturing the same | |
| US8592978B2 (en) | Method of fabricating semiconductor device and the semiconductor device | |
| US6706579B2 (en) | Method of manufacturing semiconductor device | |
| US10825830B2 (en) | Vertical semiconductor devices | |
| CN108695185B (en) | Method for detecting alignment shift | |
| KR20160109988A (en) | Semiconductor devices and methods of manufacturing the same | |
| US9508732B2 (en) | Semiconductor devices including a gate electrode and methods of manufacturing the same | |
| US20050105332A1 (en) | Memory device and fabrication method thereof | |
| US7400010B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN108831842B (en) | Method for detecting alignment shift | |
| US7674679B2 (en) | Manufacturing method of semiconductor device and semiconductor device | |
| US8836008B2 (en) | Semiconductor device and method of manufacturing same | |
| US11637125B2 (en) | Memory device | |
| US7592036B2 (en) | Method for manufacturing NAND flash memory | |
| US20080017916A1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100611065B1 (en) | Semiconductor memory device having a cell region and a dummy pattern region and the method thereof. | |
| CN105280590B (en) | Semiconductor structure and its manufacturing method | |
| TWI822415B (en) | 3d memory device and method of forming seal structure | |
| US8236664B2 (en) | Phase change memory device accounting for volume change of phase change material and method for manufacturing the same | |
| US7316956B2 (en) | Method for fabricating semiconductor device and wire with silicide | |
| KR19980079122A (en) | A semiconductor device having a projecting structure and a method of manufacturing the same | |
| TW202205624A (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |