CN105118794A - Structure for testing contact resistance of sharing contact holes of SRAM and polycrystalline silicon - Google Patents
Structure for testing contact resistance of sharing contact holes of SRAM and polycrystalline silicon Download PDFInfo
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- CN105118794A CN105118794A CN201510435944.6A CN201510435944A CN105118794A CN 105118794 A CN105118794 A CN 105118794A CN 201510435944 A CN201510435944 A CN 201510435944A CN 105118794 A CN105118794 A CN 105118794A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
A structure for testing contact resistance of sharing contact holes of a Static Random Access Memory (SRAM) and a polycrystalline silicon includes an SRAM memory cell array and a boundary unit. The boundary unit is used for leading out trap potential and is taken as the environment of the SRAM memory cell array. Moreover the SRAM memory cell array includes a plurality of array units. Each array unit includes four remodeling SRAM memory cell layout structures which are arranged according to a mirror left-right mode and a mirror up-down mode. Each remodeling SRAM memory cell layout structure contains and only contains one sharing contact hole. In each array unit, the first polycrystalline silicon connected to the sharing contact hole of each remodeling SRAM memory cell layout structure and the second polycrystalline silicon connected to the sharing contact hole of the other remodeling SRAM memory cell layout structure symmetrical with the adjacent mirror at a first side are bent toward each other, so that the first polycrystalline silicon and the second polycrystalline silicon are connected to each other. Bending portions of the polycrystalline silicon are ensured to be located entirely in the P type injection zone.
Description
Technical field
The present invention relates to semiconductor test field, more particularly, the present invention relates to the structure that a kind of SRAM of test shares contact hole and polysilicon contact resistance.
Background technology
SRAM (StaticRandomAccessMemory) i.e. static random access memory, without refresh circuit, speed is fast, is usually used in the memory of various integrated circuit.
Fig. 1 is the schematic diagram of the memory cell of a 6TSRAM, is made up of 4 NMOST1, T2, Q1, Q2 and 2 PMOSQ3, Q4.Wherein the input of Q3, Q1 and the output of Q4, Q2 connect together, and the input of Q4, Q2 and the output of Q3, Q1 connect together, and form a latch.Wherein, T1, T2 are two transfer tubes.
Along with the reduction of integrated circuit live width, the raising of integrated level, generally for and reduce SRAM chip area, introduce shared contact hole and the output drain electrode of the input grid of Q3, Q1 and Q4, Q2 connected together, the in like manner grid of Q4, Q2 and the drain electrode of Q3, Q1 connects together.As shown in Figure 2, wherein 1 is active area to the domain of 6TSRAM memory cell, active area 1 is coated with metal silicide, separates between active area by oxidization isolation layer; 2 is grid polycrystalline silicon, and polysilicon is coated with metal silicide; 3 is erose shared contact hole, a part and active region contact, and a part contacts with grid polycrystalline silicon, has 2 shared contact holes in a memory cell; 4 is foursquare Conventional contact hole; 5 is N-type injection region, and T1, T2, Q1, Q2 are included in wherein, is NMOS; 6 is P type injection region, and Q3, Q4 are included in wherein, is PMOS.
This shared contact hole shape is different from common contact hole dimension, and a part contacts a part and contacts with grid polycrystalline silicon with drain active district, even some directly contacts with oxidization isolation layer.Its contact environment relative complex, and density is very high, plays very large impact to the finished product yield that SRAM manufactures.So the contact resistance that monitoring SRAM shares contact hole is extremely important.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, a kind of SRAM of test is provided to share the structure of contact hole and polysilicon contact resistance, this structure can share the contact resistance of contact hole and polysilicon in effective monitoring SRAM manufacture technics, can some problems in effective monitoring SRAM manufacture.
In order to realize above-mentioned technical purpose, according to the present invention, providing the structure that a kind of SRAM of test shares contact hole and polysilicon contact resistance, comprising: SRAM memory cell array and boundary element; Wherein, described boundary element is used for trap potential to pick out, simultaneously as the environment of SRAM memory cell array; And described SRAM memory cell array comprises multiple array element, wherein each array element comprises according to left and right mirror image and upper and lower four remodeling SRAM memory cell domain structures arranging of the mode of mirror image; Each remodeling SRAM memory cell domain structure comprises and only comprises a shared contact hole.
Preferably, in each array element, the second polysilicon that the first polysilicon that the shared contact hole of each remodeling SRAM memory cell domain structure connects is connected with the shared contact hole of another SRAM memory cell domain structure of retrofiting of the adjacent specular of the first side bends towards each other, to make described first polysilicon and described second polysilicon be interconnected, and ensure that polysilicon sweep is in P type injection region completely.
Preferably, in each array element, the shared contact hole of each remodeling 6TSRAM memory cell domain structure connects the shared contact hole with the remodeling 6TSRAM memory cell domain structure of the adjacent specular of the second side by metal line.
Preferably, the first side is relative with the second side.
Preferably, other contact hole except sharing contact hole in each remodeling SRAM memory cell domain structure is set to floating state.
Preferably, other contact hole except sharing contact hole in each remodeling SRAM memory cell domain structure is set up and is covered, typically with metal layers covering.
Preferably, described boundary element surrounds described SRAM memory cell array.
Preferably, described remodeling SRAM memory cell domain structure is the remodeling SRAM memory cell domain structure of 6TSRAM memory cell.
Preferably, share a contact hole part and active region contact, and a shared contact hole part contacts with grid polycrystalline silicon.
Preferably, comprise by the part of grid pole polysilicon in removal complete S ram memory cell domain structure and corresponding contact hole of sharing to make each remodeling SRAM memory cell domain structure and only comprise a shared contact hole.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the schematic diagram of the memory cell of 6TSRAM.
Fig. 2 schematically shows the domain of 6TSRAM memory cell.
Fig. 3 schematically shows the schematic diagram of SRAM leakage tests structure.
Fig. 4 schematically shows and tests the schematic diagram that SRAM shares the structure of contact hole and polysilicon contact resistance according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
The present invention is on the basis of conventional SRAM leakage tests structure, a small amount of variation is carried out to the structure of memory cell, and its metal connecting line of corresponding change and polysilicon wire, make it to become the chain test structure surveyed and share contact hole and polysilicon contact resistance, can the all-in resistance of surveyor's chain shape test structure and the contact resistance of single contact hole and polysilicon, thus the contact situation sharing contact hole and polysilicon can be simulated during SRAM manufactures more accurately, and manufacture with this monitoring process.Further, the environment that this test structure shares contact hole is identical with the SRAM memory in IC manufacturing, better can monitor during SRAM manufactures the problem caused by shared contact hole.
Particularly, Fig. 3 shows and is applied to SRAM leakage tests structural representation of the present invention equally, comprises SRAM memory cell array 7 and boundary element 8; Boundary element 8 is mainly used in trap potential to pick out, simultaneously such as, as the environment (particularly, as shown in Figure 3, boundary element 8 surrounds SRAM memory cell array 7) of SRAM memory cell array 7.
Representation 6TSRAM memory cell domain 9, the 6TSRAM memory cell domain 9 of single " F " printed words representative is according to left and right mirror image and the mode of upper and lower mirror image is arranged in an array element, and this array element constantly repeats to obtain SRAM memory cell array 7.
In other words, SRAM memory cell array 7 comprises multiple array element, and wherein each array element comprises according to left and right mirror image and upper and lower four 6TSRAM memory cell domains 9 arranging of the mode of mirror image.
Fig. 4 is the domain schematic diagram of test structure of the present invention.As shown in Figure 4, in the present invention, 6TSRAM memory cell domain 9 adopts the remodeling 6TSRAM memory cell domain structure in the region representated by reference number 10 (part in Fig. 4 beyond 10 be namely with remodeling 6TSRAM memory cell domain structure 10 another 6TSRAM memory cell domain structure of retrofiting at upper and lower specular).
Each remodeling 6TSRAM memory cell domain structure according to the present invention comprises and only comprises a shared contact hole.As mentioned above, share a contact hole part and active region contact, and a shared contact hole part contacts with grid polycrystalline silicon.
And in each array element, the second polysilicon 13 that the first polysilicon 12 that each shared contact hole of retrofiting 6TSRAM memory cell domain structure connects is connected with another shared contact hole of retrofiting 6TSRAM memory cell domain structure of the adjacent specular of the first side bends towards each other, to make described first polysilicon 12 and described second polysilicon 13 be interconnected, and ensure that polysilicon sweep is in P type injection region completely.And the shared contact hole of each remodeling 6TSRAM memory cell domain structure connects the shared contact hole with the remodeling 6TSRAM memory cell domain structure of the adjacent specular of the second side by metal line.
Preferably, the first side is relative with the second side, such as up and down relatively or left and right relative.
Fig. 4 shows a kind of situation, wherein goes up a metal line 11 and is linked together by the shared contact hole of the remodeling 6TSRAM memory cell domain structure in dotted line frame and the remodeling 6TSRAM memory cell domain structure above it; The shared contact hole of the remodeling 6TSRAM memory cell domain structure outside dotted line frame in accompanying drawing and the remodeling 6TSRAM memory cell domain structure below it links together by next metal line 11.
And other contact hole except sharing contact hole in each remodeling 6TSRAM memory cell domain structure is set to floating state.
In the present invention, can comprise to make each remodeling SRAM memory cell domain structure and only comprise a shared contact hole by the part of grid pole polysilicon (and partial sharing contact hole) removed in complete S ram memory cell domain structure.
Specifically, the present invention, on the SRAM leakage tests architecture basics of Fig. 3, to the 6TSRAM memory cell correct shown in Fig. 2, removes Q1, Q3 or Q2, any grid polycrystalline silicon of Q4 and shared contact hole.This sentences the grid polycrystalline silicon that removes Q1 and Q3 and shared contact hole is example, and by Q2, the polysilicon of Q4 bends, polysilicon bending with adjacent unit like this couples together, and ensure polysilicon completely in P type injection region, with metal level, the shared contact hole that the shared contact hole in remodeling 6TSRAM memory cell domain structure 10 and opposite side close on memory cell is linked together, the contact hole of other routine covers and floating with metal level, environment when manufacturing with maximum approximate simulation SRAM memory, and arrange by the mode of Fig. 3, obtain a chain structure of " sharing contact-metal level-shared contact hole-polycide-shared contact hole ", the contact situation that SRAM shares contact hole and polysilicon can be monitored by test resistance.
Obviously, the present invention is not limited only to the domain structure shown in Fig. 2 and Fig. 4, also comprises the chain test structure of all shared contact holes of changing on SRAM test structure basis based on inventive concept and polysilicon contact resistance.Such as, except being applicable to remodeling 6TSRAM memory cell domain structure 10, can also be applicable to non-6TSRAM memory cell, can be the remodeling SRAM memory cell domain structure of the SRAM memory cell that other quantity transistor is formed.
It should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. test the structure that SRAM shares contact hole and polysilicon contact resistance, it is characterized in that comprising: SRAM memory cell array and boundary element; Wherein, described boundary element is used for trap potential to pick out, simultaneously as the environment of SRAM memory cell array; And described SRAM memory cell array comprises multiple array element, wherein each array element comprises according to left and right mirror image and upper and lower four remodeling SRAM memory cell domain structures arranging of the mode of mirror image; Each remodeling SRAM memory cell domain structure comprises and only comprises a shared contact hole; In each array element, the second polysilicon that the first polysilicon that the shared contact hole of each remodeling SRAM memory cell domain structure connects is connected with the shared contact hole of another SRAM memory cell domain structure of retrofiting of the adjacent specular of the first side bends towards each other, to make described first polysilicon and described second polysilicon be interconnected, and ensure that polysilicon sweep is in P type injection region completely.
2. test SRAM according to claim 1 shares the structure of contact hole and polysilicon contact resistance, it is characterized in that, in each array element, the shared contact hole of each remodeling 6TSRAM memory cell domain structure connects the shared contact hole with the remodeling 6TSRAM memory cell domain structure of the adjacent specular of the second side by metal line.
3. test SRAM according to claim 2 shares the structure of contact hole and polysilicon contact resistance, and it is characterized in that, the first side is relative with the second side.
4. share the structure of contact hole and polysilicon contact resistance according to the test SRAM one of claims 1 to 3 Suo Shu, it is characterized in that, other contact hole except sharing contact hole in each remodeling SRAM memory cell domain structure is set to floating state.
5. the structure of contact hole and polysilicon contact resistance is shared according to the test SRAM one of claims 1 to 3 Suo Shu, it is characterized in that, other contact hole except sharing contact hole in each remodeling SRAM memory cell domain structure is set up and is covered, typically with metal layers covering.
6. share the structure of contact hole and polysilicon contact resistance according to the test SRAM one of claims 1 to 3 Suo Shu, it is characterized in that, described boundary element surrounds described SRAM memory cell array.
7. test SRAM according to claim 1 and 2 shares the structure of contact hole and polysilicon contact resistance, and it is characterized in that, described remodeling SRAM memory cell domain structure is the remodeling SRAM memory cell domain structure of 6TSRAM memory cell.
8. share the structure of contact hole and polysilicon contact resistance according to the test SRAM one of claims 1 to 3 Suo Shu, it is characterized in that, share a contact hole part and active region contact, and a shared contact hole part contacts with grid polycrystalline silicon.
9. the structure of contact hole and polysilicon contact resistance is shared according to the test SRAM one of claims 1 to 3 Suo Shu, it is characterized in that, comprise by the part of grid pole polysilicon in removal complete S ram memory cell domain structure and corresponding contact hole of sharing to make each remodeling SRAM memory cell domain structure and only comprise a shared contact hole.
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| CN201510435944.6A CN105118794B (en) | 2015-07-22 | 2015-07-22 | A kind of test SRAM shares the structure of contact hole and polysilicon contact resistance |
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| CN201510435944.6A CN105118794B (en) | 2015-07-22 | 2015-07-22 | A kind of test SRAM shares the structure of contact hole and polysilicon contact resistance |
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| CN105118794B CN105118794B (en) | 2018-02-09 |
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Cited By (4)
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| CN105895586A (en) * | 2016-05-13 | 2016-08-24 | 武汉新芯集成电路制造有限公司 | Method for adding shared contact hole process window |
| CN109559778A (en) * | 2018-11-30 | 2019-04-02 | 上海华力微电子有限公司 | SRAM tests structure |
| CN111129005A (en) * | 2019-12-25 | 2020-05-08 | 上海华力集成电路制造有限公司 | Layout structure of double-port static random access memory unit |
| CN108695185B (en) * | 2018-05-18 | 2020-07-17 | 上海华虹宏力半导体制造有限公司 | Method for detecting alignment shift |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105895586A (en) * | 2016-05-13 | 2016-08-24 | 武汉新芯集成电路制造有限公司 | Method for adding shared contact hole process window |
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| CN108695185B (en) * | 2018-05-18 | 2020-07-17 | 上海华虹宏力半导体制造有限公司 | Method for detecting alignment shift |
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| CN111129005A (en) * | 2019-12-25 | 2020-05-08 | 上海华力集成电路制造有限公司 | Layout structure of double-port static random access memory unit |
| CN111129005B (en) * | 2019-12-25 | 2023-09-19 | 上海华力集成电路制造有限公司 | Layout structure of dual-port static random access memory unit |
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| CN105118794B (en) | 2018-02-09 |
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