JP3237630B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), and more particularly to an excimer laser annealing (E).
The present invention relates to a polysilicon TFT obtained by converting amorphous silicon into polysilicon by LA).

[0002]

2. Description of the Related Art In order to improve the performance and definition of amorphous silicon TFTs, which have been developed and put into practical use as switching elements of LCDs, and to realize circuit formation on a glass substrate, many transistors are used in the active layer of a transistor. A polysilicon TFT using crystalline silicon has been developed. Since polycrystalline silicon used for the active layer is a crystalline material, the mobility thereof is 10 times higher than that of amorphous silicon which is an amorphous material.
There is an advantage that it is about 0 times higher.

Here, a conventional method of manufacturing a polysilicon TFT will be described with reference to FIGS. First, the LPCVD method or the PE
A silicon oxide film layer 11 is formed by a CVD method (FIG. 5).
(See FIG. 5B), and an amorphous silicon layer 13 is formed thereon by an LPCVD method or a plasma CVD method (see FIG. 5C). Next, as shown in FIG.
Excimer laser annealing is performed to crystallize a predetermined region of the amorphous silicon layer 13 to form a polysilicon layer 15.
To form Thereafter, a gate oxide film 16 is formed (FIG. 5).
(See (e)), etching is performed by dry etching until the silicon oxide film layer 11 is exposed, and the polysilicon layer 15 is divided into island shapes.

In the polysilicon TFT manufactured by the above steps, the amorphous silicon layer 13 is exposed at the time of ELA, so that irregularities are formed on the surface of the crystallized polysilicon layer 15. Therefore, a method of forming a cap layer is used to prevent this. In this method, a silicon oxide film layer is formed as a cap film on the amorphous silicon layer before the ELA is performed, and annealing is performed. Two advantages are obtained, namely, suppression of variation in particle diameter and reduction of surface roughness.

A method of manufacturing a polysilicon TFT for performing ELA by forming a cap layer will be described with reference to FIGS. First, after a silicon oxide film layer 11 is formed on a glass substrate 10 by LPCVD or PECVD (see FIG. 6B), LPCVD or plasma C
The amorphous silicon layer 13 is formed by the VD method (FIG. 6)
(C)). Further, a silicon oxide film layer 14 serving as a cap layer is formed thereon by LPCVD or plasma CVD.
Is formed, a cap annealing is performed by ELA, and a predetermined region of the amorphous silicon layer 13 is crystallized,
A polysilicon layer 15 is formed. Thereafter, the silicon oxide film layer 14 is removed by etching (see FIG. 7 (f)), the polysilicon layer 15 in the opening region is removed by dry etching, and the polysilicon layer 15 is divided into islands.

[0006]

However, in the case of a conventional polysilicon TFT, in the case of a display device such as an LCD which uses a backlight to secure brightness, a region other than the TFT device forming region on the glass substrate is used. That is, there is a problem that the light transmittance in the opening is reduced, and the luminance at the time of displaying is reduced.

The reason is that when the polysilicon layer 15 is dry-etched, the underlying silicon oxide film layer 11 is removed.
In addition, the interface between the polysilicon layer 15 and the underlying film is uneven due to the movement of silicon atoms during ELA. Therefore, the surface of the silicon oxide film layer 11 has many irregularities as shown in FIG. 5 (f) and a partially enlarged view (f ′) of FIG. 5 (f). This is because the unevenness remains to the end, and the light transmittance at the opening is reduced.

In the case of the cap annealing method, a wiring layer formed on a region where the polysilicon layer 15 is removed is formed of an EL.
In the case of A, there is a problem that the wire is disconnected due to the depression caused by the pinhole 24 generated in the polysilicon layer 15.

The reason for this is that, as shown in FIG. 7F, when the silicon oxide film layer 14 serving as the cap layer is removed by etching, the etching solution passes through the pinholes generated in the polysilicon layer 17 and then drops. The silicon oxide film layer 11 made of the same material as the cap layer is also etched into the ground film to form a hollow portion 21. In the subsequent steps, the hollow portion 21 remains as the concave portion 22, and FIG.
This is because the aluminum wiring is disconnected as shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its main objects to improve the light transmittance in an opening portion and to maintain the flatness of a wiring forming portion even when cap annealing is performed. An object of the present invention is to provide a polysilicon TFT which can be ensured and does not cause breakage of aluminum wiring, and a method of manufacturing the same.

[0011]

In order to achieve the above object, the present invention provides a substrate having a first insulating layer, a second insulating layer, an amorphous silicon layer, and a cap layer laminated in this order. A polysilicon TFT in which the amorphous silicon layer is converted to a polysilicon layer by performing an ELA process through the cap layer, wherein the opening is formed by removing a predetermined region of the polysilicon layer. In the region, the second insulating film has been removed.

[0012] In the present invention, the second insulating layer comprises:
It is preferable that the first insulating layer is made of a material having resistance to an etchant of the cap layer, and the first insulating layer is made of a material having an etch rate of 1/10 or less with respect to the etchant of the second insulating layer. The thickness of the second insulating layer may be set to a thickness larger than the unevenness formed at the interface with the polysilicon during ELA, preferably 50 nm or more.

The manufacturing method of the present invention comprises the steps of:
(B) forming a second insulating layer on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer.
Forming an amorphous silicon layer on the insulating layer, (d) converting the amorphous silicon layer into a polysilicon layer by ELA, and (e) forming a predetermined region of the polysilicon in the second Forming the active region by dry etching until the first insulating layer is exposed; and (f) wet-etching the second insulating layer other than the active region until the first insulating layer is exposed. Removing step.

Further, according to the manufacturing method of the present invention, (a) a step of forming a first insulating layer on a substrate; and (b) a second insulating layer is formed on the first insulating layer. (C) forming an amorphous silicon layer on the second insulating layer, (d) forming a cap layer on the amorphous silicon layer, and (e) forming the cap layer. Converting the amorphous silicon layer into a polysilicon layer by ELA, and (f) removing the cap layer by wet etching,
(G) removing a predetermined region of the polysilicon by dry etching until the second insulating layer is exposed to form an active region; and (h) forming the second insulating layer other than the active region. a look-containing and a step of removing by wet etching until the first insulating layer is exposed, the
A second insulating layer is provided for the cap layer etchant.
And the first insulating layer is made of a material having high resistance.
The etch rate is 1 for the etchant of the second insulating layer.
/ 10 or less .

In the present invention, the first insulating layer includes:
The cap layer is made of a silicon oxide film;
Preferably, the insulating layer is made of a silicon nitride film.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A polysilicon TFT according to the present invention
In a preferred embodiment, a silicon oxide film layer (FIG. 3E) is formed on a glass substrate (10 in FIG. 3E).
11 (e) and a silicon nitride film layer (1 in FIG. 3 (e)).
2) and an amorphous silicon layer (13 in FIG. 3E)
And a cap layer (14 in FIG. 3 (e)) are laminated in this order, and the polysilicon TFT (15 in FIG. 3 (f)) is formed by performing an ELA process through the cap layer. Then, after ELA, the silicon nitride film layer is removed by wet etching.

According to the structure of the present invention, the polysilicon TF
Before the ELA step in forming T, a silicon nitride film layer is inserted between the polysilicon layer and the silicon oxide film layer,
After the polysilicon layer is removed by dry etching in the island etching step, the silicon nitride film layer immediately below the polysilicon layer is removed by wet etching. As described above, the surface of the silicon oxide film layer can be flattened by removing the silicon nitride film layer having an uneven surface during the ELA and the dry etching of the polysilicon layer. In this case, it is possible to prevent a decrease in transmittance at the opening.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] A polysilicon TFT according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are process cross-sectional views for schematically explaining a method for manufacturing a polysilicon TFT.

First, as shown in FIG. 1B, a silicon oxide film (SiO
x) The layer 11 is formed. This silicon oxide film layer 11
It is formed by LPCVD or plasma CVD using SiH ₄ and O ₂ or Si ₂ H ₆ and O ₂ as source gases. The substrate temperature at this time is 400 ° C. or less for LPCVD,
In the case of plasma CVD, the temperature is set to 350 ° C. or less.

Next, as shown in FIG. 1C, a silicon nitride (SiNx) layer 12 is formed on the silicon oxide film layer 11.
To form The etching rate of the silicon nitride film layer 12 with respect to buffered hydrofluoric acid is equal to or less than 1/10 of the etching rate with respect to the silicon oxide film layer 11, and the film thickness is formed at the interface between the polysilicon layer 14 and the silicon nitride film layer 12, which will be described later. 5 so that it is sufficiently large
Preferably, the thickness is 0 nm or more.

Next, as shown in FIG. 1D, an amorphous silicon (amorphous silicon) layer 13 is formed on the silicon nitride film layer 12. The amorphous silicon layer 13 is formed by LPCVD using Si ₂ H ₆ as a source gas, and has a thickness of about 50 to 75 nm. At this time, the substrate temperature is set to about 450 ° C. Then, the amorphous silicon layer 13 is formed by excimer laser annealing (ELA).
Is crystallized to form a polycrystalline silicon (polysilicon) layer 15. Here, when the polysilicon layer 15 is formed by ELA, irregularities having a height of about 10 nm due to the movement of silicon atoms are formed at the interface between the polysilicon layer 15 and the silicon nitride film layer 12 which is the underlying layer. You.

Next, after forming the gate oxide film 16 (see FIG. 2F), the gate oxide film layer 16 in a predetermined region is removed by wet etching so that the island-shaped polysilicon layer 17 remains. Then, the polysilicon layer 15 is etched by dry etching until the silicon nitride film layer 12 is exposed (see FIG. 2G). At this time, irregularities are further formed on the surface of the silicon nitride film layer 12 due to the damage of the dry etching. Subsequently, as shown in FIG. 2H, when the silicon nitride film layer 12 is removed by wet etching to expose the silicon oxide film layer 11,
As shown in (h '), which is a partially enlarged view of (h), a polysilicon TFT having a flat opening with a surface unevenness of 1 nm or less can be manufactured.

As described above, in this embodiment, the silicon nitride film layer 12 is inserted between the polysilicon layer 15 and the silicon oxide film layer 11, and the polysilicon layer 15 is dry-etched during island etching. The surface of the silicon oxide film layer 11 is exposed by removing the silicon nitride film layer 12 by wet etching. Here, the surface of the silicon nitride film layer 12 is
Although the surface roughness is increased due to the damage of the dry etching of No. 5, since the silicon nitride film layer 12 is removed by wet etching, the surface of the silicon oxide film layer 11 can be kept flat. Therefore, there is no surface roughness at the surface of the opening that reduces the light transmittance due to scattering, and an effect that good display characteristics can be obtained is obtained. When comparing the case where the irregularities formed at the interface between the opening formed by the manufacturing method of the present embodiment and the silicon oxide film layer 11 remain as they are, the transmittance in the present embodiment is improved by about 30% as compared with the conventional case. I have.

The etch rate of the silicon oxide film layer 11 with respect to the etchant for the silicon nitride film layer 12 is as follows:
The etching is stopped at the interface between the silicon nitride film layer 12 and the silicon oxide film layer 11 by selecting a material that is about 1/10 or less of the etch rate of the silicon nitride film layer 12, and the silicon oxide film layer 11 is etched. The surface flatness can be maintained without performing.

Embodiment 2 Next, a polysilicon TFT according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 are process cross-sectional views for schematically explaining a method for manufacturing a polysilicon TFT according to the second embodiment.

As in the first embodiment, a silicon oxide film 11, a silicon nitride film 12,
The amorphous silicon 13 is laminated in this order (FIG. 3
(D)). Next, as shown in FIG. 3E, a silicon oxide film (SiOx film) layer 14 is formed on the amorphous silicon layer 13 as a cap film, and ELA is formed thereon.
To form a polysilicon layer 15 (see FIG. 3F).

The thickness of the silicon oxide film layer 14 is EL
In the case of A, a film thickness that allows the laser energy to be transmitted to the amorphous silicon layer 13 most efficiently is selected. For example, when using an excimer laser having a wavelength of 308 nm,
The thickness of the silicon oxide film layer 14 at which the efficiency is highest is about 50 nm. Also in the case where the polysilicon layer 15 is formed by cap annealing, unevenness having a height of about 10 nm is formed at the interface between the silicon nitride film layer 12 and the polysilicon layer 15 which are the underlying layers of the polysilicon layer 15.

Next, the silicon oxide film layer 14 is removed by etching with buffered hydrofluoric acid (see FIG. 4G), and after forming a gate oxide film 16 (see FIG. 4H), the polysilicon layer 15 is removed. Etching is performed to form an island-shaped polysilicon 16 and an opening 17 which are to be active layers of the TFT (see FIG. 4I). At this time, the gate oxide film 16 → the polysilicon layer 15
→ By etching in the order of the silicon nitride film layer 12,
All of the irregularities having a height of about 10 nm at the interface between the polysilicon layer 15 and the silicon nitride film layer 12 are removed, and a flat opening having a surface irregularity of 1 nm or less is formed.

In the case where the polysilicon layer 15 is formed by cap annealing, when the ELA intensity exceeds a certain level, the hollow portion 21 is formed in the polysilicon layer 15.
Is formed. Since this energy intensity is just above the ELA intensity for obtaining a good crystalline polysilicon layer 15, when a laser intensity variation occurs, a good TF
A hollow portion 21 is formed in the polysilicon layer 15 where the T characteristic is obtained.
Is likely to exist. When the silicon oxide film layer 14 of such a structure is removed by etching with buffered hydrofluoric acid, if the silicon nitride film layer 12 is present between the polysilicon layer 15 and the silicon oxide film layer 11 as in this embodiment. Also, even when buffered hydrofluoric acid enters from the cavity 21, the silicon nitride film layer 12 is not etched, and does not adversely affect the subsequent steps.

On the other hand, as shown in FIG. 6, when only the silicon oxide film layer 11 is provided between the polysilicon layer 15 and the glass substrate 10, buffered hydrofluoric acid penetrates from the hollow portion 21 and the silicon oxide film Layer 11 will be etched. For this reason, when the opening 17 is formed, a large concave portion 22 is present, which greatly affects the shape when the interlayer insulating film layer 19 and the aluminum wiring 20 are formed in the subsequent steps. In particular, when forming the aluminum wiring 20,
As shown in FIG. 6 (h '), this causes the aluminum break 23. That is, in this embodiment, the silicon oxide film layer 12 makes it difficult for the aluminum wiring 20 to be disconnected, and the reliability of the device can be improved.

[0032]

As described above, according to the present invention,
There is no surface roughness at the surface of the opening that reduces light transmittance due to scattering, and an effect is obtained that a polysilicon TFT that can obtain good display characteristics can be manufactured.

The reason is that the underlying film of the polysilicon layer is
Irregularities due to the movement of silicon atoms occur during ELA, and damage is caused when the polysilicon layer is removed by dry etching, and the surface is further roughened. However, in the present invention, the polysilicon layer and the glass layer are formed on the glass substrate. A silicon nitride film layer is inserted between the silicon oxide film layers,
This is because the silicon nitride film layer is removed by wet etching after the removal of the polysilicon layer, so that the silicon oxide film layer having a flat surface can be exposed.

Further, according to the present invention, it is possible to prevent a disconnection of a wiring caused by a pinhole generated in a polysilicon layer during ELA using cap annealing.

The reason is that, when the cap layer is wet-etched, even if the etchant penetrates through the pinholes, the silicon nitride film as the underlying film of the polysilicon layer is not etched, so that no cavity is formed. It is.

[Brief description of the drawings]

FIG. 1 shows a polysilicon TF according to a first embodiment of the present invention.
It is a process sectional view for explaining typically the manufacturing method of T.

FIG. 2 shows a polysilicon TF according to the first embodiment of the present invention.
It is a process sectional view for explaining typically the manufacturing method of T.

FIG. 3 is a process cross-sectional view for schematically explaining a method for manufacturing a polysilicon TFT using cap annealing according to a second embodiment of the present invention.

FIG. 4 is a process cross-sectional view for schematically explaining a method of manufacturing a polysilicon TFT using cap annealing according to a second embodiment of the present invention.

FIG. 5 is a process sectional view showing a conventional method for manufacturing a polysilicon TFT.

FIG. 6 is a process sectional view showing a method for manufacturing a polysilicon TFT using conventional cap annealing.

FIG. 7 is a process sectional view showing a method for manufacturing a polysilicon TFT using conventional cap annealing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Glass substrate 11 Silicon oxide film layer 12 Silicon nitride film layer 13 Amorphous silicon layer 14 Silicon oxide film layer 15 Polysilicon layer 16 Gate oxide film layer 17 Island-like polysilicon layer 18 Opening 19 Silicon nitride film 20 Al wiring 21 Hollow part 22 Recess 23 Aluminum disconnection 24 Pinhole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/336

Claims (2)

(57) [Claims] (A) forming a first insulating layer on a substrate; (b) forming a second insulating layer on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer. Forming an amorphous silicon layer on the second insulating layer; (d) forming a cap layer on the amorphous silicon layer; and (e) forming the amorphous silicon layer through the cap layer. Converting the layer to a polysilicon layer by ELA; (f) removing the cap layer by wet etching; and (g) removing a predetermined region of the polysilicon until the second insulating layer is exposed. Removing by dry etching to form an active region; and (h) removing the second insulating layer other than the active region by wet etching until the first insulating layer is exposed. Only, the second insulating layer serves as an etchant for the cap layer.
The first insulating layer is made of a material resistant to the second insulating layer.
Made of a material whose etch rate is 1/10 or less,
A method for producing a polysilicon TFT. And wherein said first insulating layer, said cap layer is made of silicon oxide film, said second insulating layer is made of a silicon nitride film, a polysilicon TFT of claim 1, wherein the Manufacturing method.