JP3235599B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode is laminated on a semiconductor substrate, for example, a ferroelectric memory. Things.

[0002]

2. Description of the Related Art A ferroelectric has a characteristic that it has a large relative permittivity and has spontaneous polarization, and can be used as a capacitor material in a semiconductor memory. However, Pb
Ferroelectrics such as TiO3, PZT, PLZT and Pt, T
In an etching process using a photoresist of an electrode material such as i, Au, Pd or a compound thereof, the above materials are usually difficult to perform reactive etching, and ion milling has been regarded as the most effective etching method. Ion milling is a method of physically and anisotropically sputter-etching accelerated argon ions, but because of its strong anisotropy and the low reactivity of the material, the material to be etched hardly volatilizes. A part of the object to be etched adheres to the side wall of the resist after being etched to form a side wall deposition film as shown in FIG. The sidewall deposition film remains in the shape shown in FIG. 4 without being removed in the subsequent resist stripping step. Therefore, the side wall deposited film adversely affects the coverage of the interlayer insulating film in the subsequent step of forming the second interlayer insulating film. Further, when the side wall deposited film is conductive, May cause a short circuit or disconnection of the wiring.

After the resist is exposed to light and developed, the resist is reflowed by baking at a temperature of 130 ° C. to 200 ° C., and the resist is vertically tapered by tapering its shape. Has been devised not to have the side wall, and to have the effect of etching the object to be etched once attached to the resist side wall by argon ions coming later, and consequently not to leave the side wall deposition film.

However, in the etching process of the lower electrode after the etching of the ferroelectric film, conventionally, as shown in FIG. 5, the pattern of the lower electrode is about 1 μm outside one side of the mask pattern of the ferroelectric film. Therefore, it has been a great barrier in miniaturization due to the high integration of semiconductor devices. Therefore, the inventor of the present invention has tried a structure in which the pattern widths of the ferroelectric film and the lower electrode film are matched as shown in FIG. However, in a structure in which the pattern widths of the ferroelectric film and the lower electrode film match, the resist is applied to the tapered portion of the side wall of the ferroelectric film due to misalignment, as shown in FIG. 20
After the registry flow at 0 ° C., the shape of the resist was such that the taper angle exceeded 90 degrees, which was called an overhang as shown in FIG. 7B in some cases, and the sidewall deposition film was generated.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a method of etching a lower electrode after etching a ferroelectric film without obstructing miniaturization. An object of the present invention is to provide an etched shape without re-deposition on the side wall of the resist.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a lower electrode; a ferroelectric film formed on the lower electrode; and an upper part formed on the ferroelectric film. Each part of the electrode has a tapered cross-sectional shape on the semiconductor substrate.
A semiconductor device stacked so as to form one outer peripheral end , wherein at least one of the lower electrode and the ferroelectric film, the ferroelectric film and the upper electrode, and the lower electrode and the upper electrode , The upper part is formed smaller than the lower part, and a step is formed between the upper part and the lower part.

According to a second aspect of the present invention , each of the lower electrode, the ferroelectric film, and the upper electrode is tapered.
A semiconductor device stacked so as to form an outer peripheral end having a shape of a cross section , wherein a portion located at an upper portion of each portion of the lower electrode, the ferroelectric film, and the upper electrode is a portion located at a lower portion And a step formed between the upper part and the lower part.

According to a third aspect of the present invention, at least one of the upper electrode and the lower electrode is made of Pt, Au, Pb, Mo, Ti, W, Pd.
Alternatively, it is characterized by being any of these compounds. According to a fourth aspect of the present invention, in the semiconductor device, the ferroelectric film is PZT (Pb (Zr, Ti) O ₃ ),
PLZT ((Pb, La) (Zr, Ti) O ₃ ), Ti
It is characterized by containing BaO ₃ , SrTiO ₃ , or Ta ₂ O ₅ as a main component.

[0009]

According to the above structure of the present invention, the resist pattern of the lower electrode covers only the flat portion and the upper electrode portion of the ferroelectric film, and the resist pattern of the ferroelectric film or the first lower portion thereunder. When the interlayer insulating film has a taper, it does not overlap the taper, so that it is possible to obtain an etched shape without re-deposition on the resist side wall of the object to be etched.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 is an explanatory diagram of a first embodiment of the present invention. As shown in FIG. 1A, Pt (4000 angstroms) as a lower electrode film, PZT (5000 angstroms) as a ferroelectric film, and an upper electrode film are formed on a flat first interlayer insulating film on a semiconductor substrate by sputtering. Of Au (2000 angstroms) is laminated. Thereafter, a photoresist is applied to a thickness of 1.5 μm, baked at 180 ° C. after exposure and development, and then the upper electrode is etched by ion milling at 800 V and 700 mA. Next, the ferroelectric film is etched by ion milling through the same steps of resist application, exposure, development, and baking as in the etching of the upper electrode (FIG. 1B).

Thereafter, the photoresist is exposed and developed by using a mask in which the lower electrode resist pattern is set to be about 1 μm inside the ferroelectric pattern (FIG. 1).
(C)), baking at 180 ° C. At this time, as shown in FIG. 1D, the resist is on the flat portion of the ferroelectric film, and the taper angle is 70 degrees or less. Thereafter, etching was performed at 800 V, 700 mA for about 10 minutes by an ion milling apparatus. As a result, FIG.
As shown in (e), an etched shape without reprecipitation on the side wall of the resist was obtained. In this embodiment, since the resist is in the form of a ferroelectric film, the Pt of the lower electrode is etched by the self-alignment effect of the ferroelectric film. The effect of smoothing like 1 (e) was also confirmed.

The second embodiment is an example in which the present invention is applied to etching of a ferroelectric capacitor on a step. FIG.
As shown in (a), a lower electrode film (Pt: 40) laminated by sputtering on a first interlayer insulating film on a semiconductor substrate.
00 angstroms), ferroelectric film (PZT: 500
0 Å) and upper electrode film (Au: 2000)
(Angstrom), the upper electrode and then the ferroelectric film are etched by ion milling etching (FIG. 2B). Also in these steps, as in the first embodiment, it is assumed that the resist is baked at 180 ° C. after the development and is reflowed.

Thereafter, the photoresist is exposed and developed using a mask in which the lower electrode resist pattern is set to be about 1 μm inside the ferroelectric pattern (FIG. 2).
(C)), baking at 180 ° C. At this time, as shown in FIG. 2D, the resist is on the flat portion of the ferroelectric film, and the taper angle is 70 degrees or less. Thereafter, etching was performed at 800 V, 700 mA for about 10 minutes using an ion milling apparatus, and an etched shape as shown in FIG. 2E without reprecipitation on the resist side wall was obtained.

In the above embodiment, since the resist is on the ferroelectric film as described above, even if a sidewall deposition film is formed, the sidewall deposition film is made of a ferroelectric material. This also has an effect that it cannot be a cause of disconnection or short circuit. In the above embodiment, Pt
Although the case where the ferroelectric film is laminated on the electrode has been described,
According to the present invention, the present invention can be applied to an electrode made of a metal such as Au, Pb, Mo, Ti, W, and Pd or a compound thereof and a high dielectric film such as Ta2O5.

[0016]

As described above, according to the lower electrode pattern forming method of the present invention, an etched shape without re-deposition on the resist side wall of the object to be etched can be obtained without hindering miniaturization.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a side wall deposition film according to the related art.

FIG. 4 is a cross-sectional view of a conventional technique after removing a photoresist from a sidewall deposition film.

FIG. 5 is a mask pattern diagram of a lower electrode according to the related art.

FIG. 6 is a mask pattern diagram of a lower electrode which has been attempted by the inventor in the prior art.

FIG. 7 is a cross-sectional view of a mask pattern of a lower electrode, which has been attempted by the inventor when a misalignment occurs in a conventional technique.

[Explanation of symbols]

Upper electrode: 101, 201, 502, 602, 702 Ferroelectric film: 102, 202, 503, 603, 70
3 Lower electrode: 103, 203, 504, 604, 704 First interlayer insulating film: 104, 204, 505, 60
5, 705 Semiconductor substrate: 105, 205, 304, 403, 50
6, 606, 706 Re-deposits of the object to be etched: 203, 303, 402; film to be etched: 202, 302, 401; photoresist: 106, 206, 301, 501;
601, 701

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108

Claims (4)

(57) [Claims] 1. Each of a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film has a tapered cross-sectional shape on a semiconductor substrate. Have
A semiconductor device stacked so as to form an outer peripheral edge , wherein at least one of the state of the lower electrode and the ferroelectric film, the state of the ferroelectric film and the upper electrode, and the state of the lower electrode and the upper electrode 3. The semiconductor device according to claim 1, wherein an upper portion is formed smaller than a lower portion, and a step is formed between the upper portion and the lower portion. 2. Each part of a lower electrode, a ferroelectric film, and an upper electrode
A semiconductor device which is stacked so as to form an outer peripheral end having a tapered cross-sectional shape , wherein, among the respective portions of the lower electrode, the ferroelectric film, and the upper electrode, a portion located at an upper portion is located at a lower portion. A semiconductor device, wherein the semiconductor device is formed to be smaller than a located portion, and a step is formed between the upper portion and the lower portion. 3. At least one of the upper electrode and the lower electrode is made of Pt, Au, Pb, Mo, T
2. The semiconductor device according to claim 1, wherein the semiconductor device is any one of i, W, Pd and a compound thereof. 4. The method according to claim 1, wherein the ferroelectric film is made of PZT (Pb (Z
r, Ti) O ₃ ), PLZT ((Pb, La) (Zr,
Ti) O ₃ ), TiBaO ₃ , SrTiO ₃ , or T
_3. The semiconductor device according to claim 1, wherein any one of a ₂ O ₅ is a main component.