JP2000068258A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an etching shape without a side-wall deposition film as a reattached etching film to a sidewall of a resist, without disturbing minute patterning in a non-reactive sputtering etching step. SOLUTION: A non-reactive sputtering etching method includes a step for etching after a photoresist layer 106 as a mask material is formed on an inner side of a step formed on an etching film 102, a step for baking at 180 to 200 deg.C after the photoresist is exposed and developed, and a step for etching without reactive sputtering.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device,
More particularly, the present invention relates to a ferroelectric memory etching process using ion milling.

[0002]

2. Description of the Related Art A ferroelectric has a characteristic that it has a large relative permittivity and has spontaneous polarization, and can be used as a capacitor material in a semiconductor memory. However, Pb
Ferroelectrics such as TiO3, PZT, PLZT and Pt, T
In an etching process using a photoresist of an electrode material such as i, Au, Pd or a compound thereof, the above materials are usually difficult to perform reactive etching, and ion milling has been regarded as the most effective etching method. Ion milling is a method of physically and anisotropically sputter-etching accelerated argon ions, but because of its strong anisotropy and the low reactivity of the material, the material to be etched hardly volatilizes. A part of the object to be etched adheres to the side wall of the resist after being etched to form a side wall deposition film as shown in FIG. The sidewall deposition film remains in the shape shown in FIG. 4 without being removed in the subsequent resist stripping step. Therefore, the side wall deposited film adversely affects the coverage of the interlayer insulating film in the subsequent step of forming the second interlayer insulating film. Further, when the side wall deposited film is conductive, May cause a short circuit or disconnection of the wiring.

After the resist is exposed to light and developed, the resist is reflowed by baking at a temperature of 130 ° C. to 200 ° C., and the resist is vertically tapered by tapering its shape. Has been devised not to have the side wall, and to have the effect of etching the object to be etched once attached to the resist side wall by argon ions coming later, and consequently not to leave the side wall deposition film.

However, in the etching process of the lower electrode after the etching of the ferroelectric film, conventionally, as shown in FIG. 5, the pattern of the lower electrode is about 1 μm outside one side of the mask pattern of the ferroelectric film. Therefore, it has been a great barrier in miniaturization due to the high integration of semiconductor devices. Therefore, the inventor of the present invention has tried a structure in which the pattern widths of the ferroelectric film and the lower electrode film are matched as shown in FIG. However, in a structure in which the pattern widths of the ferroelectric film and the lower electrode film match, the resist is applied to the tapered portion of the side wall of the ferroelectric film due to misalignment, as shown in FIG. 20
After the registry flow at 0 ° C., the shape of the resist was such that the taper angle exceeded 90 degrees, which was called an overhang as shown in FIG. 7B in some cases, and the sidewall deposition film was generated.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a method of etching a lower electrode after etching a ferroelectric film without obstructing miniaturization. An object of the present invention is to provide an etched shape without re-deposition on the side wall of the resist.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a photoresist layer as a mask material is formed inside a step formed on a film to be etched in sputter etching without using reactivity. Etching, and after exposure and development of the photoresist,
It is characterized by comprising a step of baking at a temperature of 00 ° C. and a sputter etching step without using reactivity.

Here, the film to be etched is Pt, A
u, Pb, Mo, Ti, W, Pd or any of these compounds.

The step formed on the film to be etched is PZT (Pb (Zr, Ti) O3), PLZ
T ((Pb, La) (Zr, Ti) O3), TiBaO
3, characterized in that any one of SrTiO3 is a main component.

[0009]

According to the above structure of the present invention, the resist pattern of the lower electrode covers only the flat portion and the upper electrode portion of the ferroelectric film, and the resist pattern of the ferroelectric film or the first lower portion thereunder. When the interlayer insulating film has a taper, it does not overlap the taper, so that it is possible to obtain an etched shape without re-deposition on the resist side wall of the object to be etched.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 is an explanatory diagram of a first embodiment of the present invention. As shown in FIG. 1A, Pt (4000 angstroms) as a lower electrode film, PZT (5000 angstroms) as a ferroelectric film, and an upper electrode film are formed on a flat first interlayer insulating film on a semiconductor substrate by sputtering. Of Au (2000 angstroms) is laminated. Thereafter, a photoresist is applied to a thickness of 1.5 μm, baked at 180 ° C. after exposure and development, and then the upper electrode is etched by ion milling at 800 V and 700 mA. Next, the ferroelectric film is etched by ion milling through the same steps of resist application, exposure, development, and baking as in the etching of the upper electrode (FIG. 1B).

Thereafter, the photoresist is exposed and developed by using a mask in which the lower electrode resist pattern is set to be about 1 μm inside the ferroelectric pattern (FIG. 1).
(C)), baking at 180 ° C. At this time, as shown in FIG. 1D, the resist is on the flat portion of the ferroelectric film, and the taper angle is 70 degrees or less. Thereafter, etching was performed at 800 V, 700 mA for about 10 minutes by an ion milling apparatus. As a result, FIG.
As shown in (e), an etched shape without reprecipitation on the side wall of the resist was obtained. In this embodiment, since the resist is in the form of a ferroelectric film, the Pt of the lower electrode is etched by the self-alignment effect of the ferroelectric film. The effect of smoothing like 1 (e) was also confirmed.

The second embodiment is an example in which the present invention is applied to etching of a ferroelectric capacitor on a step. FIG.
As shown in (a), a lower electrode film (Pt: 40) laminated by sputtering on a first interlayer insulating film on a semiconductor substrate.
00 angstroms), ferroelectric film (PZT: 500
0 Å) and upper electrode film (Au: 2000)
(Angstrom), the upper electrode and then the ferroelectric film are etched by ion milling etching (FIG. 2B). Also in these steps, as in the first embodiment, it is assumed that the resist is baked at 180 ° C. after the development and is reflowed.

Thereafter, the photoresist is exposed and developed using a mask in which the lower electrode resist pattern is set to be about 1 μm inside the ferroelectric pattern (FIG. 2).
(C)), baking at 180 ° C. At this time, as shown in FIG. 2D, the resist is on the flat portion of the ferroelectric film, and the taper angle is 70 degrees or less. Thereafter, etching was performed at 800 V, 700 mA for about 10 minutes using an ion milling apparatus, and an etched shape as shown in FIG. 2E without reprecipitation on the resist side wall was obtained.

In the above embodiment, since the resist is on the ferroelectric film as described above, even if a sidewall deposition film is formed, the sidewall deposition film is made of a ferroelectric material. This also has an effect that it cannot be a cause of disconnection or short circuit. In the above embodiment, Pt
Although the case where the ferroelectric film is laminated on the electrode has been described,
According to the present invention, the present invention can be applied to an electrode made of a metal such as Au, Pb, Mo, Ti, W, and Pd or a compound thereof and a high dielectric film such as Ta2O5.

[0016]

As described above, according to the lower electrode pattern forming method of the present invention, an etched shape without re-deposition on the resist side wall of the object to be etched can be obtained without hindering miniaturization.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a side wall deposition film according to the related art.

FIG. 4 is a cross-sectional view of a conventional technique after removing a photoresist from a sidewall deposition film.

FIG. 5 is a mask pattern diagram of a lower electrode according to the related art.

FIG. 6 is a mask pattern diagram of a lower electrode which has been attempted by the inventor in the prior art.

FIG. 7 is a cross-sectional view of a mask pattern of a lower electrode, which has been attempted by the inventor when a misalignment occurs in a conventional technique.

[Explanation of symbols]

Upper electrode: 101, 201, 502, 602, 702 Ferroelectric film: 102, 202, 503, 603, 70
3 Lower electrode: 103, 203, 504, 604, 704 First interlayer insulating film: 104, 204, 505, 60
5, 705 Semiconductor substrate: 105, 205, 304, 403, 50
6, 606, 706 Re-deposits of the object to be etched: 203, 303, 402; film to be etched: 202, 302, 401; photoresist: 106, 206, 301, 501;
601, 701

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[Procedure amendment]

[Submission date] July 26, 1999 (1999.7.2)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a step of laminating a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate, the step of laminating the upper electrode, the ferroelectric film, A step of performing etching on the lower electrode, wherein the step of performing the etching is performed a plurality of times. Further, as another method of manufacturing a semiconductor device according to the present invention, there is provided a step of laminating each of members constituting a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate; And performing a plurality of etchings so that the number of etchings becomes equal to the number of etchings. Further, as still another method of manufacturing a semiconductor device according to the present invention, a step of laminating each of members constituting a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate, and etching conditions for the members are performed. It is characterized by performing etching instead.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8242

Claims (3)

[Claims] 1. A step of forming and etching a photoresist layer as a mask material inside a step formed on a film to be etched in sputter etching without using reactivity, and exposing and developing the photoresist, 180 ~
A method for manufacturing a semiconductor device, comprising: a step of baking at a temperature of 200 ° C .; and a step of sputter etching without using reactivity. 2. The method according to claim 1, wherein the film to be etched is Pt, Au, Pb,
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is Mo, Ti, W, Pd, or any of these compounds. 3. The method according to claim 1, wherein the step formed on the film to be etched is PZT (Pb (Zr, Ti) O3), PLZT.
((Pb, La) (Zr, Ti) O3), TiBaO3,
3. The method for manufacturing a semiconductor device according to claim 1, wherein one of SrTiO3 and Ta2O5 is a main component.